1/*
2 * CS5536 General timer functions
3 *
4 * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology
5 * Author: Yanhua, yanh@lemote.com
6 *
7 * Copyright (C) 2009 Lemote Inc.
8 * Author: Wu zhangjin, wuzhangjin@gmail.com
9 *
10 * Reference: AMD Geode(TM) CS5536 Companion Device Data Book
11 *
12 *  This program is free software; you can redistribute	 it and/or modify it
13 *  under  the terms of	 the GNU General  Public License as published by the
14 *  Free Software Foundation;  either version 2 of the	License, or (at your
15 *  option) any later version.
16 */
17
18#include <linux/io.h>
19#include <linux/init.h>
20#include <linux/module.h>
21#include <linux/jiffies.h>
22#include <linux/spinlock.h>
23#include <linux/interrupt.h>
24#include <linux/clockchips.h>
25
26#include <asm/time.h>
27
28#include <cs5536/cs5536_mfgpt.h>
29
30static DEFINE_RAW_SPINLOCK(mfgpt_lock);
31
32static u32 mfgpt_base;
33
34/*
35 * Initialize the MFGPT timer.
36 *
37 * This is also called after resume to bring the MFGPT into operation again.
38 */
39
40/* disable counter */
41void disable_mfgpt0_counter(void)
42{
43	outw(inw(MFGPT0_SETUP) & 0x7fff, MFGPT0_SETUP);
44}
45EXPORT_SYMBOL(disable_mfgpt0_counter);
46
47/* enable counter, comparator2 to event mode, 14.318MHz clock */
48void enable_mfgpt0_counter(void)
49{
50	outw(0xe310, MFGPT0_SETUP);
51}
52EXPORT_SYMBOL(enable_mfgpt0_counter);
53
54static void init_mfgpt_timer(enum clock_event_mode mode,
55			     struct clock_event_device *evt)
56{
57	raw_spin_lock(&mfgpt_lock);
58
59	switch (mode) {
60	case CLOCK_EVT_MODE_PERIODIC:
61		outw(COMPARE, MFGPT0_CMP2);	/* set comparator2 */
62		outw(0, MFGPT0_CNT);	/* set counter to 0 */
63		enable_mfgpt0_counter();
64		break;
65
66	case CLOCK_EVT_MODE_SHUTDOWN:
67	case CLOCK_EVT_MODE_UNUSED:
68		if (evt->mode == CLOCK_EVT_MODE_PERIODIC ||
69		    evt->mode == CLOCK_EVT_MODE_ONESHOT)
70			disable_mfgpt0_counter();
71		break;
72
73	case CLOCK_EVT_MODE_ONESHOT:
74		/* The oneshot mode have very high deviation, Not use it! */
75		break;
76
77	case CLOCK_EVT_MODE_RESUME:
78		/* Nothing to do here */
79		break;
80	}
81	raw_spin_unlock(&mfgpt_lock);
82}
83
84static struct clock_event_device mfgpt_clockevent = {
85	.name = "mfgpt",
86	.features = CLOCK_EVT_FEAT_PERIODIC,
87	.set_mode = init_mfgpt_timer,
88	.irq = CS5536_MFGPT_INTR,
89};
90
91static irqreturn_t timer_interrupt(int irq, void *dev_id)
92{
93	u32 basehi;
94
95	/*
96	 * get MFGPT base address
97	 *
98	 * NOTE: do not remove me, it's need for the value of mfgpt_base is
99	 * variable
100	 */
101	_rdmsr(DIVIL_MSR_REG(DIVIL_LBAR_MFGPT), &basehi, &mfgpt_base);
102
103	/* ack */
104	outw(inw(MFGPT0_SETUP) | 0x4000, MFGPT0_SETUP);
105
106	mfgpt_clockevent.event_handler(&mfgpt_clockevent);
107
108	return IRQ_HANDLED;
109}
110
111static struct irqaction irq5 = {
112	.handler = timer_interrupt,
113	.flags = IRQF_NOBALANCING | IRQF_TIMER,
114	.name = "timer"
115};
116
117/*
118 * Initialize the conversion factor and the min/max deltas of the clock event
119 * structure and register the clock event source with the framework.
120 */
121void __init setup_mfgpt0_timer(void)
122{
123	u32 basehi;
124	struct clock_event_device *cd = &mfgpt_clockevent;
125	unsigned int cpu = smp_processor_id();
126
127	cd->cpumask = cpumask_of(cpu);
128	clockevent_set_clock(cd, MFGPT_TICK_RATE);
129	cd->max_delta_ns = clockevent_delta2ns(0xffff, cd);
130	cd->min_delta_ns = clockevent_delta2ns(0xf, cd);
131
132	/* Enable MFGPT0 Comparator 2 Output to the Interrupt Mapper */
133	_wrmsr(DIVIL_MSR_REG(MFGPT_IRQ), 0, 0x100);
134
135	/* Enable Interrupt Gate 5 */
136	_wrmsr(DIVIL_MSR_REG(PIC_ZSEL_LOW), 0, 0x50000);
137
138	/* get MFGPT base address */
139	_rdmsr(DIVIL_MSR_REG(DIVIL_LBAR_MFGPT), &basehi, &mfgpt_base);
140
141	clockevents_register_device(cd);
142
143	setup_irq(CS5536_MFGPT_INTR, &irq5);
144}
145
146/*
147 * Since the MFGPT overflows every tick, its not very useful
148 * to just read by itself. So use jiffies to emulate a free
149 * running counter:
150 */
151static cycle_t mfgpt_read(struct clocksource *cs)
152{
153	unsigned long flags;
154	int count;
155	u32 jifs;
156	static int old_count;
157	static u32 old_jifs;
158
159	raw_spin_lock_irqsave(&mfgpt_lock, flags);
160	/*
161	 * Although our caller may have the read side of xtime_lock,
162	 * this is now a seqlock, and we are cheating in this routine
163	 * by having side effects on state that we cannot undo if
164	 * there is a collision on the seqlock and our caller has to
165	 * retry.  (Namely, old_jifs and old_count.)  So we must treat
166	 * jiffies as volatile despite the lock.  We read jiffies
167	 * before latching the timer count to guarantee that although
168	 * the jiffies value might be older than the count (that is,
169	 * the counter may underflow between the last point where
170	 * jiffies was incremented and the point where we latch the
171	 * count), it cannot be newer.
172	 */
173	jifs = jiffies;
174	/* read the count */
175	count = inw(MFGPT0_CNT);
176
177	/*
178	 * It's possible for count to appear to go the wrong way for this
179	 * reason:
180	 *
181	 *  The timer counter underflows, but we haven't handled the resulting
182	 *  interrupt and incremented jiffies yet.
183	 *
184	 * Previous attempts to handle these cases intelligently were buggy, so
185	 * we just do the simple thing now.
186	 */
187	if (count < old_count && jifs == old_jifs)
188		count = old_count;
189
190	old_count = count;
191	old_jifs = jifs;
192
193	raw_spin_unlock_irqrestore(&mfgpt_lock, flags);
194
195	return (cycle_t) (jifs * COMPARE) + count;
196}
197
198static struct clocksource clocksource_mfgpt = {
199	.name = "mfgpt",
200	.rating = 120, /* Functional for real use, but not desired */
201	.read = mfgpt_read,
202	.mask = CLOCKSOURCE_MASK(32),
203};
204
205int __init init_mfgpt_clocksource(void)
206{
207	if (num_possible_cpus() > 1)	/* MFGPT does not scale! */
208		return 0;
209
210	return clocksource_register_hz(&clocksource_mfgpt, MFGPT_TICK_RATE);
211}
212
213arch_initcall(init_mfgpt_clocksource);
214