1/* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Code to handle x86 style IRQs plus some generic interrupt stuff. 7 * 8 * Copyright (C) 1992 Linus Torvalds 9 * Copyright (C) 1994 - 2000 Ralf Baechle 10 */ 11#include <linux/delay.h> 12#include <linux/init.h> 13#include <linux/ioport.h> 14#include <linux/interrupt.h> 15#include <linux/irqdomain.h> 16#include <linux/kernel.h> 17#include <linux/spinlock.h> 18#include <linux/syscore_ops.h> 19#include <linux/irq.h> 20 21#include <asm/i8259.h> 22#include <asm/io.h> 23 24/* 25 * This is the 'legacy' 8259A Programmable Interrupt Controller, 26 * present in the majority of PC/AT boxes. 27 * plus some generic x86 specific things if generic specifics makes 28 * any sense at all. 29 * this file should become arch/i386/kernel/irq.c when the old irq.c 30 * moves to arch independent land 31 */ 32 33static int i8259A_auto_eoi = -1; 34DEFINE_RAW_SPINLOCK(i8259A_lock); 35static void disable_8259A_irq(struct irq_data *d); 36static void enable_8259A_irq(struct irq_data *d); 37static void mask_and_ack_8259A(struct irq_data *d); 38static void init_8259A(int auto_eoi); 39 40static struct irq_chip i8259A_chip = { 41 .name = "XT-PIC", 42 .irq_mask = disable_8259A_irq, 43 .irq_disable = disable_8259A_irq, 44 .irq_unmask = enable_8259A_irq, 45 .irq_mask_ack = mask_and_ack_8259A, 46}; 47 48/* 49 * 8259A PIC functions to handle ISA devices: 50 */ 51 52/* 53 * This contains the irq mask for both 8259A irq controllers, 54 */ 55static unsigned int cached_irq_mask = 0xffff; 56 57#define cached_master_mask (cached_irq_mask) 58#define cached_slave_mask (cached_irq_mask >> 8) 59 60static void disable_8259A_irq(struct irq_data *d) 61{ 62 unsigned int mask, irq = d->irq - I8259A_IRQ_BASE; 63 unsigned long flags; 64 65 mask = 1 << irq; 66 raw_spin_lock_irqsave(&i8259A_lock, flags); 67 cached_irq_mask |= mask; 68 if (irq & 8) 69 outb(cached_slave_mask, PIC_SLAVE_IMR); 70 else 71 outb(cached_master_mask, PIC_MASTER_IMR); 72 raw_spin_unlock_irqrestore(&i8259A_lock, flags); 73} 74 75static void enable_8259A_irq(struct irq_data *d) 76{ 77 unsigned int mask, irq = d->irq - I8259A_IRQ_BASE; 78 unsigned long flags; 79 80 mask = ~(1 << irq); 81 raw_spin_lock_irqsave(&i8259A_lock, flags); 82 cached_irq_mask &= mask; 83 if (irq & 8) 84 outb(cached_slave_mask, PIC_SLAVE_IMR); 85 else 86 outb(cached_master_mask, PIC_MASTER_IMR); 87 raw_spin_unlock_irqrestore(&i8259A_lock, flags); 88} 89 90int i8259A_irq_pending(unsigned int irq) 91{ 92 unsigned int mask; 93 unsigned long flags; 94 int ret; 95 96 irq -= I8259A_IRQ_BASE; 97 mask = 1 << irq; 98 raw_spin_lock_irqsave(&i8259A_lock, flags); 99 if (irq < 8) 100 ret = inb(PIC_MASTER_CMD) & mask; 101 else 102 ret = inb(PIC_SLAVE_CMD) & (mask >> 8); 103 raw_spin_unlock_irqrestore(&i8259A_lock, flags); 104 105 return ret; 106} 107 108void make_8259A_irq(unsigned int irq) 109{ 110 disable_irq_nosync(irq); 111 irq_set_chip_and_handler(irq, &i8259A_chip, handle_level_irq); 112 enable_irq(irq); 113} 114 115/* 116 * This function assumes to be called rarely. Switching between 117 * 8259A registers is slow. 118 * This has to be protected by the irq controller spinlock 119 * before being called. 120 */ 121static inline int i8259A_irq_real(unsigned int irq) 122{ 123 int value; 124 int irqmask = 1 << irq; 125 126 if (irq < 8) { 127 outb(0x0B, PIC_MASTER_CMD); /* ISR register */ 128 value = inb(PIC_MASTER_CMD) & irqmask; 129 outb(0x0A, PIC_MASTER_CMD); /* back to the IRR register */ 130 return value; 131 } 132 outb(0x0B, PIC_SLAVE_CMD); /* ISR register */ 133 value = inb(PIC_SLAVE_CMD) & (irqmask >> 8); 134 outb(0x0A, PIC_SLAVE_CMD); /* back to the IRR register */ 135 return value; 136} 137 138/* 139 * Careful! The 8259A is a fragile beast, it pretty 140 * much _has_ to be done exactly like this (mask it 141 * first, _then_ send the EOI, and the order of EOI 142 * to the two 8259s is important! 143 */ 144static void mask_and_ack_8259A(struct irq_data *d) 145{ 146 unsigned int irqmask, irq = d->irq - I8259A_IRQ_BASE; 147 unsigned long flags; 148 149 irqmask = 1 << irq; 150 raw_spin_lock_irqsave(&i8259A_lock, flags); 151 /* 152 * Lightweight spurious IRQ detection. We do not want 153 * to overdo spurious IRQ handling - it's usually a sign 154 * of hardware problems, so we only do the checks we can 155 * do without slowing down good hardware unnecessarily. 156 * 157 * Note that IRQ7 and IRQ15 (the two spurious IRQs 158 * usually resulting from the 8259A-1|2 PICs) occur 159 * even if the IRQ is masked in the 8259A. Thus we 160 * can check spurious 8259A IRQs without doing the 161 * quite slow i8259A_irq_real() call for every IRQ. 162 * This does not cover 100% of spurious interrupts, 163 * but should be enough to warn the user that there 164 * is something bad going on ... 165 */ 166 if (cached_irq_mask & irqmask) 167 goto spurious_8259A_irq; 168 cached_irq_mask |= irqmask; 169 170handle_real_irq: 171 if (irq & 8) { 172 inb(PIC_SLAVE_IMR); /* DUMMY - (do we need this?) */ 173 outb(cached_slave_mask, PIC_SLAVE_IMR); 174 outb(0x60+(irq&7), PIC_SLAVE_CMD);/* 'Specific EOI' to slave */ 175 outb(0x60+PIC_CASCADE_IR, PIC_MASTER_CMD); /* 'Specific EOI' to master-IRQ2 */ 176 } else { 177 inb(PIC_MASTER_IMR); /* DUMMY - (do we need this?) */ 178 outb(cached_master_mask, PIC_MASTER_IMR); 179 outb(0x60+irq, PIC_MASTER_CMD); /* 'Specific EOI to master */ 180 } 181 raw_spin_unlock_irqrestore(&i8259A_lock, flags); 182 return; 183 184spurious_8259A_irq: 185 /* 186 * this is the slow path - should happen rarely. 187 */ 188 if (i8259A_irq_real(irq)) 189 /* 190 * oops, the IRQ _is_ in service according to the 191 * 8259A - not spurious, go handle it. 192 */ 193 goto handle_real_irq; 194 195 { 196 static int spurious_irq_mask; 197 /* 198 * At this point we can be sure the IRQ is spurious, 199 * lets ACK and report it. [once per IRQ] 200 */ 201 if (!(spurious_irq_mask & irqmask)) { 202 printk(KERN_DEBUG "spurious 8259A interrupt: IRQ%d.\n", irq); 203 spurious_irq_mask |= irqmask; 204 } 205 atomic_inc(&irq_err_count); 206 /* 207 * Theoretically we do not have to handle this IRQ, 208 * but in Linux this does not cause problems and is 209 * simpler for us. 210 */ 211 goto handle_real_irq; 212 } 213} 214 215static void i8259A_resume(void) 216{ 217 if (i8259A_auto_eoi >= 0) 218 init_8259A(i8259A_auto_eoi); 219} 220 221static void i8259A_shutdown(void) 222{ 223 /* Put the i8259A into a quiescent state that 224 * the kernel initialization code can get it 225 * out of. 226 */ 227 if (i8259A_auto_eoi >= 0) { 228 outb(0xff, PIC_MASTER_IMR); /* mask all of 8259A-1 */ 229 outb(0xff, PIC_SLAVE_IMR); /* mask all of 8259A-2 */ 230 } 231} 232 233static struct syscore_ops i8259_syscore_ops = { 234 .resume = i8259A_resume, 235 .shutdown = i8259A_shutdown, 236}; 237 238static int __init i8259A_init_sysfs(void) 239{ 240 register_syscore_ops(&i8259_syscore_ops); 241 return 0; 242} 243 244device_initcall(i8259A_init_sysfs); 245 246static void init_8259A(int auto_eoi) 247{ 248 unsigned long flags; 249 250 i8259A_auto_eoi = auto_eoi; 251 252 raw_spin_lock_irqsave(&i8259A_lock, flags); 253 254 outb(0xff, PIC_MASTER_IMR); /* mask all of 8259A-1 */ 255 outb(0xff, PIC_SLAVE_IMR); /* mask all of 8259A-2 */ 256 257 /* 258 * outb_p - this has to work on a wide range of PC hardware. 259 */ 260 outb_p(0x11, PIC_MASTER_CMD); /* ICW1: select 8259A-1 init */ 261 outb_p(I8259A_IRQ_BASE + 0, PIC_MASTER_IMR); /* ICW2: 8259A-1 IR0 mapped to I8259A_IRQ_BASE + 0x00 */ 262 outb_p(1U << PIC_CASCADE_IR, PIC_MASTER_IMR); /* 8259A-1 (the master) has a slave on IR2 */ 263 if (auto_eoi) /* master does Auto EOI */ 264 outb_p(MASTER_ICW4_DEFAULT | PIC_ICW4_AEOI, PIC_MASTER_IMR); 265 else /* master expects normal EOI */ 266 outb_p(MASTER_ICW4_DEFAULT, PIC_MASTER_IMR); 267 268 outb_p(0x11, PIC_SLAVE_CMD); /* ICW1: select 8259A-2 init */ 269 outb_p(I8259A_IRQ_BASE + 8, PIC_SLAVE_IMR); /* ICW2: 8259A-2 IR0 mapped to I8259A_IRQ_BASE + 0x08 */ 270 outb_p(PIC_CASCADE_IR, PIC_SLAVE_IMR); /* 8259A-2 is a slave on master's IR2 */ 271 outb_p(SLAVE_ICW4_DEFAULT, PIC_SLAVE_IMR); /* (slave's support for AEOI in flat mode is to be investigated) */ 272 if (auto_eoi) 273 /* 274 * In AEOI mode we just have to mask the interrupt 275 * when acking. 276 */ 277 i8259A_chip.irq_mask_ack = disable_8259A_irq; 278 else 279 i8259A_chip.irq_mask_ack = mask_and_ack_8259A; 280 281 udelay(100); /* wait for 8259A to initialize */ 282 283 outb(cached_master_mask, PIC_MASTER_IMR); /* restore master IRQ mask */ 284 outb(cached_slave_mask, PIC_SLAVE_IMR); /* restore slave IRQ mask */ 285 286 raw_spin_unlock_irqrestore(&i8259A_lock, flags); 287} 288 289/* 290 * IRQ2 is cascade interrupt to second interrupt controller 291 */ 292static struct irqaction irq2 = { 293 .handler = no_action, 294 .name = "cascade", 295 .flags = IRQF_NO_THREAD, 296}; 297 298static struct resource pic1_io_resource = { 299 .name = "pic1", 300 .start = PIC_MASTER_CMD, 301 .end = PIC_MASTER_IMR, 302 .flags = IORESOURCE_BUSY 303}; 304 305static struct resource pic2_io_resource = { 306 .name = "pic2", 307 .start = PIC_SLAVE_CMD, 308 .end = PIC_SLAVE_IMR, 309 .flags = IORESOURCE_BUSY 310}; 311 312static int i8259A_irq_domain_map(struct irq_domain *d, unsigned int virq, 313 irq_hw_number_t hw) 314{ 315 irq_set_chip_and_handler(virq, &i8259A_chip, handle_level_irq); 316 irq_set_probe(virq); 317 return 0; 318} 319 320static struct irq_domain_ops i8259A_ops = { 321 .map = i8259A_irq_domain_map, 322 .xlate = irq_domain_xlate_onecell, 323}; 324 325/* 326 * On systems with i8259-style interrupt controllers we assume for 327 * driver compatibility reasons interrupts 0 - 15 to be the i8259 328 * interrupts even if the hardware uses a different interrupt numbering. 329 */ 330void __init init_i8259_irqs(void) 331{ 332 struct irq_domain *domain; 333 334 insert_resource(&ioport_resource, &pic1_io_resource); 335 insert_resource(&ioport_resource, &pic2_io_resource); 336 337 init_8259A(0); 338 339 domain = irq_domain_add_legacy(NULL, 16, I8259A_IRQ_BASE, 0, 340 &i8259A_ops, NULL); 341 if (!domain) 342 panic("Failed to add i8259 IRQ domain"); 343 344 setup_irq(I8259A_IRQ_BASE + PIC_CASCADE_IR, &irq2); 345} 346