1 /*
2 * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
3 * JZ4740 platform IRQ support
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * You should have received a copy of the GNU General Public License along
11 * with this program; if not, write to the Free Software Foundation, Inc.,
12 * 675 Mass Ave, Cambridge, MA 02139, USA.
13 *
14 */
15
16 #include <linux/errno.h>
17 #include <linux/init.h>
18 #include <linux/types.h>
19 #include <linux/interrupt.h>
20 #include <linux/ioport.h>
21 #include <linux/timex.h>
22 #include <linux/slab.h>
23 #include <linux/delay.h>
24
25 #include <linux/debugfs.h>
26 #include <linux/seq_file.h>
27
28 #include <asm/io.h>
29 #include <asm/mipsregs.h>
30 #include <asm/irq_cpu.h>
31
32 #include <asm/mach-jz4740/base.h>
33 #include <asm/mach-jz4740/irq.h>
34
35 #include "irq.h"
36
37 static void __iomem *jz_intc_base;
38
39 #define JZ_REG_INTC_STATUS 0x00
40 #define JZ_REG_INTC_MASK 0x04
41 #define JZ_REG_INTC_SET_MASK 0x08
42 #define JZ_REG_INTC_CLEAR_MASK 0x0c
43 #define JZ_REG_INTC_PENDING 0x10
44
jz4740_cascade(int irq,void * data)45 static irqreturn_t jz4740_cascade(int irq, void *data)
46 {
47 uint32_t irq_reg;
48
49 irq_reg = readl(jz_intc_base + JZ_REG_INTC_PENDING);
50
51 if (irq_reg)
52 generic_handle_irq(__fls(irq_reg) + JZ4740_IRQ_BASE);
53
54 return IRQ_HANDLED;
55 }
56
jz4740_irq_set_mask(struct irq_chip_generic * gc,uint32_t mask)57 static void jz4740_irq_set_mask(struct irq_chip_generic *gc, uint32_t mask)
58 {
59 struct irq_chip_regs *regs = &gc->chip_types->regs;
60
61 writel(mask, gc->reg_base + regs->enable);
62 writel(~mask, gc->reg_base + regs->disable);
63 }
64
jz4740_irq_suspend(struct irq_data * data)65 void jz4740_irq_suspend(struct irq_data *data)
66 {
67 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
68 jz4740_irq_set_mask(gc, gc->wake_active);
69 }
70
jz4740_irq_resume(struct irq_data * data)71 void jz4740_irq_resume(struct irq_data *data)
72 {
73 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
74 jz4740_irq_set_mask(gc, gc->mask_cache);
75 }
76
77 static struct irqaction jz4740_cascade_action = {
78 .handler = jz4740_cascade,
79 .name = "JZ4740 cascade interrupt",
80 };
81
arch_init_irq(void)82 void __init arch_init_irq(void)
83 {
84 struct irq_chip_generic *gc;
85 struct irq_chip_type *ct;
86
87 mips_cpu_irq_init();
88
89 jz_intc_base = ioremap(JZ4740_INTC_BASE_ADDR, 0x14);
90
91 /* Mask all irqs */
92 writel(0xffffffff, jz_intc_base + JZ_REG_INTC_SET_MASK);
93
94 gc = irq_alloc_generic_chip("INTC", 1, JZ4740_IRQ_BASE, jz_intc_base,
95 handle_level_irq);
96
97 gc->wake_enabled = IRQ_MSK(32);
98
99 ct = gc->chip_types;
100 ct->regs.enable = JZ_REG_INTC_CLEAR_MASK;
101 ct->regs.disable = JZ_REG_INTC_SET_MASK;
102 ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
103 ct->chip.irq_mask = irq_gc_mask_disable_reg;
104 ct->chip.irq_mask_ack = irq_gc_mask_disable_reg;
105 ct->chip.irq_set_wake = irq_gc_set_wake;
106 ct->chip.irq_suspend = jz4740_irq_suspend;
107 ct->chip.irq_resume = jz4740_irq_resume;
108
109 irq_setup_generic_chip(gc, IRQ_MSK(32), 0, 0, IRQ_NOPROBE | IRQ_LEVEL);
110
111 setup_irq(2, &jz4740_cascade_action);
112 }
113
plat_irq_dispatch(void)114 asmlinkage void plat_irq_dispatch(void)
115 {
116 unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
117 if (pending & STATUSF_IP2)
118 do_IRQ(2);
119 else if (pending & STATUSF_IP3)
120 do_IRQ(3);
121 else
122 spurious_interrupt();
123 }
124
125 #ifdef CONFIG_DEBUG_FS
126
intc_seq_reg(struct seq_file * s,const char * name,unsigned int reg)127 static inline void intc_seq_reg(struct seq_file *s, const char *name,
128 unsigned int reg)
129 {
130 seq_printf(s, "%s:\t\t%08x\n", name, readl(jz_intc_base + reg));
131 }
132
intc_regs_show(struct seq_file * s,void * unused)133 static int intc_regs_show(struct seq_file *s, void *unused)
134 {
135 intc_seq_reg(s, "Status", JZ_REG_INTC_STATUS);
136 intc_seq_reg(s, "Mask", JZ_REG_INTC_MASK);
137 intc_seq_reg(s, "Pending", JZ_REG_INTC_PENDING);
138
139 return 0;
140 }
141
intc_regs_open(struct inode * inode,struct file * file)142 static int intc_regs_open(struct inode *inode, struct file *file)
143 {
144 return single_open(file, intc_regs_show, NULL);
145 }
146
147 static const struct file_operations intc_regs_operations = {
148 .open = intc_regs_open,
149 .read = seq_read,
150 .llseek = seq_lseek,
151 .release = single_release,
152 };
153
intc_debugfs_init(void)154 static int __init intc_debugfs_init(void)
155 {
156 (void) debugfs_create_file("jz_regs_intc", S_IFREG | S_IRUGO,
157 NULL, NULL, &intc_regs_operations);
158 return 0;
159 }
160 subsys_initcall(intc_debugfs_init);
161
162 #endif
163