1/***********************license start*************** 2 * Author: Cavium Networks 3 * 4 * Contact: support@caviumnetworks.com 5 * This file is part of the OCTEON SDK 6 * 7 * Copyright (c) 2003-2012 Cavium Networks 8 * 9 * This file is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License, Version 2, as 11 * published by the Free Software Foundation. 12 * 13 * This file is distributed in the hope that it will be useful, but 14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty 15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or 16 * NONINFRINGEMENT. See the GNU General Public License for more 17 * details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this file; if not, write to the Free Software 21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 22 * or visit http://www.gnu.org/licenses/. 23 * 24 * This file may also be available under a different license from Cavium. 25 * Contact Cavium Networks for more information 26 ***********************license end**************************************/ 27 28#ifndef __CVMX_GMXX_DEFS_H__ 29#define __CVMX_GMXX_DEFS_H__ 30 31static inline uint64_t CVMX_GMXX_BAD_REG(unsigned long block_id) 32{ 33 switch (cvmx_get_octeon_family()) { 34 case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 35 case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 36 case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 37 case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 38 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 39 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 40 return CVMX_ADD_IO_SEG(0x0001180008000518ull) + (block_id) * 0x8000000ull; 41 case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 42 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 43 case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 44 case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 45 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 46 return CVMX_ADD_IO_SEG(0x0001180008000518ull) + (block_id) * 0x8000000ull; 47 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 48 return CVMX_ADD_IO_SEG(0x0001180008000518ull) + (block_id) * 0x1000000ull; 49 } 50 return CVMX_ADD_IO_SEG(0x0001180008000518ull) + (block_id) * 0x8000000ull; 51} 52 53static inline uint64_t CVMX_GMXX_BIST(unsigned long block_id) 54{ 55 switch (cvmx_get_octeon_family()) { 56 case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 57 case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 58 case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 59 case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 60 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 61 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 62 return CVMX_ADD_IO_SEG(0x0001180008000400ull) + (block_id) * 0x8000000ull; 63 case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 64 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 65 case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 66 case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 67 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 68 return CVMX_ADD_IO_SEG(0x0001180008000400ull) + (block_id) * 0x8000000ull; 69 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 70 return CVMX_ADD_IO_SEG(0x0001180008000400ull) + (block_id) * 0x1000000ull; 71 } 72 return CVMX_ADD_IO_SEG(0x0001180008000400ull) + (block_id) * 0x8000000ull; 73} 74 75#define CVMX_GMXX_BPID_MAPX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000680ull) + (((offset) & 15) + ((block_id) & 7) * 0x200000ull) * 8) 76#define CVMX_GMXX_BPID_MSK(block_id) (CVMX_ADD_IO_SEG(0x0001180008000700ull) + ((block_id) & 7) * 0x1000000ull) 77static inline uint64_t CVMX_GMXX_CLK_EN(unsigned long block_id) 78{ 79 switch (cvmx_get_octeon_family()) { 80 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 81 case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 82 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 83 return CVMX_ADD_IO_SEG(0x00011800080007F0ull) + (block_id) * 0x8000000ull; 84 case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 85 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 86 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 87 return CVMX_ADD_IO_SEG(0x00011800080007F0ull) + (block_id) * 0x8000000ull; 88 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 89 return CVMX_ADD_IO_SEG(0x00011800080007F0ull) + (block_id) * 0x1000000ull; 90 } 91 return CVMX_ADD_IO_SEG(0x00011800080007F0ull) + (block_id) * 0x8000000ull; 92} 93 94#define CVMX_GMXX_EBP_DIS(block_id) (CVMX_ADD_IO_SEG(0x0001180008000608ull) + ((block_id) & 7) * 0x1000000ull) 95#define CVMX_GMXX_EBP_MSK(block_id) (CVMX_ADD_IO_SEG(0x0001180008000600ull) + ((block_id) & 7) * 0x1000000ull) 96static inline uint64_t CVMX_GMXX_HG2_CONTROL(unsigned long block_id) 97{ 98 switch (cvmx_get_octeon_family()) { 99 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 100 case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 101 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 102 return CVMX_ADD_IO_SEG(0x0001180008000550ull) + (block_id) * 0x8000000ull; 103 case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 104 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 105 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 106 return CVMX_ADD_IO_SEG(0x0001180008000550ull) + (block_id) * 0x8000000ull; 107 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 108 return CVMX_ADD_IO_SEG(0x0001180008000550ull) + (block_id) * 0x1000000ull; 109 } 110 return CVMX_ADD_IO_SEG(0x0001180008000550ull) + (block_id) * 0x8000000ull; 111} 112 113static inline uint64_t CVMX_GMXX_INF_MODE(unsigned long block_id) 114{ 115 switch (cvmx_get_octeon_family()) { 116 case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 117 case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 118 case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 119 case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 120 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 121 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 122 return CVMX_ADD_IO_SEG(0x00011800080007F8ull) + (block_id) * 0x8000000ull; 123 case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 124 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 125 case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 126 case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 127 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 128 return CVMX_ADD_IO_SEG(0x00011800080007F8ull) + (block_id) * 0x8000000ull; 129 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 130 return CVMX_ADD_IO_SEG(0x00011800080007F8ull) + (block_id) * 0x1000000ull; 131 } 132 return CVMX_ADD_IO_SEG(0x00011800080007F8ull) + (block_id) * 0x8000000ull; 133} 134 135static inline uint64_t CVMX_GMXX_NXA_ADR(unsigned long block_id) 136{ 137 switch (cvmx_get_octeon_family()) { 138 case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 139 case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 140 case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 141 case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 142 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 143 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 144 return CVMX_ADD_IO_SEG(0x0001180008000510ull) + (block_id) * 0x8000000ull; 145 case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 146 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 147 case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 148 case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 149 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 150 return CVMX_ADD_IO_SEG(0x0001180008000510ull) + (block_id) * 0x8000000ull; 151 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 152 return CVMX_ADD_IO_SEG(0x0001180008000510ull) + (block_id) * 0x1000000ull; 153 } 154 return CVMX_ADD_IO_SEG(0x0001180008000510ull) + (block_id) * 0x8000000ull; 155} 156 157#define CVMX_GMXX_PIPE_STATUS(block_id) (CVMX_ADD_IO_SEG(0x0001180008000760ull) + ((block_id) & 7) * 0x1000000ull) 158static inline uint64_t CVMX_GMXX_PRTX_CBFC_CTL(unsigned long offset, unsigned long block_id) 159{ 160 switch (cvmx_get_octeon_family()) { 161 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 162 case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 163 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 164 return CVMX_ADD_IO_SEG(0x0001180008000580ull) + (block_id) * 0x8000000ull; 165 case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 166 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 167 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 168 return CVMX_ADD_IO_SEG(0x0001180008000580ull) + (block_id) * 0x8000000ull; 169 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 170 return CVMX_ADD_IO_SEG(0x0001180008000580ull) + (block_id) * 0x1000000ull; 171 } 172 return CVMX_ADD_IO_SEG(0x0001180008000580ull) + (block_id) * 0x8000000ull; 173} 174 175static inline uint64_t CVMX_GMXX_PRTX_CFG(unsigned long offset, unsigned long block_id) 176{ 177 switch (cvmx_get_octeon_family()) { 178 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 179 return CVMX_ADD_IO_SEG(0x0001180008000010ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 180 case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 181 case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 182 return CVMX_ADD_IO_SEG(0x0001180008000010ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 183 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 184 case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 185 return CVMX_ADD_IO_SEG(0x0001180008000010ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 186 case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 187 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 188 case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 189 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 190 case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 191 return CVMX_ADD_IO_SEG(0x0001180008000010ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 192 case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 193 return CVMX_ADD_IO_SEG(0x0001180008000010ull) + ((offset) + (block_id) * 0x0ull) * 2048; 194 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 195 return CVMX_ADD_IO_SEG(0x0001180008000010ull) + ((offset) + (block_id) * 0x2000ull) * 2048; 196 } 197 return CVMX_ADD_IO_SEG(0x0001180008000010ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 198} 199 200#define CVMX_GMXX_RXAUI_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180008000740ull) + ((block_id) & 7) * 0x1000000ull) 201static inline uint64_t CVMX_GMXX_RXX_ADR_CAM0(unsigned long offset, unsigned long block_id) 202{ 203 switch (cvmx_get_octeon_family()) { 204 case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 205 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 206 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 207 return CVMX_ADD_IO_SEG(0x0001180008000180ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 208 case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 209 case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 210 return CVMX_ADD_IO_SEG(0x0001180008000180ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 211 case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 212 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 213 case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 214 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 215 case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 216 return CVMX_ADD_IO_SEG(0x0001180008000180ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 217 case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 218 return CVMX_ADD_IO_SEG(0x0001180008000180ull) + ((offset) + (block_id) * 0x0ull) * 2048; 219 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 220 return CVMX_ADD_IO_SEG(0x0001180008000180ull) + ((offset) + (block_id) * 0x2000ull) * 2048; 221 } 222 return CVMX_ADD_IO_SEG(0x0001180008000180ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 223} 224 225static inline uint64_t CVMX_GMXX_RXX_ADR_CAM1(unsigned long offset, unsigned long block_id) 226{ 227 switch (cvmx_get_octeon_family()) { 228 case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 229 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 230 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 231 return CVMX_ADD_IO_SEG(0x0001180008000188ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 232 case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 233 case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 234 return CVMX_ADD_IO_SEG(0x0001180008000188ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 235 case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 236 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 237 case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 238 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 239 case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 240 return CVMX_ADD_IO_SEG(0x0001180008000188ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 241 case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 242 return CVMX_ADD_IO_SEG(0x0001180008000188ull) + ((offset) + (block_id) * 0x0ull) * 2048; 243 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 244 return CVMX_ADD_IO_SEG(0x0001180008000188ull) + ((offset) + (block_id) * 0x2000ull) * 2048; 245 } 246 return CVMX_ADD_IO_SEG(0x0001180008000188ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 247} 248 249static inline uint64_t CVMX_GMXX_RXX_ADR_CAM2(unsigned long offset, unsigned long block_id) 250{ 251 switch (cvmx_get_octeon_family()) { 252 case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 253 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 254 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 255 return CVMX_ADD_IO_SEG(0x0001180008000190ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 256 case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 257 case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 258 return CVMX_ADD_IO_SEG(0x0001180008000190ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 259 case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 260 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 261 case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 262 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 263 case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 264 return CVMX_ADD_IO_SEG(0x0001180008000190ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 265 case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 266 return CVMX_ADD_IO_SEG(0x0001180008000190ull) + ((offset) + (block_id) * 0x0ull) * 2048; 267 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 268 return CVMX_ADD_IO_SEG(0x0001180008000190ull) + ((offset) + (block_id) * 0x2000ull) * 2048; 269 } 270 return CVMX_ADD_IO_SEG(0x0001180008000190ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 271} 272 273static inline uint64_t CVMX_GMXX_RXX_ADR_CAM3(unsigned long offset, unsigned long block_id) 274{ 275 switch (cvmx_get_octeon_family()) { 276 case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 277 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 278 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 279 return CVMX_ADD_IO_SEG(0x0001180008000198ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 280 case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 281 case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 282 return CVMX_ADD_IO_SEG(0x0001180008000198ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 283 case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 284 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 285 case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 286 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 287 case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 288 return CVMX_ADD_IO_SEG(0x0001180008000198ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 289 case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 290 return CVMX_ADD_IO_SEG(0x0001180008000198ull) + ((offset) + (block_id) * 0x0ull) * 2048; 291 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 292 return CVMX_ADD_IO_SEG(0x0001180008000198ull) + ((offset) + (block_id) * 0x2000ull) * 2048; 293 } 294 return CVMX_ADD_IO_SEG(0x0001180008000198ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 295} 296 297static inline uint64_t CVMX_GMXX_RXX_ADR_CAM4(unsigned long offset, unsigned long block_id) 298{ 299 switch (cvmx_get_octeon_family()) { 300 case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 301 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 302 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 303 return CVMX_ADD_IO_SEG(0x00011800080001A0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 304 case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 305 case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 306 return CVMX_ADD_IO_SEG(0x00011800080001A0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 307 case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 308 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 309 case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 310 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 311 case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 312 return CVMX_ADD_IO_SEG(0x00011800080001A0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 313 case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 314 return CVMX_ADD_IO_SEG(0x00011800080001A0ull) + ((offset) + (block_id) * 0x0ull) * 2048; 315 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 316 return CVMX_ADD_IO_SEG(0x00011800080001A0ull) + ((offset) + (block_id) * 0x2000ull) * 2048; 317 } 318 return CVMX_ADD_IO_SEG(0x00011800080001A0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 319} 320 321static inline uint64_t CVMX_GMXX_RXX_ADR_CAM5(unsigned long offset, unsigned long block_id) 322{ 323 switch (cvmx_get_octeon_family()) { 324 case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 325 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 326 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 327 return CVMX_ADD_IO_SEG(0x00011800080001A8ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 328 case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 329 case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 330 return CVMX_ADD_IO_SEG(0x00011800080001A8ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 331 case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 332 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 333 case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 334 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 335 case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 336 return CVMX_ADD_IO_SEG(0x00011800080001A8ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 337 case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 338 return CVMX_ADD_IO_SEG(0x00011800080001A8ull) + ((offset) + (block_id) * 0x0ull) * 2048; 339 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 340 return CVMX_ADD_IO_SEG(0x00011800080001A8ull) + ((offset) + (block_id) * 0x2000ull) * 2048; 341 } 342 return CVMX_ADD_IO_SEG(0x00011800080001A8ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 343} 344 345static inline uint64_t CVMX_GMXX_RXX_ADR_CAM_ALL_EN(unsigned long offset, unsigned long block_id) 346{ 347 switch (cvmx_get_octeon_family()) { 348 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 349 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 350 return CVMX_ADD_IO_SEG(0x0001180008000110ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 351 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 352 return CVMX_ADD_IO_SEG(0x0001180008000110ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 353 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 354 return CVMX_ADD_IO_SEG(0x0001180008000110ull) + ((offset) + (block_id) * 0x2000ull) * 2048; 355 } 356 return CVMX_ADD_IO_SEG(0x0001180008000110ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 357} 358 359static inline uint64_t CVMX_GMXX_RXX_ADR_CAM_EN(unsigned long offset, unsigned long block_id) 360{ 361 switch (cvmx_get_octeon_family()) { 362 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 363 return CVMX_ADD_IO_SEG(0x0001180008000108ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 364 case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 365 case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 366 return CVMX_ADD_IO_SEG(0x0001180008000108ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 367 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 368 case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 369 return CVMX_ADD_IO_SEG(0x0001180008000108ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 370 case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 371 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 372 case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 373 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 374 case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 375 return CVMX_ADD_IO_SEG(0x0001180008000108ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 376 case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 377 return CVMX_ADD_IO_SEG(0x0001180008000108ull) + ((offset) + (block_id) * 0x0ull) * 2048; 378 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 379 return CVMX_ADD_IO_SEG(0x0001180008000108ull) + ((offset) + (block_id) * 0x2000ull) * 2048; 380 } 381 return CVMX_ADD_IO_SEG(0x0001180008000108ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 382} 383 384static inline uint64_t CVMX_GMXX_RXX_ADR_CTL(unsigned long offset, unsigned long block_id) 385{ 386 switch (cvmx_get_octeon_family()) { 387 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 388 return CVMX_ADD_IO_SEG(0x0001180008000100ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 389 case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 390 case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 391 return CVMX_ADD_IO_SEG(0x0001180008000100ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 392 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 393 case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 394 return CVMX_ADD_IO_SEG(0x0001180008000100ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 395 case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 396 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 397 case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 398 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 399 case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 400 return CVMX_ADD_IO_SEG(0x0001180008000100ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 401 case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 402 return CVMX_ADD_IO_SEG(0x0001180008000100ull) + ((offset) + (block_id) * 0x0ull) * 2048; 403 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 404 return CVMX_ADD_IO_SEG(0x0001180008000100ull) + ((offset) + (block_id) * 0x2000ull) * 2048; 405 } 406 return CVMX_ADD_IO_SEG(0x0001180008000100ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 407} 408 409static inline uint64_t CVMX_GMXX_RXX_DECISION(unsigned long offset, unsigned long block_id) 410{ 411 switch (cvmx_get_octeon_family()) { 412 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 413 return CVMX_ADD_IO_SEG(0x0001180008000040ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 414 case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 415 case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 416 return CVMX_ADD_IO_SEG(0x0001180008000040ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 417 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 418 case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 419 return CVMX_ADD_IO_SEG(0x0001180008000040ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 420 case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 421 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 422 case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 423 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 424 case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 425 return CVMX_ADD_IO_SEG(0x0001180008000040ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 426 case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 427 return CVMX_ADD_IO_SEG(0x0001180008000040ull) + ((offset) + (block_id) * 0x0ull) * 2048; 428 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 429 return CVMX_ADD_IO_SEG(0x0001180008000040ull) + ((offset) + (block_id) * 0x2000ull) * 2048; 430 } 431 return CVMX_ADD_IO_SEG(0x0001180008000040ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 432} 433 434static inline uint64_t CVMX_GMXX_RXX_FRM_CHK(unsigned long offset, unsigned long block_id) 435{ 436 switch (cvmx_get_octeon_family()) { 437 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 438 return CVMX_ADD_IO_SEG(0x0001180008000020ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 439 case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 440 case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 441 return CVMX_ADD_IO_SEG(0x0001180008000020ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 442 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 443 case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 444 return CVMX_ADD_IO_SEG(0x0001180008000020ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 445 case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 446 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 447 case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 448 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 449 case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 450 return CVMX_ADD_IO_SEG(0x0001180008000020ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 451 case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 452 return CVMX_ADD_IO_SEG(0x0001180008000020ull) + ((offset) + (block_id) * 0x0ull) * 2048; 453 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 454 return CVMX_ADD_IO_SEG(0x0001180008000020ull) + ((offset) + (block_id) * 0x2000ull) * 2048; 455 } 456 return CVMX_ADD_IO_SEG(0x0001180008000020ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 457} 458 459static inline uint64_t CVMX_GMXX_RXX_FRM_CTL(unsigned long offset, unsigned long block_id) 460{ 461 switch (cvmx_get_octeon_family()) { 462 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 463 return CVMX_ADD_IO_SEG(0x0001180008000018ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 464 case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 465 case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 466 return CVMX_ADD_IO_SEG(0x0001180008000018ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 467 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 468 case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 469 return CVMX_ADD_IO_SEG(0x0001180008000018ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 470 case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 471 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 472 case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 473 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 474 case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 475 return CVMX_ADD_IO_SEG(0x0001180008000018ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 476 case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 477 return CVMX_ADD_IO_SEG(0x0001180008000018ull) + ((offset) + (block_id) * 0x0ull) * 2048; 478 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 479 return CVMX_ADD_IO_SEG(0x0001180008000018ull) + ((offset) + (block_id) * 0x2000ull) * 2048; 480 } 481 return CVMX_ADD_IO_SEG(0x0001180008000018ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 482} 483 484#define CVMX_GMXX_RXX_FRM_MAX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000030ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048) 485#define CVMX_GMXX_RXX_FRM_MIN(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000028ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048) 486static inline uint64_t CVMX_GMXX_RXX_IFG(unsigned long offset, unsigned long block_id) 487{ 488 switch (cvmx_get_octeon_family()) { 489 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 490 return CVMX_ADD_IO_SEG(0x0001180008000058ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 491 case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 492 case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 493 return CVMX_ADD_IO_SEG(0x0001180008000058ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 494 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 495 case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 496 return CVMX_ADD_IO_SEG(0x0001180008000058ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 497 case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 498 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 499 case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 500 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 501 case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 502 return CVMX_ADD_IO_SEG(0x0001180008000058ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 503 case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 504 return CVMX_ADD_IO_SEG(0x0001180008000058ull) + ((offset) + (block_id) * 0x0ull) * 2048; 505 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 506 return CVMX_ADD_IO_SEG(0x0001180008000058ull) + ((offset) + (block_id) * 0x2000ull) * 2048; 507 } 508 return CVMX_ADD_IO_SEG(0x0001180008000058ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 509} 510 511static inline uint64_t CVMX_GMXX_RXX_INT_EN(unsigned long offset, unsigned long block_id) 512{ 513 switch (cvmx_get_octeon_family()) { 514 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 515 return CVMX_ADD_IO_SEG(0x0001180008000008ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 516 case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 517 case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 518 return CVMX_ADD_IO_SEG(0x0001180008000008ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 519 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 520 case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 521 return CVMX_ADD_IO_SEG(0x0001180008000008ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 522 case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 523 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 524 case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 525 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 526 case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 527 return CVMX_ADD_IO_SEG(0x0001180008000008ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 528 case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 529 return CVMX_ADD_IO_SEG(0x0001180008000008ull) + ((offset) + (block_id) * 0x0ull) * 2048; 530 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 531 return CVMX_ADD_IO_SEG(0x0001180008000008ull) + ((offset) + (block_id) * 0x2000ull) * 2048; 532 } 533 return CVMX_ADD_IO_SEG(0x0001180008000008ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 534} 535 536static inline uint64_t CVMX_GMXX_RXX_INT_REG(unsigned long offset, unsigned long block_id) 537{ 538 switch (cvmx_get_octeon_family()) { 539 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 540 return CVMX_ADD_IO_SEG(0x0001180008000000ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 541 case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 542 case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 543 return CVMX_ADD_IO_SEG(0x0001180008000000ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 544 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 545 case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 546 return CVMX_ADD_IO_SEG(0x0001180008000000ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 547 case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 548 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 549 case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 550 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 551 case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 552 return CVMX_ADD_IO_SEG(0x0001180008000000ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 553 case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 554 return CVMX_ADD_IO_SEG(0x0001180008000000ull) + ((offset) + (block_id) * 0x0ull) * 2048; 555 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 556 return CVMX_ADD_IO_SEG(0x0001180008000000ull) + ((offset) + (block_id) * 0x2000ull) * 2048; 557 } 558 return CVMX_ADD_IO_SEG(0x0001180008000000ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 559} 560 561static inline uint64_t CVMX_GMXX_RXX_JABBER(unsigned long offset, unsigned long block_id) 562{ 563 switch (cvmx_get_octeon_family()) { 564 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 565 return CVMX_ADD_IO_SEG(0x0001180008000038ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 566 case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 567 case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 568 return CVMX_ADD_IO_SEG(0x0001180008000038ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 569 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 570 case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 571 return CVMX_ADD_IO_SEG(0x0001180008000038ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 572 case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 573 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 574 case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 575 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 576 case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 577 return CVMX_ADD_IO_SEG(0x0001180008000038ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 578 case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 579 return CVMX_ADD_IO_SEG(0x0001180008000038ull) + ((offset) + (block_id) * 0x0ull) * 2048; 580 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 581 return CVMX_ADD_IO_SEG(0x0001180008000038ull) + ((offset) + (block_id) * 0x2000ull) * 2048; 582 } 583 return CVMX_ADD_IO_SEG(0x0001180008000038ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 584} 585 586static inline uint64_t CVMX_GMXX_RXX_PAUSE_DROP_TIME(unsigned long offset, unsigned long block_id) 587{ 588 switch (cvmx_get_octeon_family()) { 589 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 590 return CVMX_ADD_IO_SEG(0x0001180008000068ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 591 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 592 return CVMX_ADD_IO_SEG(0x0001180008000068ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 593 case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 594 return CVMX_ADD_IO_SEG(0x0001180008000068ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 595 case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 596 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 597 case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 598 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 599 return CVMX_ADD_IO_SEG(0x0001180008000068ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 600 case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 601 return CVMX_ADD_IO_SEG(0x0001180008000068ull) + ((offset) + (block_id) * 0x0ull) * 2048; 602 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 603 return CVMX_ADD_IO_SEG(0x0001180008000068ull) + ((offset) + (block_id) * 0x2000ull) * 2048; 604 } 605 return CVMX_ADD_IO_SEG(0x0001180008000068ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 606} 607 608#define CVMX_GMXX_RXX_RX_INBND(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000060ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048) 609static inline uint64_t CVMX_GMXX_RXX_STATS_CTL(unsigned long offset, unsigned long block_id) 610{ 611 switch (cvmx_get_octeon_family()) { 612 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 613 return CVMX_ADD_IO_SEG(0x0001180008000050ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 614 case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 615 case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 616 return CVMX_ADD_IO_SEG(0x0001180008000050ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 617 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 618 case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 619 return CVMX_ADD_IO_SEG(0x0001180008000050ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 620 case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 621 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 622 case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 623 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 624 case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 625 return CVMX_ADD_IO_SEG(0x0001180008000050ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 626 case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 627 return CVMX_ADD_IO_SEG(0x0001180008000050ull) + ((offset) + (block_id) * 0x0ull) * 2048; 628 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 629 return CVMX_ADD_IO_SEG(0x0001180008000050ull) + ((offset) + (block_id) * 0x2000ull) * 2048; 630 } 631 return CVMX_ADD_IO_SEG(0x0001180008000050ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 632} 633 634static inline uint64_t CVMX_GMXX_RXX_STATS_OCTS(unsigned long offset, unsigned long block_id) 635{ 636 switch (cvmx_get_octeon_family()) { 637 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 638 return CVMX_ADD_IO_SEG(0x0001180008000088ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 639 case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 640 case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 641 return CVMX_ADD_IO_SEG(0x0001180008000088ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 642 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 643 case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 644 return CVMX_ADD_IO_SEG(0x0001180008000088ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 645 case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 646 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 647 case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 648 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 649 case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 650 return CVMX_ADD_IO_SEG(0x0001180008000088ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 651 case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 652 return CVMX_ADD_IO_SEG(0x0001180008000088ull) + ((offset) + (block_id) * 0x0ull) * 2048; 653 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 654 return CVMX_ADD_IO_SEG(0x0001180008000088ull) + ((offset) + (block_id) * 0x2000ull) * 2048; 655 } 656 return CVMX_ADD_IO_SEG(0x0001180008000088ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 657} 658 659static inline uint64_t CVMX_GMXX_RXX_STATS_OCTS_CTL(unsigned long offset, unsigned long block_id) 660{ 661 switch (cvmx_get_octeon_family()) { 662 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 663 return CVMX_ADD_IO_SEG(0x0001180008000098ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 664 case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 665 case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 666 return CVMX_ADD_IO_SEG(0x0001180008000098ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 667 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 668 case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 669 return CVMX_ADD_IO_SEG(0x0001180008000098ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 670 case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 671 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 672 case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 673 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 674 case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 675 return CVMX_ADD_IO_SEG(0x0001180008000098ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 676 case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 677 return CVMX_ADD_IO_SEG(0x0001180008000098ull) + ((offset) + (block_id) * 0x0ull) * 2048; 678 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 679 return CVMX_ADD_IO_SEG(0x0001180008000098ull) + ((offset) + (block_id) * 0x2000ull) * 2048; 680 } 681 return CVMX_ADD_IO_SEG(0x0001180008000098ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 682} 683 684static inline uint64_t CVMX_GMXX_RXX_STATS_OCTS_DMAC(unsigned long offset, unsigned long block_id) 685{ 686 switch (cvmx_get_octeon_family()) { 687 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 688 return CVMX_ADD_IO_SEG(0x00011800080000A8ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 689 case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 690 case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 691 return CVMX_ADD_IO_SEG(0x00011800080000A8ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 692 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 693 case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 694 return CVMX_ADD_IO_SEG(0x00011800080000A8ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 695 case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 696 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 697 case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 698 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 699 case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 700 return CVMX_ADD_IO_SEG(0x00011800080000A8ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 701 case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 702 return CVMX_ADD_IO_SEG(0x00011800080000A8ull) + ((offset) + (block_id) * 0x0ull) * 2048; 703 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 704 return CVMX_ADD_IO_SEG(0x00011800080000A8ull) + ((offset) + (block_id) * 0x2000ull) * 2048; 705 } 706 return CVMX_ADD_IO_SEG(0x00011800080000A8ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 707} 708 709static inline uint64_t CVMX_GMXX_RXX_STATS_OCTS_DRP(unsigned long offset, unsigned long block_id) 710{ 711 switch (cvmx_get_octeon_family()) { 712 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 713 return CVMX_ADD_IO_SEG(0x00011800080000B8ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 714 case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 715 case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 716 return CVMX_ADD_IO_SEG(0x00011800080000B8ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 717 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 718 case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 719 return CVMX_ADD_IO_SEG(0x00011800080000B8ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 720 case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 721 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 722 case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 723 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 724 case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 725 return CVMX_ADD_IO_SEG(0x00011800080000B8ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 726 case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 727 return CVMX_ADD_IO_SEG(0x00011800080000B8ull) + ((offset) + (block_id) * 0x0ull) * 2048; 728 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 729 return CVMX_ADD_IO_SEG(0x00011800080000B8ull) + ((offset) + (block_id) * 0x2000ull) * 2048; 730 } 731 return CVMX_ADD_IO_SEG(0x00011800080000B8ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 732} 733 734static inline uint64_t CVMX_GMXX_RXX_STATS_PKTS(unsigned long offset, unsigned long block_id) 735{ 736 switch (cvmx_get_octeon_family()) { 737 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 738 return CVMX_ADD_IO_SEG(0x0001180008000080ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 739 case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 740 case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 741 return CVMX_ADD_IO_SEG(0x0001180008000080ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 742 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 743 case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 744 return CVMX_ADD_IO_SEG(0x0001180008000080ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 745 case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 746 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 747 case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 748 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 749 case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 750 return CVMX_ADD_IO_SEG(0x0001180008000080ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 751 case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 752 return CVMX_ADD_IO_SEG(0x0001180008000080ull) + ((offset) + (block_id) * 0x0ull) * 2048; 753 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 754 return CVMX_ADD_IO_SEG(0x0001180008000080ull) + ((offset) + (block_id) * 0x2000ull) * 2048; 755 } 756 return CVMX_ADD_IO_SEG(0x0001180008000080ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 757} 758 759static inline uint64_t CVMX_GMXX_RXX_STATS_PKTS_BAD(unsigned long offset, unsigned long block_id) 760{ 761 switch (cvmx_get_octeon_family()) { 762 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 763 return CVMX_ADD_IO_SEG(0x00011800080000C0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 764 case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 765 case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 766 return CVMX_ADD_IO_SEG(0x00011800080000C0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 767 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 768 case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 769 return CVMX_ADD_IO_SEG(0x00011800080000C0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 770 case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 771 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 772 case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 773 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 774 case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 775 return CVMX_ADD_IO_SEG(0x00011800080000C0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 776 case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 777 return CVMX_ADD_IO_SEG(0x00011800080000C0ull) + ((offset) + (block_id) * 0x0ull) * 2048; 778 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 779 return CVMX_ADD_IO_SEG(0x00011800080000C0ull) + ((offset) + (block_id) * 0x2000ull) * 2048; 780 } 781 return CVMX_ADD_IO_SEG(0x00011800080000C0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 782} 783 784static inline uint64_t CVMX_GMXX_RXX_STATS_PKTS_CTL(unsigned long offset, unsigned long block_id) 785{ 786 switch (cvmx_get_octeon_family()) { 787 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 788 return CVMX_ADD_IO_SEG(0x0001180008000090ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 789 case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 790 case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 791 return CVMX_ADD_IO_SEG(0x0001180008000090ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 792 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 793 case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 794 return CVMX_ADD_IO_SEG(0x0001180008000090ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 795 case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 796 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 797 case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 798 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 799 case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 800 return CVMX_ADD_IO_SEG(0x0001180008000090ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 801 case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 802 return CVMX_ADD_IO_SEG(0x0001180008000090ull) + ((offset) + (block_id) * 0x0ull) * 2048; 803 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 804 return CVMX_ADD_IO_SEG(0x0001180008000090ull) + ((offset) + (block_id) * 0x2000ull) * 2048; 805 } 806 return CVMX_ADD_IO_SEG(0x0001180008000090ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 807} 808 809static inline uint64_t CVMX_GMXX_RXX_STATS_PKTS_DMAC(unsigned long offset, unsigned long block_id) 810{ 811 switch (cvmx_get_octeon_family()) { 812 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 813 return CVMX_ADD_IO_SEG(0x00011800080000A0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 814 case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 815 case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 816 return CVMX_ADD_IO_SEG(0x00011800080000A0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 817 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 818 case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 819 return CVMX_ADD_IO_SEG(0x00011800080000A0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 820 case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 821 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 822 case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 823 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 824 case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 825 return CVMX_ADD_IO_SEG(0x00011800080000A0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 826 case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 827 return CVMX_ADD_IO_SEG(0x00011800080000A0ull) + ((offset) + (block_id) * 0x0ull) * 2048; 828 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 829 return CVMX_ADD_IO_SEG(0x00011800080000A0ull) + ((offset) + (block_id) * 0x2000ull) * 2048; 830 } 831 return CVMX_ADD_IO_SEG(0x00011800080000A0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 832} 833 834static inline uint64_t CVMX_GMXX_RXX_STATS_PKTS_DRP(unsigned long offset, unsigned long block_id) 835{ 836 switch (cvmx_get_octeon_family()) { 837 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 838 return CVMX_ADD_IO_SEG(0x00011800080000B0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 839 case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 840 case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 841 return CVMX_ADD_IO_SEG(0x00011800080000B0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 842 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 843 case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 844 return CVMX_ADD_IO_SEG(0x00011800080000B0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 845 case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 846 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 847 case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 848 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 849 case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 850 return CVMX_ADD_IO_SEG(0x00011800080000B0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 851 case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 852 return CVMX_ADD_IO_SEG(0x00011800080000B0ull) + ((offset) + (block_id) * 0x0ull) * 2048; 853 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 854 return CVMX_ADD_IO_SEG(0x00011800080000B0ull) + ((offset) + (block_id) * 0x2000ull) * 2048; 855 } 856 return CVMX_ADD_IO_SEG(0x00011800080000B0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 857} 858 859static inline uint64_t CVMX_GMXX_RXX_UDD_SKP(unsigned long offset, unsigned long block_id) 860{ 861 switch (cvmx_get_octeon_family()) { 862 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 863 return CVMX_ADD_IO_SEG(0x0001180008000048ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 864 case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 865 case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 866 return CVMX_ADD_IO_SEG(0x0001180008000048ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 867 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 868 case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 869 return CVMX_ADD_IO_SEG(0x0001180008000048ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 870 case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 871 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 872 case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 873 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 874 case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 875 return CVMX_ADD_IO_SEG(0x0001180008000048ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 876 case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 877 return CVMX_ADD_IO_SEG(0x0001180008000048ull) + ((offset) + (block_id) * 0x0ull) * 2048; 878 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 879 return CVMX_ADD_IO_SEG(0x0001180008000048ull) + ((offset) + (block_id) * 0x2000ull) * 2048; 880 } 881 return CVMX_ADD_IO_SEG(0x0001180008000048ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 882} 883 884static inline uint64_t CVMX_GMXX_RX_BP_DROPX(unsigned long offset, unsigned long block_id) 885{ 886 switch (cvmx_get_octeon_family()) { 887 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 888 return CVMX_ADD_IO_SEG(0x0001180008000420ull) + ((offset) + (block_id) * 0x1000000ull) * 8; 889 case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 890 case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 891 return CVMX_ADD_IO_SEG(0x0001180008000420ull) + ((offset) + (block_id) * 0x1000000ull) * 8; 892 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 893 case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 894 return CVMX_ADD_IO_SEG(0x0001180008000420ull) + ((offset) + (block_id) * 0x1000000ull) * 8; 895 case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 896 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 897 case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 898 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 899 case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 900 return CVMX_ADD_IO_SEG(0x0001180008000420ull) + ((offset) + (block_id) * 0x1000000ull) * 8; 901 case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 902 return CVMX_ADD_IO_SEG(0x0001180008000420ull) + ((offset) + (block_id) * 0x0ull) * 8; 903 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 904 return CVMX_ADD_IO_SEG(0x0001180008000420ull) + ((offset) + (block_id) * 0x200000ull) * 8; 905 } 906 return CVMX_ADD_IO_SEG(0x0001180008000420ull) + ((offset) + (block_id) * 0x1000000ull) * 8; 907} 908 909static inline uint64_t CVMX_GMXX_RX_BP_OFFX(unsigned long offset, unsigned long block_id) 910{ 911 switch (cvmx_get_octeon_family()) { 912 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 913 return CVMX_ADD_IO_SEG(0x0001180008000460ull) + ((offset) + (block_id) * 0x1000000ull) * 8; 914 case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 915 case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 916 return CVMX_ADD_IO_SEG(0x0001180008000460ull) + ((offset) + (block_id) * 0x1000000ull) * 8; 917 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 918 case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 919 return CVMX_ADD_IO_SEG(0x0001180008000460ull) + ((offset) + (block_id) * 0x1000000ull) * 8; 920 case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 921 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 922 case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 923 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 924 case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 925 return CVMX_ADD_IO_SEG(0x0001180008000460ull) + ((offset) + (block_id) * 0x1000000ull) * 8; 926 case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 927 return CVMX_ADD_IO_SEG(0x0001180008000460ull) + ((offset) + (block_id) * 0x0ull) * 8; 928 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 929 return CVMX_ADD_IO_SEG(0x0001180008000460ull) + ((offset) + (block_id) * 0x200000ull) * 8; 930 } 931 return CVMX_ADD_IO_SEG(0x0001180008000460ull) + ((offset) + (block_id) * 0x1000000ull) * 8; 932} 933 934static inline uint64_t CVMX_GMXX_RX_BP_ONX(unsigned long offset, unsigned long block_id) 935{ 936 switch (cvmx_get_octeon_family()) { 937 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 938 return CVMX_ADD_IO_SEG(0x0001180008000440ull) + ((offset) + (block_id) * 0x1000000ull) * 8; 939 case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 940 case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 941 return CVMX_ADD_IO_SEG(0x0001180008000440ull) + ((offset) + (block_id) * 0x1000000ull) * 8; 942 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 943 case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 944 return CVMX_ADD_IO_SEG(0x0001180008000440ull) + ((offset) + (block_id) * 0x1000000ull) * 8; 945 case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 946 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 947 case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 948 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 949 case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 950 return CVMX_ADD_IO_SEG(0x0001180008000440ull) + ((offset) + (block_id) * 0x1000000ull) * 8; 951 case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 952 return CVMX_ADD_IO_SEG(0x0001180008000440ull) + ((offset) + (block_id) * 0x0ull) * 8; 953 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 954 return CVMX_ADD_IO_SEG(0x0001180008000440ull) + ((offset) + (block_id) * 0x200000ull) * 8; 955 } 956 return CVMX_ADD_IO_SEG(0x0001180008000440ull) + ((offset) + (block_id) * 0x1000000ull) * 8; 957} 958 959static inline uint64_t CVMX_GMXX_RX_HG2_STATUS(unsigned long block_id) 960{ 961 switch (cvmx_get_octeon_family()) { 962 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 963 case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 964 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 965 return CVMX_ADD_IO_SEG(0x0001180008000548ull) + (block_id) * 0x8000000ull; 966 case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 967 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 968 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 969 return CVMX_ADD_IO_SEG(0x0001180008000548ull) + (block_id) * 0x8000000ull; 970 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 971 return CVMX_ADD_IO_SEG(0x0001180008000548ull) + (block_id) * 0x1000000ull; 972 } 973 return CVMX_ADD_IO_SEG(0x0001180008000548ull) + (block_id) * 0x8000000ull; 974} 975 976#define CVMX_GMXX_RX_PASS_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800080005F8ull) + ((block_id) & 1) * 0x8000000ull) 977#define CVMX_GMXX_RX_PASS_MAPX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000600ull) + (((offset) & 15) + ((block_id) & 1) * 0x1000000ull) * 8) 978static inline uint64_t CVMX_GMXX_RX_PRTS(unsigned long block_id) 979{ 980 switch (cvmx_get_octeon_family()) { 981 case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 982 case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 983 case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 984 case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 985 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 986 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 987 return CVMX_ADD_IO_SEG(0x0001180008000410ull) + (block_id) * 0x8000000ull; 988 case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 989 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 990 case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 991 case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 992 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 993 return CVMX_ADD_IO_SEG(0x0001180008000410ull) + (block_id) * 0x8000000ull; 994 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 995 return CVMX_ADD_IO_SEG(0x0001180008000410ull) + (block_id) * 0x1000000ull; 996 } 997 return CVMX_ADD_IO_SEG(0x0001180008000410ull) + (block_id) * 0x8000000ull; 998} 999 1000static inline uint64_t CVMX_GMXX_RX_PRT_INFO(unsigned long block_id) 1001{ 1002 switch (cvmx_get_octeon_family()) { 1003 case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 1004 case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 1005 case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 1006 case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 1007 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 1008 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 1009 return CVMX_ADD_IO_SEG(0x00011800080004E8ull) + (block_id) * 0x8000000ull; 1010 case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 1011 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 1012 case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 1013 case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 1014 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 1015 return CVMX_ADD_IO_SEG(0x00011800080004E8ull) + (block_id) * 0x8000000ull; 1016 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 1017 return CVMX_ADD_IO_SEG(0x00011800080004E8ull) + (block_id) * 0x1000000ull; 1018 } 1019 return CVMX_ADD_IO_SEG(0x00011800080004E8ull) + (block_id) * 0x8000000ull; 1020} 1021 1022#define CVMX_GMXX_RX_TX_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800080007E8ull)) 1023static inline uint64_t CVMX_GMXX_RX_XAUI_BAD_COL(unsigned long block_id) 1024{ 1025 switch (cvmx_get_octeon_family()) { 1026 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 1027 case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 1028 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 1029 return CVMX_ADD_IO_SEG(0x0001180008000538ull) + (block_id) * 0x8000000ull; 1030 case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 1031 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 1032 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 1033 return CVMX_ADD_IO_SEG(0x0001180008000538ull) + (block_id) * 0x8000000ull; 1034 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 1035 return CVMX_ADD_IO_SEG(0x0001180008000538ull) + (block_id) * 0x1000000ull; 1036 } 1037 return CVMX_ADD_IO_SEG(0x0001180008000538ull) + (block_id) * 0x8000000ull; 1038} 1039 1040static inline uint64_t CVMX_GMXX_RX_XAUI_CTL(unsigned long block_id) 1041{ 1042 switch (cvmx_get_octeon_family()) { 1043 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 1044 case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 1045 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 1046 return CVMX_ADD_IO_SEG(0x0001180008000530ull) + (block_id) * 0x8000000ull; 1047 case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 1048 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 1049 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 1050 return CVMX_ADD_IO_SEG(0x0001180008000530ull) + (block_id) * 0x8000000ull; 1051 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 1052 return CVMX_ADD_IO_SEG(0x0001180008000530ull) + (block_id) * 0x1000000ull; 1053 } 1054 return CVMX_ADD_IO_SEG(0x0001180008000530ull) + (block_id) * 0x8000000ull; 1055} 1056 1057static inline uint64_t CVMX_GMXX_SMACX(unsigned long offset, unsigned long block_id) 1058{ 1059 switch (cvmx_get_octeon_family()) { 1060 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 1061 return CVMX_ADD_IO_SEG(0x0001180008000230ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1062 case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 1063 case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 1064 return CVMX_ADD_IO_SEG(0x0001180008000230ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1065 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 1066 case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 1067 return CVMX_ADD_IO_SEG(0x0001180008000230ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1068 case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 1069 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 1070 case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 1071 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 1072 case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 1073 return CVMX_ADD_IO_SEG(0x0001180008000230ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1074 case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 1075 return CVMX_ADD_IO_SEG(0x0001180008000230ull) + ((offset) + (block_id) * 0x0ull) * 2048; 1076 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 1077 return CVMX_ADD_IO_SEG(0x0001180008000230ull) + ((offset) + (block_id) * 0x2000ull) * 2048; 1078 } 1079 return CVMX_ADD_IO_SEG(0x0001180008000230ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1080} 1081 1082static inline uint64_t CVMX_GMXX_SOFT_BIST(unsigned long block_id) 1083{ 1084 switch (cvmx_get_octeon_family()) { 1085 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 1086 return CVMX_ADD_IO_SEG(0x00011800080007E8ull) + (block_id) * 0x8000000ull; 1087 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 1088 return CVMX_ADD_IO_SEG(0x00011800080007E8ull) + (block_id) * 0x8000000ull; 1089 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 1090 return CVMX_ADD_IO_SEG(0x00011800080007E8ull) + (block_id) * 0x1000000ull; 1091 } 1092 return CVMX_ADD_IO_SEG(0x00011800080007E8ull) + (block_id) * 0x1000000ull; 1093} 1094 1095static inline uint64_t CVMX_GMXX_STAT_BP(unsigned long block_id) 1096{ 1097 switch (cvmx_get_octeon_family()) { 1098 case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 1099 case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 1100 case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 1101 case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 1102 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 1103 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 1104 return CVMX_ADD_IO_SEG(0x0001180008000520ull) + (block_id) * 0x8000000ull; 1105 case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 1106 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 1107 case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 1108 case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 1109 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 1110 return CVMX_ADD_IO_SEG(0x0001180008000520ull) + (block_id) * 0x8000000ull; 1111 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 1112 return CVMX_ADD_IO_SEG(0x0001180008000520ull) + (block_id) * 0x1000000ull; 1113 } 1114 return CVMX_ADD_IO_SEG(0x0001180008000520ull) + (block_id) * 0x8000000ull; 1115} 1116 1117static inline uint64_t CVMX_GMXX_TB_REG(unsigned long block_id) 1118{ 1119 switch (cvmx_get_octeon_family()) { 1120 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 1121 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 1122 return CVMX_ADD_IO_SEG(0x00011800080007E0ull) + (block_id) * 0x8000000ull; 1123 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 1124 return CVMX_ADD_IO_SEG(0x00011800080007E0ull) + (block_id) * 0x8000000ull; 1125 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 1126 return CVMX_ADD_IO_SEG(0x00011800080007E0ull) + (block_id) * 0x1000000ull; 1127 } 1128 return CVMX_ADD_IO_SEG(0x00011800080007E0ull) + (block_id) * 0x8000000ull; 1129} 1130 1131static inline uint64_t CVMX_GMXX_TXX_APPEND(unsigned long offset, unsigned long block_id) 1132{ 1133 switch (cvmx_get_octeon_family()) { 1134 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 1135 return CVMX_ADD_IO_SEG(0x0001180008000218ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1136 case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 1137 case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 1138 return CVMX_ADD_IO_SEG(0x0001180008000218ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1139 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 1140 case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 1141 return CVMX_ADD_IO_SEG(0x0001180008000218ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1142 case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 1143 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 1144 case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 1145 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 1146 case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 1147 return CVMX_ADD_IO_SEG(0x0001180008000218ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1148 case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 1149 return CVMX_ADD_IO_SEG(0x0001180008000218ull) + ((offset) + (block_id) * 0x0ull) * 2048; 1150 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 1151 return CVMX_ADD_IO_SEG(0x0001180008000218ull) + ((offset) + (block_id) * 0x2000ull) * 2048; 1152 } 1153 return CVMX_ADD_IO_SEG(0x0001180008000218ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1154} 1155 1156static inline uint64_t CVMX_GMXX_TXX_BURST(unsigned long offset, unsigned long block_id) 1157{ 1158 switch (cvmx_get_octeon_family()) { 1159 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 1160 return CVMX_ADD_IO_SEG(0x0001180008000228ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1161 case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 1162 case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 1163 return CVMX_ADD_IO_SEG(0x0001180008000228ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1164 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 1165 case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 1166 return CVMX_ADD_IO_SEG(0x0001180008000228ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1167 case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 1168 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 1169 case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 1170 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 1171 case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 1172 return CVMX_ADD_IO_SEG(0x0001180008000228ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1173 case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 1174 return CVMX_ADD_IO_SEG(0x0001180008000228ull) + ((offset) + (block_id) * 0x0ull) * 2048; 1175 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 1176 return CVMX_ADD_IO_SEG(0x0001180008000228ull) + ((offset) + (block_id) * 0x2000ull) * 2048; 1177 } 1178 return CVMX_ADD_IO_SEG(0x0001180008000228ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1179} 1180 1181static inline uint64_t CVMX_GMXX_TXX_CBFC_XOFF(unsigned long offset, unsigned long block_id) 1182{ 1183 switch (cvmx_get_octeon_family()) { 1184 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 1185 case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 1186 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 1187 return CVMX_ADD_IO_SEG(0x00011800080005A0ull) + (block_id) * 0x8000000ull; 1188 case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 1189 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 1190 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 1191 return CVMX_ADD_IO_SEG(0x00011800080005A0ull) + (block_id) * 0x8000000ull; 1192 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 1193 return CVMX_ADD_IO_SEG(0x00011800080005A0ull) + (block_id) * 0x1000000ull; 1194 } 1195 return CVMX_ADD_IO_SEG(0x00011800080005A0ull) + (block_id) * 0x8000000ull; 1196} 1197 1198static inline uint64_t CVMX_GMXX_TXX_CBFC_XON(unsigned long offset, unsigned long block_id) 1199{ 1200 switch (cvmx_get_octeon_family()) { 1201 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 1202 case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 1203 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 1204 return CVMX_ADD_IO_SEG(0x00011800080005C0ull) + (block_id) * 0x8000000ull; 1205 case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 1206 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 1207 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 1208 return CVMX_ADD_IO_SEG(0x00011800080005C0ull) + (block_id) * 0x8000000ull; 1209 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 1210 return CVMX_ADD_IO_SEG(0x00011800080005C0ull) + (block_id) * 0x1000000ull; 1211 } 1212 return CVMX_ADD_IO_SEG(0x00011800080005C0ull) + (block_id) * 0x8000000ull; 1213} 1214 1215#define CVMX_GMXX_TXX_CLK(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000208ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048) 1216static inline uint64_t CVMX_GMXX_TXX_CTL(unsigned long offset, unsigned long block_id) 1217{ 1218 switch (cvmx_get_octeon_family()) { 1219 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 1220 return CVMX_ADD_IO_SEG(0x0001180008000270ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1221 case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 1222 case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 1223 return CVMX_ADD_IO_SEG(0x0001180008000270ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1224 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 1225 case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 1226 return CVMX_ADD_IO_SEG(0x0001180008000270ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1227 case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 1228 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 1229 case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 1230 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 1231 case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 1232 return CVMX_ADD_IO_SEG(0x0001180008000270ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1233 case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 1234 return CVMX_ADD_IO_SEG(0x0001180008000270ull) + ((offset) + (block_id) * 0x0ull) * 2048; 1235 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 1236 return CVMX_ADD_IO_SEG(0x0001180008000270ull) + ((offset) + (block_id) * 0x2000ull) * 2048; 1237 } 1238 return CVMX_ADD_IO_SEG(0x0001180008000270ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1239} 1240 1241static inline uint64_t CVMX_GMXX_TXX_MIN_PKT(unsigned long offset, unsigned long block_id) 1242{ 1243 switch (cvmx_get_octeon_family()) { 1244 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 1245 return CVMX_ADD_IO_SEG(0x0001180008000240ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1246 case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 1247 case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 1248 return CVMX_ADD_IO_SEG(0x0001180008000240ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1249 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 1250 case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 1251 return CVMX_ADD_IO_SEG(0x0001180008000240ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1252 case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 1253 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 1254 case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 1255 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 1256 case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 1257 return CVMX_ADD_IO_SEG(0x0001180008000240ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1258 case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 1259 return CVMX_ADD_IO_SEG(0x0001180008000240ull) + ((offset) + (block_id) * 0x0ull) * 2048; 1260 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 1261 return CVMX_ADD_IO_SEG(0x0001180008000240ull) + ((offset) + (block_id) * 0x2000ull) * 2048; 1262 } 1263 return CVMX_ADD_IO_SEG(0x0001180008000240ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1264} 1265 1266static inline uint64_t CVMX_GMXX_TXX_PAUSE_PKT_INTERVAL(unsigned long offset, unsigned long block_id) 1267{ 1268 switch (cvmx_get_octeon_family()) { 1269 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 1270 return CVMX_ADD_IO_SEG(0x0001180008000248ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1271 case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 1272 case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 1273 return CVMX_ADD_IO_SEG(0x0001180008000248ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1274 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 1275 case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 1276 return CVMX_ADD_IO_SEG(0x0001180008000248ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1277 case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 1278 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 1279 case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 1280 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 1281 case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 1282 return CVMX_ADD_IO_SEG(0x0001180008000248ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1283 case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 1284 return CVMX_ADD_IO_SEG(0x0001180008000248ull) + ((offset) + (block_id) * 0x0ull) * 2048; 1285 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 1286 return CVMX_ADD_IO_SEG(0x0001180008000248ull) + ((offset) + (block_id) * 0x2000ull) * 2048; 1287 } 1288 return CVMX_ADD_IO_SEG(0x0001180008000248ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1289} 1290 1291static inline uint64_t CVMX_GMXX_TXX_PAUSE_PKT_TIME(unsigned long offset, unsigned long block_id) 1292{ 1293 switch (cvmx_get_octeon_family()) { 1294 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 1295 return CVMX_ADD_IO_SEG(0x0001180008000238ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1296 case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 1297 case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 1298 return CVMX_ADD_IO_SEG(0x0001180008000238ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1299 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 1300 case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 1301 return CVMX_ADD_IO_SEG(0x0001180008000238ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1302 case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 1303 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 1304 case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 1305 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 1306 case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 1307 return CVMX_ADD_IO_SEG(0x0001180008000238ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1308 case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 1309 return CVMX_ADD_IO_SEG(0x0001180008000238ull) + ((offset) + (block_id) * 0x0ull) * 2048; 1310 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 1311 return CVMX_ADD_IO_SEG(0x0001180008000238ull) + ((offset) + (block_id) * 0x2000ull) * 2048; 1312 } 1313 return CVMX_ADD_IO_SEG(0x0001180008000238ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1314} 1315 1316static inline uint64_t CVMX_GMXX_TXX_PAUSE_TOGO(unsigned long offset, unsigned long block_id) 1317{ 1318 switch (cvmx_get_octeon_family()) { 1319 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 1320 return CVMX_ADD_IO_SEG(0x0001180008000258ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1321 case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 1322 case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 1323 return CVMX_ADD_IO_SEG(0x0001180008000258ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1324 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 1325 case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 1326 return CVMX_ADD_IO_SEG(0x0001180008000258ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1327 case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 1328 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 1329 case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 1330 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 1331 case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 1332 return CVMX_ADD_IO_SEG(0x0001180008000258ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1333 case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 1334 return CVMX_ADD_IO_SEG(0x0001180008000258ull) + ((offset) + (block_id) * 0x0ull) * 2048; 1335 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 1336 return CVMX_ADD_IO_SEG(0x0001180008000258ull) + ((offset) + (block_id) * 0x2000ull) * 2048; 1337 } 1338 return CVMX_ADD_IO_SEG(0x0001180008000258ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1339} 1340 1341static inline uint64_t CVMX_GMXX_TXX_PAUSE_ZERO(unsigned long offset, unsigned long block_id) 1342{ 1343 switch (cvmx_get_octeon_family()) { 1344 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 1345 return CVMX_ADD_IO_SEG(0x0001180008000260ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1346 case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 1347 case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 1348 return CVMX_ADD_IO_SEG(0x0001180008000260ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1349 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 1350 case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 1351 return CVMX_ADD_IO_SEG(0x0001180008000260ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1352 case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 1353 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 1354 case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 1355 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 1356 case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 1357 return CVMX_ADD_IO_SEG(0x0001180008000260ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1358 case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 1359 return CVMX_ADD_IO_SEG(0x0001180008000260ull) + ((offset) + (block_id) * 0x0ull) * 2048; 1360 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 1361 return CVMX_ADD_IO_SEG(0x0001180008000260ull) + ((offset) + (block_id) * 0x2000ull) * 2048; 1362 } 1363 return CVMX_ADD_IO_SEG(0x0001180008000260ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1364} 1365 1366#define CVMX_GMXX_TXX_PIPE(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000310ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048) 1367static inline uint64_t CVMX_GMXX_TXX_SGMII_CTL(unsigned long offset, unsigned long block_id) 1368{ 1369 switch (cvmx_get_octeon_family()) { 1370 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 1371 return CVMX_ADD_IO_SEG(0x0001180008000300ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1372 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 1373 case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 1374 return CVMX_ADD_IO_SEG(0x0001180008000300ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1375 case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 1376 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 1377 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 1378 return CVMX_ADD_IO_SEG(0x0001180008000300ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1379 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 1380 return CVMX_ADD_IO_SEG(0x0001180008000300ull) + ((offset) + (block_id) * 0x2000ull) * 2048; 1381 } 1382 return CVMX_ADD_IO_SEG(0x0001180008000300ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1383} 1384 1385static inline uint64_t CVMX_GMXX_TXX_SLOT(unsigned long offset, unsigned long block_id) 1386{ 1387 switch (cvmx_get_octeon_family()) { 1388 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 1389 return CVMX_ADD_IO_SEG(0x0001180008000220ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1390 case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 1391 case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 1392 return CVMX_ADD_IO_SEG(0x0001180008000220ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1393 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 1394 case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 1395 return CVMX_ADD_IO_SEG(0x0001180008000220ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1396 case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 1397 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 1398 case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 1399 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 1400 case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 1401 return CVMX_ADD_IO_SEG(0x0001180008000220ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1402 case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 1403 return CVMX_ADD_IO_SEG(0x0001180008000220ull) + ((offset) + (block_id) * 0x0ull) * 2048; 1404 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 1405 return CVMX_ADD_IO_SEG(0x0001180008000220ull) + ((offset) + (block_id) * 0x2000ull) * 2048; 1406 } 1407 return CVMX_ADD_IO_SEG(0x0001180008000220ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1408} 1409 1410static inline uint64_t CVMX_GMXX_TXX_SOFT_PAUSE(unsigned long offset, unsigned long block_id) 1411{ 1412 switch (cvmx_get_octeon_family()) { 1413 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 1414 return CVMX_ADD_IO_SEG(0x0001180008000250ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1415 case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 1416 case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 1417 return CVMX_ADD_IO_SEG(0x0001180008000250ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1418 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 1419 case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 1420 return CVMX_ADD_IO_SEG(0x0001180008000250ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1421 case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 1422 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 1423 case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 1424 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 1425 case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 1426 return CVMX_ADD_IO_SEG(0x0001180008000250ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1427 case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 1428 return CVMX_ADD_IO_SEG(0x0001180008000250ull) + ((offset) + (block_id) * 0x0ull) * 2048; 1429 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 1430 return CVMX_ADD_IO_SEG(0x0001180008000250ull) + ((offset) + (block_id) * 0x2000ull) * 2048; 1431 } 1432 return CVMX_ADD_IO_SEG(0x0001180008000250ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1433} 1434 1435static inline uint64_t CVMX_GMXX_TXX_STAT0(unsigned long offset, unsigned long block_id) 1436{ 1437 switch (cvmx_get_octeon_family()) { 1438 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 1439 return CVMX_ADD_IO_SEG(0x0001180008000280ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1440 case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 1441 case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 1442 return CVMX_ADD_IO_SEG(0x0001180008000280ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1443 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 1444 case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 1445 return CVMX_ADD_IO_SEG(0x0001180008000280ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1446 case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 1447 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 1448 case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 1449 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 1450 case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 1451 return CVMX_ADD_IO_SEG(0x0001180008000280ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1452 case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 1453 return CVMX_ADD_IO_SEG(0x0001180008000280ull) + ((offset) + (block_id) * 0x0ull) * 2048; 1454 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 1455 return CVMX_ADD_IO_SEG(0x0001180008000280ull) + ((offset) + (block_id) * 0x2000ull) * 2048; 1456 } 1457 return CVMX_ADD_IO_SEG(0x0001180008000280ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1458} 1459 1460static inline uint64_t CVMX_GMXX_TXX_STAT1(unsigned long offset, unsigned long block_id) 1461{ 1462 switch (cvmx_get_octeon_family()) { 1463 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 1464 return CVMX_ADD_IO_SEG(0x0001180008000288ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1465 case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 1466 case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 1467 return CVMX_ADD_IO_SEG(0x0001180008000288ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1468 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 1469 case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 1470 return CVMX_ADD_IO_SEG(0x0001180008000288ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1471 case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 1472 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 1473 case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 1474 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 1475 case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 1476 return CVMX_ADD_IO_SEG(0x0001180008000288ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1477 case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 1478 return CVMX_ADD_IO_SEG(0x0001180008000288ull) + ((offset) + (block_id) * 0x0ull) * 2048; 1479 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 1480 return CVMX_ADD_IO_SEG(0x0001180008000288ull) + ((offset) + (block_id) * 0x2000ull) * 2048; 1481 } 1482 return CVMX_ADD_IO_SEG(0x0001180008000288ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1483} 1484 1485static inline uint64_t CVMX_GMXX_TXX_STAT2(unsigned long offset, unsigned long block_id) 1486{ 1487 switch (cvmx_get_octeon_family()) { 1488 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 1489 return CVMX_ADD_IO_SEG(0x0001180008000290ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1490 case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 1491 case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 1492 return CVMX_ADD_IO_SEG(0x0001180008000290ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1493 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 1494 case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 1495 return CVMX_ADD_IO_SEG(0x0001180008000290ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1496 case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 1497 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 1498 case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 1499 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 1500 case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 1501 return CVMX_ADD_IO_SEG(0x0001180008000290ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1502 case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 1503 return CVMX_ADD_IO_SEG(0x0001180008000290ull) + ((offset) + (block_id) * 0x0ull) * 2048; 1504 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 1505 return CVMX_ADD_IO_SEG(0x0001180008000290ull) + ((offset) + (block_id) * 0x2000ull) * 2048; 1506 } 1507 return CVMX_ADD_IO_SEG(0x0001180008000290ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1508} 1509 1510static inline uint64_t CVMX_GMXX_TXX_STAT3(unsigned long offset, unsigned long block_id) 1511{ 1512 switch (cvmx_get_octeon_family()) { 1513 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 1514 return CVMX_ADD_IO_SEG(0x0001180008000298ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1515 case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 1516 case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 1517 return CVMX_ADD_IO_SEG(0x0001180008000298ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1518 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 1519 case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 1520 return CVMX_ADD_IO_SEG(0x0001180008000298ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1521 case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 1522 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 1523 case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 1524 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 1525 case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 1526 return CVMX_ADD_IO_SEG(0x0001180008000298ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1527 case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 1528 return CVMX_ADD_IO_SEG(0x0001180008000298ull) + ((offset) + (block_id) * 0x0ull) * 2048; 1529 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 1530 return CVMX_ADD_IO_SEG(0x0001180008000298ull) + ((offset) + (block_id) * 0x2000ull) * 2048; 1531 } 1532 return CVMX_ADD_IO_SEG(0x0001180008000298ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1533} 1534 1535static inline uint64_t CVMX_GMXX_TXX_STAT4(unsigned long offset, unsigned long block_id) 1536{ 1537 switch (cvmx_get_octeon_family()) { 1538 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 1539 return CVMX_ADD_IO_SEG(0x00011800080002A0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1540 case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 1541 case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 1542 return CVMX_ADD_IO_SEG(0x00011800080002A0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1543 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 1544 case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 1545 return CVMX_ADD_IO_SEG(0x00011800080002A0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1546 case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 1547 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 1548 case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 1549 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 1550 case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 1551 return CVMX_ADD_IO_SEG(0x00011800080002A0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1552 case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 1553 return CVMX_ADD_IO_SEG(0x00011800080002A0ull) + ((offset) + (block_id) * 0x0ull) * 2048; 1554 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 1555 return CVMX_ADD_IO_SEG(0x00011800080002A0ull) + ((offset) + (block_id) * 0x2000ull) * 2048; 1556 } 1557 return CVMX_ADD_IO_SEG(0x00011800080002A0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1558} 1559 1560static inline uint64_t CVMX_GMXX_TXX_STAT5(unsigned long offset, unsigned long block_id) 1561{ 1562 switch (cvmx_get_octeon_family()) { 1563 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 1564 return CVMX_ADD_IO_SEG(0x00011800080002A8ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1565 case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 1566 case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 1567 return CVMX_ADD_IO_SEG(0x00011800080002A8ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1568 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 1569 case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 1570 return CVMX_ADD_IO_SEG(0x00011800080002A8ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1571 case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 1572 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 1573 case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 1574 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 1575 case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 1576 return CVMX_ADD_IO_SEG(0x00011800080002A8ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1577 case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 1578 return CVMX_ADD_IO_SEG(0x00011800080002A8ull) + ((offset) + (block_id) * 0x0ull) * 2048; 1579 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 1580 return CVMX_ADD_IO_SEG(0x00011800080002A8ull) + ((offset) + (block_id) * 0x2000ull) * 2048; 1581 } 1582 return CVMX_ADD_IO_SEG(0x00011800080002A8ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1583} 1584 1585static inline uint64_t CVMX_GMXX_TXX_STAT6(unsigned long offset, unsigned long block_id) 1586{ 1587 switch (cvmx_get_octeon_family()) { 1588 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 1589 return CVMX_ADD_IO_SEG(0x00011800080002B0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1590 case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 1591 case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 1592 return CVMX_ADD_IO_SEG(0x00011800080002B0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1593 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 1594 case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 1595 return CVMX_ADD_IO_SEG(0x00011800080002B0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1596 case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 1597 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 1598 case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 1599 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 1600 case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 1601 return CVMX_ADD_IO_SEG(0x00011800080002B0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1602 case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 1603 return CVMX_ADD_IO_SEG(0x00011800080002B0ull) + ((offset) + (block_id) * 0x0ull) * 2048; 1604 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 1605 return CVMX_ADD_IO_SEG(0x00011800080002B0ull) + ((offset) + (block_id) * 0x2000ull) * 2048; 1606 } 1607 return CVMX_ADD_IO_SEG(0x00011800080002B0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1608} 1609 1610static inline uint64_t CVMX_GMXX_TXX_STAT7(unsigned long offset, unsigned long block_id) 1611{ 1612 switch (cvmx_get_octeon_family()) { 1613 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 1614 return CVMX_ADD_IO_SEG(0x00011800080002B8ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1615 case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 1616 case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 1617 return CVMX_ADD_IO_SEG(0x00011800080002B8ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1618 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 1619 case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 1620 return CVMX_ADD_IO_SEG(0x00011800080002B8ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1621 case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 1622 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 1623 case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 1624 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 1625 case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 1626 return CVMX_ADD_IO_SEG(0x00011800080002B8ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1627 case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 1628 return CVMX_ADD_IO_SEG(0x00011800080002B8ull) + ((offset) + (block_id) * 0x0ull) * 2048; 1629 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 1630 return CVMX_ADD_IO_SEG(0x00011800080002B8ull) + ((offset) + (block_id) * 0x2000ull) * 2048; 1631 } 1632 return CVMX_ADD_IO_SEG(0x00011800080002B8ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1633} 1634 1635static inline uint64_t CVMX_GMXX_TXX_STAT8(unsigned long offset, unsigned long block_id) 1636{ 1637 switch (cvmx_get_octeon_family()) { 1638 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 1639 return CVMX_ADD_IO_SEG(0x00011800080002C0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1640 case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 1641 case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 1642 return CVMX_ADD_IO_SEG(0x00011800080002C0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1643 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 1644 case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 1645 return CVMX_ADD_IO_SEG(0x00011800080002C0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1646 case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 1647 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 1648 case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 1649 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 1650 case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 1651 return CVMX_ADD_IO_SEG(0x00011800080002C0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1652 case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 1653 return CVMX_ADD_IO_SEG(0x00011800080002C0ull) + ((offset) + (block_id) * 0x0ull) * 2048; 1654 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 1655 return CVMX_ADD_IO_SEG(0x00011800080002C0ull) + ((offset) + (block_id) * 0x2000ull) * 2048; 1656 } 1657 return CVMX_ADD_IO_SEG(0x00011800080002C0ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1658} 1659 1660static inline uint64_t CVMX_GMXX_TXX_STAT9(unsigned long offset, unsigned long block_id) 1661{ 1662 switch (cvmx_get_octeon_family()) { 1663 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 1664 return CVMX_ADD_IO_SEG(0x00011800080002C8ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1665 case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 1666 case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 1667 return CVMX_ADD_IO_SEG(0x00011800080002C8ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1668 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 1669 case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 1670 return CVMX_ADD_IO_SEG(0x00011800080002C8ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1671 case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 1672 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 1673 case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 1674 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 1675 case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 1676 return CVMX_ADD_IO_SEG(0x00011800080002C8ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1677 case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 1678 return CVMX_ADD_IO_SEG(0x00011800080002C8ull) + ((offset) + (block_id) * 0x0ull) * 2048; 1679 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 1680 return CVMX_ADD_IO_SEG(0x00011800080002C8ull) + ((offset) + (block_id) * 0x2000ull) * 2048; 1681 } 1682 return CVMX_ADD_IO_SEG(0x00011800080002C8ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1683} 1684 1685static inline uint64_t CVMX_GMXX_TXX_STATS_CTL(unsigned long offset, unsigned long block_id) 1686{ 1687 switch (cvmx_get_octeon_family()) { 1688 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 1689 return CVMX_ADD_IO_SEG(0x0001180008000268ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1690 case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 1691 case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 1692 return CVMX_ADD_IO_SEG(0x0001180008000268ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1693 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 1694 case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 1695 return CVMX_ADD_IO_SEG(0x0001180008000268ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1696 case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 1697 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 1698 case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 1699 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 1700 case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 1701 return CVMX_ADD_IO_SEG(0x0001180008000268ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1702 case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 1703 return CVMX_ADD_IO_SEG(0x0001180008000268ull) + ((offset) + (block_id) * 0x0ull) * 2048; 1704 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 1705 return CVMX_ADD_IO_SEG(0x0001180008000268ull) + ((offset) + (block_id) * 0x2000ull) * 2048; 1706 } 1707 return CVMX_ADD_IO_SEG(0x0001180008000268ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1708} 1709 1710static inline uint64_t CVMX_GMXX_TXX_THRESH(unsigned long offset, unsigned long block_id) 1711{ 1712 switch (cvmx_get_octeon_family()) { 1713 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 1714 return CVMX_ADD_IO_SEG(0x0001180008000210ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1715 case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 1716 case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 1717 return CVMX_ADD_IO_SEG(0x0001180008000210ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1718 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 1719 case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 1720 return CVMX_ADD_IO_SEG(0x0001180008000210ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1721 case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 1722 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 1723 case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 1724 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 1725 case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 1726 return CVMX_ADD_IO_SEG(0x0001180008000210ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1727 case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 1728 return CVMX_ADD_IO_SEG(0x0001180008000210ull) + ((offset) + (block_id) * 0x0ull) * 2048; 1729 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 1730 return CVMX_ADD_IO_SEG(0x0001180008000210ull) + ((offset) + (block_id) * 0x2000ull) * 2048; 1731 } 1732 return CVMX_ADD_IO_SEG(0x0001180008000210ull) + ((offset) + (block_id) * 0x10000ull) * 2048; 1733} 1734 1735static inline uint64_t CVMX_GMXX_TX_BP(unsigned long block_id) 1736{ 1737 switch (cvmx_get_octeon_family()) { 1738 case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 1739 case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 1740 case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 1741 case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 1742 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 1743 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 1744 return CVMX_ADD_IO_SEG(0x00011800080004D0ull) + (block_id) * 0x8000000ull; 1745 case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 1746 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 1747 case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 1748 case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 1749 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 1750 return CVMX_ADD_IO_SEG(0x00011800080004D0ull) + (block_id) * 0x8000000ull; 1751 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 1752 return CVMX_ADD_IO_SEG(0x00011800080004D0ull) + (block_id) * 0x1000000ull; 1753 } 1754 return CVMX_ADD_IO_SEG(0x00011800080004D0ull) + (block_id) * 0x8000000ull; 1755} 1756 1757#define CVMX_GMXX_TX_CLK_MSKX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000780ull) + (((offset) & 1) + ((block_id) & 0) * 0x0ull) * 8) 1758static inline uint64_t CVMX_GMXX_TX_COL_ATTEMPT(unsigned long block_id) 1759{ 1760 switch (cvmx_get_octeon_family()) { 1761 case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 1762 case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 1763 case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 1764 case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 1765 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 1766 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 1767 return CVMX_ADD_IO_SEG(0x0001180008000498ull) + (block_id) * 0x8000000ull; 1768 case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 1769 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 1770 case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 1771 case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 1772 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 1773 return CVMX_ADD_IO_SEG(0x0001180008000498ull) + (block_id) * 0x8000000ull; 1774 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 1775 return CVMX_ADD_IO_SEG(0x0001180008000498ull) + (block_id) * 0x1000000ull; 1776 } 1777 return CVMX_ADD_IO_SEG(0x0001180008000498ull) + (block_id) * 0x8000000ull; 1778} 1779 1780static inline uint64_t CVMX_GMXX_TX_CORRUPT(unsigned long block_id) 1781{ 1782 switch (cvmx_get_octeon_family()) { 1783 case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 1784 case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 1785 case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 1786 case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 1787 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 1788 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 1789 return CVMX_ADD_IO_SEG(0x00011800080004D8ull) + (block_id) * 0x8000000ull; 1790 case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 1791 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 1792 case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 1793 case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 1794 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 1795 return CVMX_ADD_IO_SEG(0x00011800080004D8ull) + (block_id) * 0x8000000ull; 1796 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 1797 return CVMX_ADD_IO_SEG(0x00011800080004D8ull) + (block_id) * 0x1000000ull; 1798 } 1799 return CVMX_ADD_IO_SEG(0x00011800080004D8ull) + (block_id) * 0x8000000ull; 1800} 1801 1802static inline uint64_t CVMX_GMXX_TX_HG2_REG1(unsigned long block_id) 1803{ 1804 switch (cvmx_get_octeon_family()) { 1805 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 1806 case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 1807 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 1808 return CVMX_ADD_IO_SEG(0x0001180008000558ull) + (block_id) * 0x8000000ull; 1809 case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 1810 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 1811 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 1812 return CVMX_ADD_IO_SEG(0x0001180008000558ull) + (block_id) * 0x8000000ull; 1813 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 1814 return CVMX_ADD_IO_SEG(0x0001180008000558ull) + (block_id) * 0x1000000ull; 1815 } 1816 return CVMX_ADD_IO_SEG(0x0001180008000558ull) + (block_id) * 0x8000000ull; 1817} 1818 1819static inline uint64_t CVMX_GMXX_TX_HG2_REG2(unsigned long block_id) 1820{ 1821 switch (cvmx_get_octeon_family()) { 1822 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 1823 case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 1824 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 1825 return CVMX_ADD_IO_SEG(0x0001180008000560ull) + (block_id) * 0x8000000ull; 1826 case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 1827 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 1828 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 1829 return CVMX_ADD_IO_SEG(0x0001180008000560ull) + (block_id) * 0x8000000ull; 1830 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 1831 return CVMX_ADD_IO_SEG(0x0001180008000560ull) + (block_id) * 0x1000000ull; 1832 } 1833 return CVMX_ADD_IO_SEG(0x0001180008000560ull) + (block_id) * 0x8000000ull; 1834} 1835 1836static inline uint64_t CVMX_GMXX_TX_IFG(unsigned long block_id) 1837{ 1838 switch (cvmx_get_octeon_family()) { 1839 case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 1840 case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 1841 case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 1842 case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 1843 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 1844 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 1845 return CVMX_ADD_IO_SEG(0x0001180008000488ull) + (block_id) * 0x8000000ull; 1846 case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 1847 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 1848 case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 1849 case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 1850 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 1851 return CVMX_ADD_IO_SEG(0x0001180008000488ull) + (block_id) * 0x8000000ull; 1852 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 1853 return CVMX_ADD_IO_SEG(0x0001180008000488ull) + (block_id) * 0x1000000ull; 1854 } 1855 return CVMX_ADD_IO_SEG(0x0001180008000488ull) + (block_id) * 0x8000000ull; 1856} 1857 1858static inline uint64_t CVMX_GMXX_TX_INT_EN(unsigned long block_id) 1859{ 1860 switch (cvmx_get_octeon_family()) { 1861 case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 1862 case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 1863 case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 1864 case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 1865 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 1866 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 1867 return CVMX_ADD_IO_SEG(0x0001180008000508ull) + (block_id) * 0x8000000ull; 1868 case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 1869 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 1870 case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 1871 case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 1872 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 1873 return CVMX_ADD_IO_SEG(0x0001180008000508ull) + (block_id) * 0x8000000ull; 1874 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 1875 return CVMX_ADD_IO_SEG(0x0001180008000508ull) + (block_id) * 0x1000000ull; 1876 } 1877 return CVMX_ADD_IO_SEG(0x0001180008000508ull) + (block_id) * 0x8000000ull; 1878} 1879 1880static inline uint64_t CVMX_GMXX_TX_INT_REG(unsigned long block_id) 1881{ 1882 switch (cvmx_get_octeon_family()) { 1883 case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 1884 case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 1885 case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 1886 case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 1887 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 1888 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 1889 return CVMX_ADD_IO_SEG(0x0001180008000500ull) + (block_id) * 0x8000000ull; 1890 case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 1891 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 1892 case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 1893 case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 1894 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 1895 return CVMX_ADD_IO_SEG(0x0001180008000500ull) + (block_id) * 0x8000000ull; 1896 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 1897 return CVMX_ADD_IO_SEG(0x0001180008000500ull) + (block_id) * 0x1000000ull; 1898 } 1899 return CVMX_ADD_IO_SEG(0x0001180008000500ull) + (block_id) * 0x8000000ull; 1900} 1901 1902static inline uint64_t CVMX_GMXX_TX_JAM(unsigned long block_id) 1903{ 1904 switch (cvmx_get_octeon_family()) { 1905 case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 1906 case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 1907 case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 1908 case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 1909 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 1910 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 1911 return CVMX_ADD_IO_SEG(0x0001180008000490ull) + (block_id) * 0x8000000ull; 1912 case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 1913 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 1914 case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 1915 case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 1916 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 1917 return CVMX_ADD_IO_SEG(0x0001180008000490ull) + (block_id) * 0x8000000ull; 1918 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 1919 return CVMX_ADD_IO_SEG(0x0001180008000490ull) + (block_id) * 0x1000000ull; 1920 } 1921 return CVMX_ADD_IO_SEG(0x0001180008000490ull) + (block_id) * 0x8000000ull; 1922} 1923 1924static inline uint64_t CVMX_GMXX_TX_LFSR(unsigned long block_id) 1925{ 1926 switch (cvmx_get_octeon_family()) { 1927 case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 1928 case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 1929 case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 1930 case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 1931 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 1932 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 1933 return CVMX_ADD_IO_SEG(0x00011800080004F8ull) + (block_id) * 0x8000000ull; 1934 case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 1935 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 1936 case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 1937 case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 1938 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 1939 return CVMX_ADD_IO_SEG(0x00011800080004F8ull) + (block_id) * 0x8000000ull; 1940 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 1941 return CVMX_ADD_IO_SEG(0x00011800080004F8ull) + (block_id) * 0x1000000ull; 1942 } 1943 return CVMX_ADD_IO_SEG(0x00011800080004F8ull) + (block_id) * 0x8000000ull; 1944} 1945 1946static inline uint64_t CVMX_GMXX_TX_OVR_BP(unsigned long block_id) 1947{ 1948 switch (cvmx_get_octeon_family()) { 1949 case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 1950 case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 1951 case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 1952 case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 1953 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 1954 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 1955 return CVMX_ADD_IO_SEG(0x00011800080004C8ull) + (block_id) * 0x8000000ull; 1956 case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 1957 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 1958 case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 1959 case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 1960 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 1961 return CVMX_ADD_IO_SEG(0x00011800080004C8ull) + (block_id) * 0x8000000ull; 1962 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 1963 return CVMX_ADD_IO_SEG(0x00011800080004C8ull) + (block_id) * 0x1000000ull; 1964 } 1965 return CVMX_ADD_IO_SEG(0x00011800080004C8ull) + (block_id) * 0x8000000ull; 1966} 1967 1968static inline uint64_t CVMX_GMXX_TX_PAUSE_PKT_DMAC(unsigned long block_id) 1969{ 1970 switch (cvmx_get_octeon_family()) { 1971 case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 1972 case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 1973 case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 1974 case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 1975 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 1976 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 1977 return CVMX_ADD_IO_SEG(0x00011800080004A0ull) + (block_id) * 0x8000000ull; 1978 case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 1979 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 1980 case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 1981 case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 1982 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 1983 return CVMX_ADD_IO_SEG(0x00011800080004A0ull) + (block_id) * 0x8000000ull; 1984 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 1985 return CVMX_ADD_IO_SEG(0x00011800080004A0ull) + (block_id) * 0x1000000ull; 1986 } 1987 return CVMX_ADD_IO_SEG(0x00011800080004A0ull) + (block_id) * 0x8000000ull; 1988} 1989 1990static inline uint64_t CVMX_GMXX_TX_PAUSE_PKT_TYPE(unsigned long block_id) 1991{ 1992 switch (cvmx_get_octeon_family()) { 1993 case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 1994 case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 1995 case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 1996 case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 1997 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 1998 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 1999 return CVMX_ADD_IO_SEG(0x00011800080004A8ull) + (block_id) * 0x8000000ull; 2000 case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 2001 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 2002 case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 2003 case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 2004 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 2005 return CVMX_ADD_IO_SEG(0x00011800080004A8ull) + (block_id) * 0x8000000ull; 2006 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 2007 return CVMX_ADD_IO_SEG(0x00011800080004A8ull) + (block_id) * 0x1000000ull; 2008 } 2009 return CVMX_ADD_IO_SEG(0x00011800080004A8ull) + (block_id) * 0x8000000ull; 2010} 2011 2012static inline uint64_t CVMX_GMXX_TX_PRTS(unsigned long block_id) 2013{ 2014 switch (cvmx_get_octeon_family()) { 2015 case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 2016 case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 2017 case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 2018 case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 2019 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 2020 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 2021 return CVMX_ADD_IO_SEG(0x0001180008000480ull) + (block_id) * 0x8000000ull; 2022 case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 2023 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 2024 case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 2025 case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 2026 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 2027 return CVMX_ADD_IO_SEG(0x0001180008000480ull) + (block_id) * 0x8000000ull; 2028 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 2029 return CVMX_ADD_IO_SEG(0x0001180008000480ull) + (block_id) * 0x1000000ull; 2030 } 2031 return CVMX_ADD_IO_SEG(0x0001180008000480ull) + (block_id) * 0x8000000ull; 2032} 2033 2034#define CVMX_GMXX_TX_SPI_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800080004C0ull) + ((block_id) & 1) * 0x8000000ull) 2035#define CVMX_GMXX_TX_SPI_DRAIN(block_id) (CVMX_ADD_IO_SEG(0x00011800080004E0ull) + ((block_id) & 1) * 0x8000000ull) 2036#define CVMX_GMXX_TX_SPI_MAX(block_id) (CVMX_ADD_IO_SEG(0x00011800080004B0ull) + ((block_id) & 1) * 0x8000000ull) 2037#define CVMX_GMXX_TX_SPI_ROUNDX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000680ull) + (((offset) & 31) + ((block_id) & 1) * 0x1000000ull) * 8) 2038#define CVMX_GMXX_TX_SPI_THRESH(block_id) (CVMX_ADD_IO_SEG(0x00011800080004B8ull) + ((block_id) & 1) * 0x8000000ull) 2039static inline uint64_t CVMX_GMXX_TX_XAUI_CTL(unsigned long block_id) 2040{ 2041 switch (cvmx_get_octeon_family()) { 2042 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 2043 case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 2044 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 2045 return CVMX_ADD_IO_SEG(0x0001180008000528ull) + (block_id) * 0x8000000ull; 2046 case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 2047 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 2048 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 2049 return CVMX_ADD_IO_SEG(0x0001180008000528ull) + (block_id) * 0x8000000ull; 2050 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 2051 return CVMX_ADD_IO_SEG(0x0001180008000528ull) + (block_id) * 0x1000000ull; 2052 } 2053 return CVMX_ADD_IO_SEG(0x0001180008000528ull) + (block_id) * 0x8000000ull; 2054} 2055 2056static inline uint64_t CVMX_GMXX_XAUI_EXT_LOOPBACK(unsigned long block_id) 2057{ 2058 switch (cvmx_get_octeon_family()) { 2059 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 2060 case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 2061 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 2062 return CVMX_ADD_IO_SEG(0x0001180008000540ull) + (block_id) * 0x8000000ull; 2063 case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 2064 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 2065 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 2066 return CVMX_ADD_IO_SEG(0x0001180008000540ull) + (block_id) * 0x8000000ull; 2067 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 2068 return CVMX_ADD_IO_SEG(0x0001180008000540ull) + (block_id) * 0x1000000ull; 2069 } 2070 return CVMX_ADD_IO_SEG(0x0001180008000540ull) + (block_id) * 0x8000000ull; 2071} 2072 2073union cvmx_gmxx_bad_reg { 2074 uint64_t u64; 2075 struct cvmx_gmxx_bad_reg_s { 2076#ifdef __BIG_ENDIAN_BITFIELD 2077 uint64_t reserved_31_63:33; 2078 uint64_t inb_nxa:4; 2079 uint64_t statovr:1; 2080 uint64_t loststat:4; 2081 uint64_t reserved_18_21:4; 2082 uint64_t out_ovr:16; 2083 uint64_t ncb_ovr:1; 2084 uint64_t out_col:1; 2085#else 2086 uint64_t out_col:1; 2087 uint64_t ncb_ovr:1; 2088 uint64_t out_ovr:16; 2089 uint64_t reserved_18_21:4; 2090 uint64_t loststat:4; 2091 uint64_t statovr:1; 2092 uint64_t inb_nxa:4; 2093 uint64_t reserved_31_63:33; 2094#endif 2095 } s; 2096 struct cvmx_gmxx_bad_reg_cn30xx { 2097#ifdef __BIG_ENDIAN_BITFIELD 2098 uint64_t reserved_31_63:33; 2099 uint64_t inb_nxa:4; 2100 uint64_t statovr:1; 2101 uint64_t reserved_25_25:1; 2102 uint64_t loststat:3; 2103 uint64_t reserved_5_21:17; 2104 uint64_t out_ovr:3; 2105 uint64_t reserved_0_1:2; 2106#else 2107 uint64_t reserved_0_1:2; 2108 uint64_t out_ovr:3; 2109 uint64_t reserved_5_21:17; 2110 uint64_t loststat:3; 2111 uint64_t reserved_25_25:1; 2112 uint64_t statovr:1; 2113 uint64_t inb_nxa:4; 2114 uint64_t reserved_31_63:33; 2115#endif 2116 } cn30xx; 2117 struct cvmx_gmxx_bad_reg_cn30xx cn31xx; 2118 struct cvmx_gmxx_bad_reg_s cn38xx; 2119 struct cvmx_gmxx_bad_reg_s cn38xxp2; 2120 struct cvmx_gmxx_bad_reg_cn30xx cn50xx; 2121 struct cvmx_gmxx_bad_reg_cn52xx { 2122#ifdef __BIG_ENDIAN_BITFIELD 2123 uint64_t reserved_31_63:33; 2124 uint64_t inb_nxa:4; 2125 uint64_t statovr:1; 2126 uint64_t loststat:4; 2127 uint64_t reserved_6_21:16; 2128 uint64_t out_ovr:4; 2129 uint64_t reserved_0_1:2; 2130#else 2131 uint64_t reserved_0_1:2; 2132 uint64_t out_ovr:4; 2133 uint64_t reserved_6_21:16; 2134 uint64_t loststat:4; 2135 uint64_t statovr:1; 2136 uint64_t inb_nxa:4; 2137 uint64_t reserved_31_63:33; 2138#endif 2139 } cn52xx; 2140 struct cvmx_gmxx_bad_reg_cn52xx cn52xxp1; 2141 struct cvmx_gmxx_bad_reg_cn52xx cn56xx; 2142 struct cvmx_gmxx_bad_reg_cn52xx cn56xxp1; 2143 struct cvmx_gmxx_bad_reg_s cn58xx; 2144 struct cvmx_gmxx_bad_reg_s cn58xxp1; 2145 struct cvmx_gmxx_bad_reg_cn52xx cn61xx; 2146 struct cvmx_gmxx_bad_reg_cn52xx cn63xx; 2147 struct cvmx_gmxx_bad_reg_cn52xx cn63xxp1; 2148 struct cvmx_gmxx_bad_reg_cn52xx cn66xx; 2149 struct cvmx_gmxx_bad_reg_cn52xx cn68xx; 2150 struct cvmx_gmxx_bad_reg_cn52xx cn68xxp1; 2151 struct cvmx_gmxx_bad_reg_cn52xx cnf71xx; 2152}; 2153 2154union cvmx_gmxx_bist { 2155 uint64_t u64; 2156 struct cvmx_gmxx_bist_s { 2157#ifdef __BIG_ENDIAN_BITFIELD 2158 uint64_t reserved_25_63:39; 2159 uint64_t status:25; 2160#else 2161 uint64_t status:25; 2162 uint64_t reserved_25_63:39; 2163#endif 2164 } s; 2165 struct cvmx_gmxx_bist_cn30xx { 2166#ifdef __BIG_ENDIAN_BITFIELD 2167 uint64_t reserved_10_63:54; 2168 uint64_t status:10; 2169#else 2170 uint64_t status:10; 2171 uint64_t reserved_10_63:54; 2172#endif 2173 } cn30xx; 2174 struct cvmx_gmxx_bist_cn30xx cn31xx; 2175 struct cvmx_gmxx_bist_cn30xx cn38xx; 2176 struct cvmx_gmxx_bist_cn30xx cn38xxp2; 2177 struct cvmx_gmxx_bist_cn50xx { 2178#ifdef __BIG_ENDIAN_BITFIELD 2179 uint64_t reserved_12_63:52; 2180 uint64_t status:12; 2181#else 2182 uint64_t status:12; 2183 uint64_t reserved_12_63:52; 2184#endif 2185 } cn50xx; 2186 struct cvmx_gmxx_bist_cn52xx { 2187#ifdef __BIG_ENDIAN_BITFIELD 2188 uint64_t reserved_16_63:48; 2189 uint64_t status:16; 2190#else 2191 uint64_t status:16; 2192 uint64_t reserved_16_63:48; 2193#endif 2194 } cn52xx; 2195 struct cvmx_gmxx_bist_cn52xx cn52xxp1; 2196 struct cvmx_gmxx_bist_cn52xx cn56xx; 2197 struct cvmx_gmxx_bist_cn52xx cn56xxp1; 2198 struct cvmx_gmxx_bist_cn58xx { 2199#ifdef __BIG_ENDIAN_BITFIELD 2200 uint64_t reserved_17_63:47; 2201 uint64_t status:17; 2202#else 2203 uint64_t status:17; 2204 uint64_t reserved_17_63:47; 2205#endif 2206 } cn58xx; 2207 struct cvmx_gmxx_bist_cn58xx cn58xxp1; 2208 struct cvmx_gmxx_bist_s cn61xx; 2209 struct cvmx_gmxx_bist_s cn63xx; 2210 struct cvmx_gmxx_bist_s cn63xxp1; 2211 struct cvmx_gmxx_bist_s cn66xx; 2212 struct cvmx_gmxx_bist_s cn68xx; 2213 struct cvmx_gmxx_bist_s cn68xxp1; 2214 struct cvmx_gmxx_bist_s cnf71xx; 2215}; 2216 2217union cvmx_gmxx_bpid_mapx { 2218 uint64_t u64; 2219 struct cvmx_gmxx_bpid_mapx_s { 2220#ifdef __BIG_ENDIAN_BITFIELD 2221 uint64_t reserved_17_63:47; 2222 uint64_t status:1; 2223 uint64_t reserved_9_15:7; 2224 uint64_t val:1; 2225 uint64_t reserved_6_7:2; 2226 uint64_t bpid:6; 2227#else 2228 uint64_t bpid:6; 2229 uint64_t reserved_6_7:2; 2230 uint64_t val:1; 2231 uint64_t reserved_9_15:7; 2232 uint64_t status:1; 2233 uint64_t reserved_17_63:47; 2234#endif 2235 } s; 2236 struct cvmx_gmxx_bpid_mapx_s cn68xx; 2237 struct cvmx_gmxx_bpid_mapx_s cn68xxp1; 2238}; 2239 2240union cvmx_gmxx_bpid_msk { 2241 uint64_t u64; 2242 struct cvmx_gmxx_bpid_msk_s { 2243#ifdef __BIG_ENDIAN_BITFIELD 2244 uint64_t reserved_48_63:16; 2245 uint64_t msk_or:16; 2246 uint64_t reserved_16_31:16; 2247 uint64_t msk_and:16; 2248#else 2249 uint64_t msk_and:16; 2250 uint64_t reserved_16_31:16; 2251 uint64_t msk_or:16; 2252 uint64_t reserved_48_63:16; 2253#endif 2254 } s; 2255 struct cvmx_gmxx_bpid_msk_s cn68xx; 2256 struct cvmx_gmxx_bpid_msk_s cn68xxp1; 2257}; 2258 2259union cvmx_gmxx_clk_en { 2260 uint64_t u64; 2261 struct cvmx_gmxx_clk_en_s { 2262#ifdef __BIG_ENDIAN_BITFIELD 2263 uint64_t reserved_1_63:63; 2264 uint64_t clk_en:1; 2265#else 2266 uint64_t clk_en:1; 2267 uint64_t reserved_1_63:63; 2268#endif 2269 } s; 2270 struct cvmx_gmxx_clk_en_s cn52xx; 2271 struct cvmx_gmxx_clk_en_s cn52xxp1; 2272 struct cvmx_gmxx_clk_en_s cn56xx; 2273 struct cvmx_gmxx_clk_en_s cn56xxp1; 2274 struct cvmx_gmxx_clk_en_s cn61xx; 2275 struct cvmx_gmxx_clk_en_s cn63xx; 2276 struct cvmx_gmxx_clk_en_s cn63xxp1; 2277 struct cvmx_gmxx_clk_en_s cn66xx; 2278 struct cvmx_gmxx_clk_en_s cn68xx; 2279 struct cvmx_gmxx_clk_en_s cn68xxp1; 2280 struct cvmx_gmxx_clk_en_s cnf71xx; 2281}; 2282 2283union cvmx_gmxx_ebp_dis { 2284 uint64_t u64; 2285 struct cvmx_gmxx_ebp_dis_s { 2286#ifdef __BIG_ENDIAN_BITFIELD 2287 uint64_t reserved_16_63:48; 2288 uint64_t dis:16; 2289#else 2290 uint64_t dis:16; 2291 uint64_t reserved_16_63:48; 2292#endif 2293 } s; 2294 struct cvmx_gmxx_ebp_dis_s cn68xx; 2295 struct cvmx_gmxx_ebp_dis_s cn68xxp1; 2296}; 2297 2298union cvmx_gmxx_ebp_msk { 2299 uint64_t u64; 2300 struct cvmx_gmxx_ebp_msk_s { 2301#ifdef __BIG_ENDIAN_BITFIELD 2302 uint64_t reserved_16_63:48; 2303 uint64_t msk:16; 2304#else 2305 uint64_t msk:16; 2306 uint64_t reserved_16_63:48; 2307#endif 2308 } s; 2309 struct cvmx_gmxx_ebp_msk_s cn68xx; 2310 struct cvmx_gmxx_ebp_msk_s cn68xxp1; 2311}; 2312 2313union cvmx_gmxx_hg2_control { 2314 uint64_t u64; 2315 struct cvmx_gmxx_hg2_control_s { 2316#ifdef __BIG_ENDIAN_BITFIELD 2317 uint64_t reserved_19_63:45; 2318 uint64_t hg2tx_en:1; 2319 uint64_t hg2rx_en:1; 2320 uint64_t phys_en:1; 2321 uint64_t logl_en:16; 2322#else 2323 uint64_t logl_en:16; 2324 uint64_t phys_en:1; 2325 uint64_t hg2rx_en:1; 2326 uint64_t hg2tx_en:1; 2327 uint64_t reserved_19_63:45; 2328#endif 2329 } s; 2330 struct cvmx_gmxx_hg2_control_s cn52xx; 2331 struct cvmx_gmxx_hg2_control_s cn52xxp1; 2332 struct cvmx_gmxx_hg2_control_s cn56xx; 2333 struct cvmx_gmxx_hg2_control_s cn61xx; 2334 struct cvmx_gmxx_hg2_control_s cn63xx; 2335 struct cvmx_gmxx_hg2_control_s cn63xxp1; 2336 struct cvmx_gmxx_hg2_control_s cn66xx; 2337 struct cvmx_gmxx_hg2_control_s cn68xx; 2338 struct cvmx_gmxx_hg2_control_s cn68xxp1; 2339 struct cvmx_gmxx_hg2_control_s cnf71xx; 2340}; 2341 2342union cvmx_gmxx_inf_mode { 2343 uint64_t u64; 2344 struct cvmx_gmxx_inf_mode_s { 2345#ifdef __BIG_ENDIAN_BITFIELD 2346 uint64_t reserved_20_63:44; 2347 uint64_t rate:4; 2348 uint64_t reserved_12_15:4; 2349 uint64_t speed:4; 2350 uint64_t reserved_7_7:1; 2351 uint64_t mode:3; 2352 uint64_t reserved_3_3:1; 2353 uint64_t p0mii:1; 2354 uint64_t en:1; 2355 uint64_t type:1; 2356#else 2357 uint64_t type:1; 2358 uint64_t en:1; 2359 uint64_t p0mii:1; 2360 uint64_t reserved_3_3:1; 2361 uint64_t mode:3; 2362 uint64_t reserved_7_7:1; 2363 uint64_t speed:4; 2364 uint64_t reserved_12_15:4; 2365 uint64_t rate:4; 2366 uint64_t reserved_20_63:44; 2367#endif 2368 } s; 2369 struct cvmx_gmxx_inf_mode_cn30xx { 2370#ifdef __BIG_ENDIAN_BITFIELD 2371 uint64_t reserved_3_63:61; 2372 uint64_t p0mii:1; 2373 uint64_t en:1; 2374 uint64_t type:1; 2375#else 2376 uint64_t type:1; 2377 uint64_t en:1; 2378 uint64_t p0mii:1; 2379 uint64_t reserved_3_63:61; 2380#endif 2381 } cn30xx; 2382 struct cvmx_gmxx_inf_mode_cn31xx { 2383#ifdef __BIG_ENDIAN_BITFIELD 2384 uint64_t reserved_2_63:62; 2385 uint64_t en:1; 2386 uint64_t type:1; 2387#else 2388 uint64_t type:1; 2389 uint64_t en:1; 2390 uint64_t reserved_2_63:62; 2391#endif 2392 } cn31xx; 2393 struct cvmx_gmxx_inf_mode_cn31xx cn38xx; 2394 struct cvmx_gmxx_inf_mode_cn31xx cn38xxp2; 2395 struct cvmx_gmxx_inf_mode_cn30xx cn50xx; 2396 struct cvmx_gmxx_inf_mode_cn52xx { 2397#ifdef __BIG_ENDIAN_BITFIELD 2398 uint64_t reserved_10_63:54; 2399 uint64_t speed:2; 2400 uint64_t reserved_6_7:2; 2401 uint64_t mode:2; 2402 uint64_t reserved_2_3:2; 2403 uint64_t en:1; 2404 uint64_t type:1; 2405#else 2406 uint64_t type:1; 2407 uint64_t en:1; 2408 uint64_t reserved_2_3:2; 2409 uint64_t mode:2; 2410 uint64_t reserved_6_7:2; 2411 uint64_t speed:2; 2412 uint64_t reserved_10_63:54; 2413#endif 2414 } cn52xx; 2415 struct cvmx_gmxx_inf_mode_cn52xx cn52xxp1; 2416 struct cvmx_gmxx_inf_mode_cn52xx cn56xx; 2417 struct cvmx_gmxx_inf_mode_cn52xx cn56xxp1; 2418 struct cvmx_gmxx_inf_mode_cn31xx cn58xx; 2419 struct cvmx_gmxx_inf_mode_cn31xx cn58xxp1; 2420 struct cvmx_gmxx_inf_mode_cn61xx { 2421#ifdef __BIG_ENDIAN_BITFIELD 2422 uint64_t reserved_12_63:52; 2423 uint64_t speed:4; 2424 uint64_t reserved_5_7:3; 2425 uint64_t mode:1; 2426 uint64_t reserved_2_3:2; 2427 uint64_t en:1; 2428 uint64_t type:1; 2429#else 2430 uint64_t type:1; 2431 uint64_t en:1; 2432 uint64_t reserved_2_3:2; 2433 uint64_t mode:1; 2434 uint64_t reserved_5_7:3; 2435 uint64_t speed:4; 2436 uint64_t reserved_12_63:52; 2437#endif 2438 } cn61xx; 2439 struct cvmx_gmxx_inf_mode_cn61xx cn63xx; 2440 struct cvmx_gmxx_inf_mode_cn61xx cn63xxp1; 2441 struct cvmx_gmxx_inf_mode_cn66xx { 2442#ifdef __BIG_ENDIAN_BITFIELD 2443 uint64_t reserved_20_63:44; 2444 uint64_t rate:4; 2445 uint64_t reserved_12_15:4; 2446 uint64_t speed:4; 2447 uint64_t reserved_5_7:3; 2448 uint64_t mode:1; 2449 uint64_t reserved_2_3:2; 2450 uint64_t en:1; 2451 uint64_t type:1; 2452#else 2453 uint64_t type:1; 2454 uint64_t en:1; 2455 uint64_t reserved_2_3:2; 2456 uint64_t mode:1; 2457 uint64_t reserved_5_7:3; 2458 uint64_t speed:4; 2459 uint64_t reserved_12_15:4; 2460 uint64_t rate:4; 2461 uint64_t reserved_20_63:44; 2462#endif 2463 } cn66xx; 2464 struct cvmx_gmxx_inf_mode_cn68xx { 2465#ifdef __BIG_ENDIAN_BITFIELD 2466 uint64_t reserved_12_63:52; 2467 uint64_t speed:4; 2468 uint64_t reserved_7_7:1; 2469 uint64_t mode:3; 2470 uint64_t reserved_2_3:2; 2471 uint64_t en:1; 2472 uint64_t type:1; 2473#else 2474 uint64_t type:1; 2475 uint64_t en:1; 2476 uint64_t reserved_2_3:2; 2477 uint64_t mode:3; 2478 uint64_t reserved_7_7:1; 2479 uint64_t speed:4; 2480 uint64_t reserved_12_63:52; 2481#endif 2482 } cn68xx; 2483 struct cvmx_gmxx_inf_mode_cn68xx cn68xxp1; 2484 struct cvmx_gmxx_inf_mode_cn61xx cnf71xx; 2485}; 2486 2487union cvmx_gmxx_nxa_adr { 2488 uint64_t u64; 2489 struct cvmx_gmxx_nxa_adr_s { 2490#ifdef __BIG_ENDIAN_BITFIELD 2491 uint64_t reserved_23_63:41; 2492 uint64_t pipe:7; 2493 uint64_t reserved_6_15:10; 2494 uint64_t prt:6; 2495#else 2496 uint64_t prt:6; 2497 uint64_t reserved_6_15:10; 2498 uint64_t pipe:7; 2499 uint64_t reserved_23_63:41; 2500#endif 2501 } s; 2502 struct cvmx_gmxx_nxa_adr_cn30xx { 2503#ifdef __BIG_ENDIAN_BITFIELD 2504 uint64_t reserved_6_63:58; 2505 uint64_t prt:6; 2506#else 2507 uint64_t prt:6; 2508 uint64_t reserved_6_63:58; 2509#endif 2510 } cn30xx; 2511 struct cvmx_gmxx_nxa_adr_cn30xx cn31xx; 2512 struct cvmx_gmxx_nxa_adr_cn30xx cn38xx; 2513 struct cvmx_gmxx_nxa_adr_cn30xx cn38xxp2; 2514 struct cvmx_gmxx_nxa_adr_cn30xx cn50xx; 2515 struct cvmx_gmxx_nxa_adr_cn30xx cn52xx; 2516 struct cvmx_gmxx_nxa_adr_cn30xx cn52xxp1; 2517 struct cvmx_gmxx_nxa_adr_cn30xx cn56xx; 2518 struct cvmx_gmxx_nxa_adr_cn30xx cn56xxp1; 2519 struct cvmx_gmxx_nxa_adr_cn30xx cn58xx; 2520 struct cvmx_gmxx_nxa_adr_cn30xx cn58xxp1; 2521 struct cvmx_gmxx_nxa_adr_cn30xx cn61xx; 2522 struct cvmx_gmxx_nxa_adr_cn30xx cn63xx; 2523 struct cvmx_gmxx_nxa_adr_cn30xx cn63xxp1; 2524 struct cvmx_gmxx_nxa_adr_cn30xx cn66xx; 2525 struct cvmx_gmxx_nxa_adr_s cn68xx; 2526 struct cvmx_gmxx_nxa_adr_s cn68xxp1; 2527 struct cvmx_gmxx_nxa_adr_cn30xx cnf71xx; 2528}; 2529 2530union cvmx_gmxx_pipe_status { 2531 uint64_t u64; 2532 struct cvmx_gmxx_pipe_status_s { 2533#ifdef __BIG_ENDIAN_BITFIELD 2534 uint64_t reserved_20_63:44; 2535 uint64_t ovr:4; 2536 uint64_t reserved_12_15:4; 2537 uint64_t bp:4; 2538 uint64_t reserved_4_7:4; 2539 uint64_t stop:4; 2540#else 2541 uint64_t stop:4; 2542 uint64_t reserved_4_7:4; 2543 uint64_t bp:4; 2544 uint64_t reserved_12_15:4; 2545 uint64_t ovr:4; 2546 uint64_t reserved_20_63:44; 2547#endif 2548 } s; 2549 struct cvmx_gmxx_pipe_status_s cn68xx; 2550 struct cvmx_gmxx_pipe_status_s cn68xxp1; 2551}; 2552 2553union cvmx_gmxx_prtx_cbfc_ctl { 2554 uint64_t u64; 2555 struct cvmx_gmxx_prtx_cbfc_ctl_s { 2556#ifdef __BIG_ENDIAN_BITFIELD 2557 uint64_t phys_en:16; 2558 uint64_t logl_en:16; 2559 uint64_t phys_bp:16; 2560 uint64_t reserved_4_15:12; 2561 uint64_t bck_en:1; 2562 uint64_t drp_en:1; 2563 uint64_t tx_en:1; 2564 uint64_t rx_en:1; 2565#else 2566 uint64_t rx_en:1; 2567 uint64_t tx_en:1; 2568 uint64_t drp_en:1; 2569 uint64_t bck_en:1; 2570 uint64_t reserved_4_15:12; 2571 uint64_t phys_bp:16; 2572 uint64_t logl_en:16; 2573 uint64_t phys_en:16; 2574#endif 2575 } s; 2576 struct cvmx_gmxx_prtx_cbfc_ctl_s cn52xx; 2577 struct cvmx_gmxx_prtx_cbfc_ctl_s cn56xx; 2578 struct cvmx_gmxx_prtx_cbfc_ctl_s cn61xx; 2579 struct cvmx_gmxx_prtx_cbfc_ctl_s cn63xx; 2580 struct cvmx_gmxx_prtx_cbfc_ctl_s cn63xxp1; 2581 struct cvmx_gmxx_prtx_cbfc_ctl_s cn66xx; 2582 struct cvmx_gmxx_prtx_cbfc_ctl_s cn68xx; 2583 struct cvmx_gmxx_prtx_cbfc_ctl_s cn68xxp1; 2584 struct cvmx_gmxx_prtx_cbfc_ctl_s cnf71xx; 2585}; 2586 2587union cvmx_gmxx_prtx_cfg { 2588 uint64_t u64; 2589 struct cvmx_gmxx_prtx_cfg_s { 2590#ifdef __BIG_ENDIAN_BITFIELD 2591 uint64_t reserved_22_63:42; 2592 uint64_t pknd:6; 2593 uint64_t reserved_14_15:2; 2594 uint64_t tx_idle:1; 2595 uint64_t rx_idle:1; 2596 uint64_t reserved_9_11:3; 2597 uint64_t speed_msb:1; 2598 uint64_t reserved_4_7:4; 2599 uint64_t slottime:1; 2600 uint64_t duplex:1; 2601 uint64_t speed:1; 2602 uint64_t en:1; 2603#else 2604 uint64_t en:1; 2605 uint64_t speed:1; 2606 uint64_t duplex:1; 2607 uint64_t slottime:1; 2608 uint64_t reserved_4_7:4; 2609 uint64_t speed_msb:1; 2610 uint64_t reserved_9_11:3; 2611 uint64_t rx_idle:1; 2612 uint64_t tx_idle:1; 2613 uint64_t reserved_14_15:2; 2614 uint64_t pknd:6; 2615 uint64_t reserved_22_63:42; 2616#endif 2617 } s; 2618 struct cvmx_gmxx_prtx_cfg_cn30xx { 2619#ifdef __BIG_ENDIAN_BITFIELD 2620 uint64_t reserved_4_63:60; 2621 uint64_t slottime:1; 2622 uint64_t duplex:1; 2623 uint64_t speed:1; 2624 uint64_t en:1; 2625#else 2626 uint64_t en:1; 2627 uint64_t speed:1; 2628 uint64_t duplex:1; 2629 uint64_t slottime:1; 2630 uint64_t reserved_4_63:60; 2631#endif 2632 } cn30xx; 2633 struct cvmx_gmxx_prtx_cfg_cn30xx cn31xx; 2634 struct cvmx_gmxx_prtx_cfg_cn30xx cn38xx; 2635 struct cvmx_gmxx_prtx_cfg_cn30xx cn38xxp2; 2636 struct cvmx_gmxx_prtx_cfg_cn30xx cn50xx; 2637 struct cvmx_gmxx_prtx_cfg_cn52xx { 2638#ifdef __BIG_ENDIAN_BITFIELD 2639 uint64_t reserved_14_63:50; 2640 uint64_t tx_idle:1; 2641 uint64_t rx_idle:1; 2642 uint64_t reserved_9_11:3; 2643 uint64_t speed_msb:1; 2644 uint64_t reserved_4_7:4; 2645 uint64_t slottime:1; 2646 uint64_t duplex:1; 2647 uint64_t speed:1; 2648 uint64_t en:1; 2649#else 2650 uint64_t en:1; 2651 uint64_t speed:1; 2652 uint64_t duplex:1; 2653 uint64_t slottime:1; 2654 uint64_t reserved_4_7:4; 2655 uint64_t speed_msb:1; 2656 uint64_t reserved_9_11:3; 2657 uint64_t rx_idle:1; 2658 uint64_t tx_idle:1; 2659 uint64_t reserved_14_63:50; 2660#endif 2661 } cn52xx; 2662 struct cvmx_gmxx_prtx_cfg_cn52xx cn52xxp1; 2663 struct cvmx_gmxx_prtx_cfg_cn52xx cn56xx; 2664 struct cvmx_gmxx_prtx_cfg_cn52xx cn56xxp1; 2665 struct cvmx_gmxx_prtx_cfg_cn30xx cn58xx; 2666 struct cvmx_gmxx_prtx_cfg_cn30xx cn58xxp1; 2667 struct cvmx_gmxx_prtx_cfg_cn52xx cn61xx; 2668 struct cvmx_gmxx_prtx_cfg_cn52xx cn63xx; 2669 struct cvmx_gmxx_prtx_cfg_cn52xx cn63xxp1; 2670 struct cvmx_gmxx_prtx_cfg_cn52xx cn66xx; 2671 struct cvmx_gmxx_prtx_cfg_s cn68xx; 2672 struct cvmx_gmxx_prtx_cfg_s cn68xxp1; 2673 struct cvmx_gmxx_prtx_cfg_cn52xx cnf71xx; 2674}; 2675 2676union cvmx_gmxx_rxx_adr_cam0 { 2677 uint64_t u64; 2678 struct cvmx_gmxx_rxx_adr_cam0_s { 2679#ifdef __BIG_ENDIAN_BITFIELD 2680 uint64_t adr:64; 2681#else 2682 uint64_t adr:64; 2683#endif 2684 } s; 2685 struct cvmx_gmxx_rxx_adr_cam0_s cn30xx; 2686 struct cvmx_gmxx_rxx_adr_cam0_s cn31xx; 2687 struct cvmx_gmxx_rxx_adr_cam0_s cn38xx; 2688 struct cvmx_gmxx_rxx_adr_cam0_s cn38xxp2; 2689 struct cvmx_gmxx_rxx_adr_cam0_s cn50xx; 2690 struct cvmx_gmxx_rxx_adr_cam0_s cn52xx; 2691 struct cvmx_gmxx_rxx_adr_cam0_s cn52xxp1; 2692 struct cvmx_gmxx_rxx_adr_cam0_s cn56xx; 2693 struct cvmx_gmxx_rxx_adr_cam0_s cn56xxp1; 2694 struct cvmx_gmxx_rxx_adr_cam0_s cn58xx; 2695 struct cvmx_gmxx_rxx_adr_cam0_s cn58xxp1; 2696 struct cvmx_gmxx_rxx_adr_cam0_s cn61xx; 2697 struct cvmx_gmxx_rxx_adr_cam0_s cn63xx; 2698 struct cvmx_gmxx_rxx_adr_cam0_s cn63xxp1; 2699 struct cvmx_gmxx_rxx_adr_cam0_s cn66xx; 2700 struct cvmx_gmxx_rxx_adr_cam0_s cn68xx; 2701 struct cvmx_gmxx_rxx_adr_cam0_s cn68xxp1; 2702 struct cvmx_gmxx_rxx_adr_cam0_s cnf71xx; 2703}; 2704 2705union cvmx_gmxx_rxx_adr_cam1 { 2706 uint64_t u64; 2707 struct cvmx_gmxx_rxx_adr_cam1_s { 2708#ifdef __BIG_ENDIAN_BITFIELD 2709 uint64_t adr:64; 2710#else 2711 uint64_t adr:64; 2712#endif 2713 } s; 2714 struct cvmx_gmxx_rxx_adr_cam1_s cn30xx; 2715 struct cvmx_gmxx_rxx_adr_cam1_s cn31xx; 2716 struct cvmx_gmxx_rxx_adr_cam1_s cn38xx; 2717 struct cvmx_gmxx_rxx_adr_cam1_s cn38xxp2; 2718 struct cvmx_gmxx_rxx_adr_cam1_s cn50xx; 2719 struct cvmx_gmxx_rxx_adr_cam1_s cn52xx; 2720 struct cvmx_gmxx_rxx_adr_cam1_s cn52xxp1; 2721 struct cvmx_gmxx_rxx_adr_cam1_s cn56xx; 2722 struct cvmx_gmxx_rxx_adr_cam1_s cn56xxp1; 2723 struct cvmx_gmxx_rxx_adr_cam1_s cn58xx; 2724 struct cvmx_gmxx_rxx_adr_cam1_s cn58xxp1; 2725 struct cvmx_gmxx_rxx_adr_cam1_s cn61xx; 2726 struct cvmx_gmxx_rxx_adr_cam1_s cn63xx; 2727 struct cvmx_gmxx_rxx_adr_cam1_s cn63xxp1; 2728 struct cvmx_gmxx_rxx_adr_cam1_s cn66xx; 2729 struct cvmx_gmxx_rxx_adr_cam1_s cn68xx; 2730 struct cvmx_gmxx_rxx_adr_cam1_s cn68xxp1; 2731 struct cvmx_gmxx_rxx_adr_cam1_s cnf71xx; 2732}; 2733 2734union cvmx_gmxx_rxx_adr_cam2 { 2735 uint64_t u64; 2736 struct cvmx_gmxx_rxx_adr_cam2_s { 2737#ifdef __BIG_ENDIAN_BITFIELD 2738 uint64_t adr:64; 2739#else 2740 uint64_t adr:64; 2741#endif 2742 } s; 2743 struct cvmx_gmxx_rxx_adr_cam2_s cn30xx; 2744 struct cvmx_gmxx_rxx_adr_cam2_s cn31xx; 2745 struct cvmx_gmxx_rxx_adr_cam2_s cn38xx; 2746 struct cvmx_gmxx_rxx_adr_cam2_s cn38xxp2; 2747 struct cvmx_gmxx_rxx_adr_cam2_s cn50xx; 2748 struct cvmx_gmxx_rxx_adr_cam2_s cn52xx; 2749 struct cvmx_gmxx_rxx_adr_cam2_s cn52xxp1; 2750 struct cvmx_gmxx_rxx_adr_cam2_s cn56xx; 2751 struct cvmx_gmxx_rxx_adr_cam2_s cn56xxp1; 2752 struct cvmx_gmxx_rxx_adr_cam2_s cn58xx; 2753 struct cvmx_gmxx_rxx_adr_cam2_s cn58xxp1; 2754 struct cvmx_gmxx_rxx_adr_cam2_s cn61xx; 2755 struct cvmx_gmxx_rxx_adr_cam2_s cn63xx; 2756 struct cvmx_gmxx_rxx_adr_cam2_s cn63xxp1; 2757 struct cvmx_gmxx_rxx_adr_cam2_s cn66xx; 2758 struct cvmx_gmxx_rxx_adr_cam2_s cn68xx; 2759 struct cvmx_gmxx_rxx_adr_cam2_s cn68xxp1; 2760 struct cvmx_gmxx_rxx_adr_cam2_s cnf71xx; 2761}; 2762 2763union cvmx_gmxx_rxx_adr_cam3 { 2764 uint64_t u64; 2765 struct cvmx_gmxx_rxx_adr_cam3_s { 2766#ifdef __BIG_ENDIAN_BITFIELD 2767 uint64_t adr:64; 2768#else 2769 uint64_t adr:64; 2770#endif 2771 } s; 2772 struct cvmx_gmxx_rxx_adr_cam3_s cn30xx; 2773 struct cvmx_gmxx_rxx_adr_cam3_s cn31xx; 2774 struct cvmx_gmxx_rxx_adr_cam3_s cn38xx; 2775 struct cvmx_gmxx_rxx_adr_cam3_s cn38xxp2; 2776 struct cvmx_gmxx_rxx_adr_cam3_s cn50xx; 2777 struct cvmx_gmxx_rxx_adr_cam3_s cn52xx; 2778 struct cvmx_gmxx_rxx_adr_cam3_s cn52xxp1; 2779 struct cvmx_gmxx_rxx_adr_cam3_s cn56xx; 2780 struct cvmx_gmxx_rxx_adr_cam3_s cn56xxp1; 2781 struct cvmx_gmxx_rxx_adr_cam3_s cn58xx; 2782 struct cvmx_gmxx_rxx_adr_cam3_s cn58xxp1; 2783 struct cvmx_gmxx_rxx_adr_cam3_s cn61xx; 2784 struct cvmx_gmxx_rxx_adr_cam3_s cn63xx; 2785 struct cvmx_gmxx_rxx_adr_cam3_s cn63xxp1; 2786 struct cvmx_gmxx_rxx_adr_cam3_s cn66xx; 2787 struct cvmx_gmxx_rxx_adr_cam3_s cn68xx; 2788 struct cvmx_gmxx_rxx_adr_cam3_s cn68xxp1; 2789 struct cvmx_gmxx_rxx_adr_cam3_s cnf71xx; 2790}; 2791 2792union cvmx_gmxx_rxx_adr_cam4 { 2793 uint64_t u64; 2794 struct cvmx_gmxx_rxx_adr_cam4_s { 2795#ifdef __BIG_ENDIAN_BITFIELD 2796 uint64_t adr:64; 2797#else 2798 uint64_t adr:64; 2799#endif 2800 } s; 2801 struct cvmx_gmxx_rxx_adr_cam4_s cn30xx; 2802 struct cvmx_gmxx_rxx_adr_cam4_s cn31xx; 2803 struct cvmx_gmxx_rxx_adr_cam4_s cn38xx; 2804 struct cvmx_gmxx_rxx_adr_cam4_s cn38xxp2; 2805 struct cvmx_gmxx_rxx_adr_cam4_s cn50xx; 2806 struct cvmx_gmxx_rxx_adr_cam4_s cn52xx; 2807 struct cvmx_gmxx_rxx_adr_cam4_s cn52xxp1; 2808 struct cvmx_gmxx_rxx_adr_cam4_s cn56xx; 2809 struct cvmx_gmxx_rxx_adr_cam4_s cn56xxp1; 2810 struct cvmx_gmxx_rxx_adr_cam4_s cn58xx; 2811 struct cvmx_gmxx_rxx_adr_cam4_s cn58xxp1; 2812 struct cvmx_gmxx_rxx_adr_cam4_s cn61xx; 2813 struct cvmx_gmxx_rxx_adr_cam4_s cn63xx; 2814 struct cvmx_gmxx_rxx_adr_cam4_s cn63xxp1; 2815 struct cvmx_gmxx_rxx_adr_cam4_s cn66xx; 2816 struct cvmx_gmxx_rxx_adr_cam4_s cn68xx; 2817 struct cvmx_gmxx_rxx_adr_cam4_s cn68xxp1; 2818 struct cvmx_gmxx_rxx_adr_cam4_s cnf71xx; 2819}; 2820 2821union cvmx_gmxx_rxx_adr_cam5 { 2822 uint64_t u64; 2823 struct cvmx_gmxx_rxx_adr_cam5_s { 2824#ifdef __BIG_ENDIAN_BITFIELD 2825 uint64_t adr:64; 2826#else 2827 uint64_t adr:64; 2828#endif 2829 } s; 2830 struct cvmx_gmxx_rxx_adr_cam5_s cn30xx; 2831 struct cvmx_gmxx_rxx_adr_cam5_s cn31xx; 2832 struct cvmx_gmxx_rxx_adr_cam5_s cn38xx; 2833 struct cvmx_gmxx_rxx_adr_cam5_s cn38xxp2; 2834 struct cvmx_gmxx_rxx_adr_cam5_s cn50xx; 2835 struct cvmx_gmxx_rxx_adr_cam5_s cn52xx; 2836 struct cvmx_gmxx_rxx_adr_cam5_s cn52xxp1; 2837 struct cvmx_gmxx_rxx_adr_cam5_s cn56xx; 2838 struct cvmx_gmxx_rxx_adr_cam5_s cn56xxp1; 2839 struct cvmx_gmxx_rxx_adr_cam5_s cn58xx; 2840 struct cvmx_gmxx_rxx_adr_cam5_s cn58xxp1; 2841 struct cvmx_gmxx_rxx_adr_cam5_s cn61xx; 2842 struct cvmx_gmxx_rxx_adr_cam5_s cn63xx; 2843 struct cvmx_gmxx_rxx_adr_cam5_s cn63xxp1; 2844 struct cvmx_gmxx_rxx_adr_cam5_s cn66xx; 2845 struct cvmx_gmxx_rxx_adr_cam5_s cn68xx; 2846 struct cvmx_gmxx_rxx_adr_cam5_s cn68xxp1; 2847 struct cvmx_gmxx_rxx_adr_cam5_s cnf71xx; 2848}; 2849 2850union cvmx_gmxx_rxx_adr_cam_all_en { 2851 uint64_t u64; 2852 struct cvmx_gmxx_rxx_adr_cam_all_en_s { 2853#ifdef __BIG_ENDIAN_BITFIELD 2854 uint64_t reserved_32_63:32; 2855 uint64_t en:32; 2856#else 2857 uint64_t en:32; 2858 uint64_t reserved_32_63:32; 2859#endif 2860 } s; 2861 struct cvmx_gmxx_rxx_adr_cam_all_en_s cn61xx; 2862 struct cvmx_gmxx_rxx_adr_cam_all_en_s cn66xx; 2863 struct cvmx_gmxx_rxx_adr_cam_all_en_s cn68xx; 2864 struct cvmx_gmxx_rxx_adr_cam_all_en_s cnf71xx; 2865}; 2866 2867union cvmx_gmxx_rxx_adr_cam_en { 2868 uint64_t u64; 2869 struct cvmx_gmxx_rxx_adr_cam_en_s { 2870#ifdef __BIG_ENDIAN_BITFIELD 2871 uint64_t reserved_8_63:56; 2872 uint64_t en:8; 2873#else 2874 uint64_t en:8; 2875 uint64_t reserved_8_63:56; 2876#endif 2877 } s; 2878 struct cvmx_gmxx_rxx_adr_cam_en_s cn30xx; 2879 struct cvmx_gmxx_rxx_adr_cam_en_s cn31xx; 2880 struct cvmx_gmxx_rxx_adr_cam_en_s cn38xx; 2881 struct cvmx_gmxx_rxx_adr_cam_en_s cn38xxp2; 2882 struct cvmx_gmxx_rxx_adr_cam_en_s cn50xx; 2883 struct cvmx_gmxx_rxx_adr_cam_en_s cn52xx; 2884 struct cvmx_gmxx_rxx_adr_cam_en_s cn52xxp1; 2885 struct cvmx_gmxx_rxx_adr_cam_en_s cn56xx; 2886 struct cvmx_gmxx_rxx_adr_cam_en_s cn56xxp1; 2887 struct cvmx_gmxx_rxx_adr_cam_en_s cn58xx; 2888 struct cvmx_gmxx_rxx_adr_cam_en_s cn58xxp1; 2889 struct cvmx_gmxx_rxx_adr_cam_en_s cn61xx; 2890 struct cvmx_gmxx_rxx_adr_cam_en_s cn63xx; 2891 struct cvmx_gmxx_rxx_adr_cam_en_s cn63xxp1; 2892 struct cvmx_gmxx_rxx_adr_cam_en_s cn66xx; 2893 struct cvmx_gmxx_rxx_adr_cam_en_s cn68xx; 2894 struct cvmx_gmxx_rxx_adr_cam_en_s cn68xxp1; 2895 struct cvmx_gmxx_rxx_adr_cam_en_s cnf71xx; 2896}; 2897 2898union cvmx_gmxx_rxx_adr_ctl { 2899 uint64_t u64; 2900 struct cvmx_gmxx_rxx_adr_ctl_s { 2901#ifdef __BIG_ENDIAN_BITFIELD 2902 uint64_t reserved_4_63:60; 2903 uint64_t cam_mode:1; 2904 uint64_t mcst:2; 2905 uint64_t bcst:1; 2906#else 2907 uint64_t bcst:1; 2908 uint64_t mcst:2; 2909 uint64_t cam_mode:1; 2910 uint64_t reserved_4_63:60; 2911#endif 2912 } s; 2913 struct cvmx_gmxx_rxx_adr_ctl_s cn30xx; 2914 struct cvmx_gmxx_rxx_adr_ctl_s cn31xx; 2915 struct cvmx_gmxx_rxx_adr_ctl_s cn38xx; 2916 struct cvmx_gmxx_rxx_adr_ctl_s cn38xxp2; 2917 struct cvmx_gmxx_rxx_adr_ctl_s cn50xx; 2918 struct cvmx_gmxx_rxx_adr_ctl_s cn52xx; 2919 struct cvmx_gmxx_rxx_adr_ctl_s cn52xxp1; 2920 struct cvmx_gmxx_rxx_adr_ctl_s cn56xx; 2921 struct cvmx_gmxx_rxx_adr_ctl_s cn56xxp1; 2922 struct cvmx_gmxx_rxx_adr_ctl_s cn58xx; 2923 struct cvmx_gmxx_rxx_adr_ctl_s cn58xxp1; 2924 struct cvmx_gmxx_rxx_adr_ctl_s cn61xx; 2925 struct cvmx_gmxx_rxx_adr_ctl_s cn63xx; 2926 struct cvmx_gmxx_rxx_adr_ctl_s cn63xxp1; 2927 struct cvmx_gmxx_rxx_adr_ctl_s cn66xx; 2928 struct cvmx_gmxx_rxx_adr_ctl_s cn68xx; 2929 struct cvmx_gmxx_rxx_adr_ctl_s cn68xxp1; 2930 struct cvmx_gmxx_rxx_adr_ctl_s cnf71xx; 2931}; 2932 2933union cvmx_gmxx_rxx_decision { 2934 uint64_t u64; 2935 struct cvmx_gmxx_rxx_decision_s { 2936#ifdef __BIG_ENDIAN_BITFIELD 2937 uint64_t reserved_5_63:59; 2938 uint64_t cnt:5; 2939#else 2940 uint64_t cnt:5; 2941 uint64_t reserved_5_63:59; 2942#endif 2943 } s; 2944 struct cvmx_gmxx_rxx_decision_s cn30xx; 2945 struct cvmx_gmxx_rxx_decision_s cn31xx; 2946 struct cvmx_gmxx_rxx_decision_s cn38xx; 2947 struct cvmx_gmxx_rxx_decision_s cn38xxp2; 2948 struct cvmx_gmxx_rxx_decision_s cn50xx; 2949 struct cvmx_gmxx_rxx_decision_s cn52xx; 2950 struct cvmx_gmxx_rxx_decision_s cn52xxp1; 2951 struct cvmx_gmxx_rxx_decision_s cn56xx; 2952 struct cvmx_gmxx_rxx_decision_s cn56xxp1; 2953 struct cvmx_gmxx_rxx_decision_s cn58xx; 2954 struct cvmx_gmxx_rxx_decision_s cn58xxp1; 2955 struct cvmx_gmxx_rxx_decision_s cn61xx; 2956 struct cvmx_gmxx_rxx_decision_s cn63xx; 2957 struct cvmx_gmxx_rxx_decision_s cn63xxp1; 2958 struct cvmx_gmxx_rxx_decision_s cn66xx; 2959 struct cvmx_gmxx_rxx_decision_s cn68xx; 2960 struct cvmx_gmxx_rxx_decision_s cn68xxp1; 2961 struct cvmx_gmxx_rxx_decision_s cnf71xx; 2962}; 2963 2964union cvmx_gmxx_rxx_frm_chk { 2965 uint64_t u64; 2966 struct cvmx_gmxx_rxx_frm_chk_s { 2967#ifdef __BIG_ENDIAN_BITFIELD 2968 uint64_t reserved_10_63:54; 2969 uint64_t niberr:1; 2970 uint64_t skperr:1; 2971 uint64_t rcverr:1; 2972 uint64_t lenerr:1; 2973 uint64_t alnerr:1; 2974 uint64_t fcserr:1; 2975 uint64_t jabber:1; 2976 uint64_t maxerr:1; 2977 uint64_t carext:1; 2978 uint64_t minerr:1; 2979#else 2980 uint64_t minerr:1; 2981 uint64_t carext:1; 2982 uint64_t maxerr:1; 2983 uint64_t jabber:1; 2984 uint64_t fcserr:1; 2985 uint64_t alnerr:1; 2986 uint64_t lenerr:1; 2987 uint64_t rcverr:1; 2988 uint64_t skperr:1; 2989 uint64_t niberr:1; 2990 uint64_t reserved_10_63:54; 2991#endif 2992 } s; 2993 struct cvmx_gmxx_rxx_frm_chk_s cn30xx; 2994 struct cvmx_gmxx_rxx_frm_chk_s cn31xx; 2995 struct cvmx_gmxx_rxx_frm_chk_s cn38xx; 2996 struct cvmx_gmxx_rxx_frm_chk_s cn38xxp2; 2997 struct cvmx_gmxx_rxx_frm_chk_cn50xx { 2998#ifdef __BIG_ENDIAN_BITFIELD 2999 uint64_t reserved_10_63:54; 3000 uint64_t niberr:1; 3001 uint64_t skperr:1; 3002 uint64_t rcverr:1; 3003 uint64_t reserved_6_6:1; 3004 uint64_t alnerr:1; 3005 uint64_t fcserr:1; 3006 uint64_t jabber:1; 3007 uint64_t reserved_2_2:1; 3008 uint64_t carext:1; 3009 uint64_t reserved_0_0:1; 3010#else 3011 uint64_t reserved_0_0:1; 3012 uint64_t carext:1; 3013 uint64_t reserved_2_2:1; 3014 uint64_t jabber:1; 3015 uint64_t fcserr:1; 3016 uint64_t alnerr:1; 3017 uint64_t reserved_6_6:1; 3018 uint64_t rcverr:1; 3019 uint64_t skperr:1; 3020 uint64_t niberr:1; 3021 uint64_t reserved_10_63:54; 3022#endif 3023 } cn50xx; 3024 struct cvmx_gmxx_rxx_frm_chk_cn52xx { 3025#ifdef __BIG_ENDIAN_BITFIELD 3026 uint64_t reserved_9_63:55; 3027 uint64_t skperr:1; 3028 uint64_t rcverr:1; 3029 uint64_t reserved_5_6:2; 3030 uint64_t fcserr:1; 3031 uint64_t jabber:1; 3032 uint64_t reserved_2_2:1; 3033 uint64_t carext:1; 3034 uint64_t reserved_0_0:1; 3035#else 3036 uint64_t reserved_0_0:1; 3037 uint64_t carext:1; 3038 uint64_t reserved_2_2:1; 3039 uint64_t jabber:1; 3040 uint64_t fcserr:1; 3041 uint64_t reserved_5_6:2; 3042 uint64_t rcverr:1; 3043 uint64_t skperr:1; 3044 uint64_t reserved_9_63:55; 3045#endif 3046 } cn52xx; 3047 struct cvmx_gmxx_rxx_frm_chk_cn52xx cn52xxp1; 3048 struct cvmx_gmxx_rxx_frm_chk_cn52xx cn56xx; 3049 struct cvmx_gmxx_rxx_frm_chk_cn52xx cn56xxp1; 3050 struct cvmx_gmxx_rxx_frm_chk_s cn58xx; 3051 struct cvmx_gmxx_rxx_frm_chk_s cn58xxp1; 3052 struct cvmx_gmxx_rxx_frm_chk_cn61xx { 3053#ifdef __BIG_ENDIAN_BITFIELD 3054 uint64_t reserved_9_63:55; 3055 uint64_t skperr:1; 3056 uint64_t rcverr:1; 3057 uint64_t reserved_5_6:2; 3058 uint64_t fcserr:1; 3059 uint64_t jabber:1; 3060 uint64_t reserved_2_2:1; 3061 uint64_t carext:1; 3062 uint64_t minerr:1; 3063#else 3064 uint64_t minerr:1; 3065 uint64_t carext:1; 3066 uint64_t reserved_2_2:1; 3067 uint64_t jabber:1; 3068 uint64_t fcserr:1; 3069 uint64_t reserved_5_6:2; 3070 uint64_t rcverr:1; 3071 uint64_t skperr:1; 3072 uint64_t reserved_9_63:55; 3073#endif 3074 } cn61xx; 3075 struct cvmx_gmxx_rxx_frm_chk_cn61xx cn63xx; 3076 struct cvmx_gmxx_rxx_frm_chk_cn61xx cn63xxp1; 3077 struct cvmx_gmxx_rxx_frm_chk_cn61xx cn66xx; 3078 struct cvmx_gmxx_rxx_frm_chk_cn61xx cn68xx; 3079 struct cvmx_gmxx_rxx_frm_chk_cn61xx cn68xxp1; 3080 struct cvmx_gmxx_rxx_frm_chk_cn61xx cnf71xx; 3081}; 3082 3083union cvmx_gmxx_rxx_frm_ctl { 3084 uint64_t u64; 3085 struct cvmx_gmxx_rxx_frm_ctl_s { 3086#ifdef __BIG_ENDIAN_BITFIELD 3087 uint64_t reserved_13_63:51; 3088 uint64_t ptp_mode:1; 3089 uint64_t reserved_11_11:1; 3090 uint64_t null_dis:1; 3091 uint64_t pre_align:1; 3092 uint64_t pad_len:1; 3093 uint64_t vlan_len:1; 3094 uint64_t pre_free:1; 3095 uint64_t ctl_smac:1; 3096 uint64_t ctl_mcst:1; 3097 uint64_t ctl_bck:1; 3098 uint64_t ctl_drp:1; 3099 uint64_t pre_strp:1; 3100 uint64_t pre_chk:1; 3101#else 3102 uint64_t pre_chk:1; 3103 uint64_t pre_strp:1; 3104 uint64_t ctl_drp:1; 3105 uint64_t ctl_bck:1; 3106 uint64_t ctl_mcst:1; 3107 uint64_t ctl_smac:1; 3108 uint64_t pre_free:1; 3109 uint64_t vlan_len:1; 3110 uint64_t pad_len:1; 3111 uint64_t pre_align:1; 3112 uint64_t null_dis:1; 3113 uint64_t reserved_11_11:1; 3114 uint64_t ptp_mode:1; 3115 uint64_t reserved_13_63:51; 3116#endif 3117 } s; 3118 struct cvmx_gmxx_rxx_frm_ctl_cn30xx { 3119#ifdef __BIG_ENDIAN_BITFIELD 3120 uint64_t reserved_9_63:55; 3121 uint64_t pad_len:1; 3122 uint64_t vlan_len:1; 3123 uint64_t pre_free:1; 3124 uint64_t ctl_smac:1; 3125 uint64_t ctl_mcst:1; 3126 uint64_t ctl_bck:1; 3127 uint64_t ctl_drp:1; 3128 uint64_t pre_strp:1; 3129 uint64_t pre_chk:1; 3130#else 3131 uint64_t pre_chk:1; 3132 uint64_t pre_strp:1; 3133 uint64_t ctl_drp:1; 3134 uint64_t ctl_bck:1; 3135 uint64_t ctl_mcst:1; 3136 uint64_t ctl_smac:1; 3137 uint64_t pre_free:1; 3138 uint64_t vlan_len:1; 3139 uint64_t pad_len:1; 3140 uint64_t reserved_9_63:55; 3141#endif 3142 } cn30xx; 3143 struct cvmx_gmxx_rxx_frm_ctl_cn31xx { 3144#ifdef __BIG_ENDIAN_BITFIELD 3145 uint64_t reserved_8_63:56; 3146 uint64_t vlan_len:1; 3147 uint64_t pre_free:1; 3148 uint64_t ctl_smac:1; 3149 uint64_t ctl_mcst:1; 3150 uint64_t ctl_bck:1; 3151 uint64_t ctl_drp:1; 3152 uint64_t pre_strp:1; 3153 uint64_t pre_chk:1; 3154#else 3155 uint64_t pre_chk:1; 3156 uint64_t pre_strp:1; 3157 uint64_t ctl_drp:1; 3158 uint64_t ctl_bck:1; 3159 uint64_t ctl_mcst:1; 3160 uint64_t ctl_smac:1; 3161 uint64_t pre_free:1; 3162 uint64_t vlan_len:1; 3163 uint64_t reserved_8_63:56; 3164#endif 3165 } cn31xx; 3166 struct cvmx_gmxx_rxx_frm_ctl_cn30xx cn38xx; 3167 struct cvmx_gmxx_rxx_frm_ctl_cn31xx cn38xxp2; 3168 struct cvmx_gmxx_rxx_frm_ctl_cn50xx { 3169#ifdef __BIG_ENDIAN_BITFIELD 3170 uint64_t reserved_11_63:53; 3171 uint64_t null_dis:1; 3172 uint64_t pre_align:1; 3173 uint64_t reserved_7_8:2; 3174 uint64_t pre_free:1; 3175 uint64_t ctl_smac:1; 3176 uint64_t ctl_mcst:1; 3177 uint64_t ctl_bck:1; 3178 uint64_t ctl_drp:1; 3179 uint64_t pre_strp:1; 3180 uint64_t pre_chk:1; 3181#else 3182 uint64_t pre_chk:1; 3183 uint64_t pre_strp:1; 3184 uint64_t ctl_drp:1; 3185 uint64_t ctl_bck:1; 3186 uint64_t ctl_mcst:1; 3187 uint64_t ctl_smac:1; 3188 uint64_t pre_free:1; 3189 uint64_t reserved_7_8:2; 3190 uint64_t pre_align:1; 3191 uint64_t null_dis:1; 3192 uint64_t reserved_11_63:53; 3193#endif 3194 } cn50xx; 3195 struct cvmx_gmxx_rxx_frm_ctl_cn50xx cn52xx; 3196 struct cvmx_gmxx_rxx_frm_ctl_cn50xx cn52xxp1; 3197 struct cvmx_gmxx_rxx_frm_ctl_cn50xx cn56xx; 3198 struct cvmx_gmxx_rxx_frm_ctl_cn56xxp1 { 3199#ifdef __BIG_ENDIAN_BITFIELD 3200 uint64_t reserved_10_63:54; 3201 uint64_t pre_align:1; 3202 uint64_t reserved_7_8:2; 3203 uint64_t pre_free:1; 3204 uint64_t ctl_smac:1; 3205 uint64_t ctl_mcst:1; 3206 uint64_t ctl_bck:1; 3207 uint64_t ctl_drp:1; 3208 uint64_t pre_strp:1; 3209 uint64_t pre_chk:1; 3210#else 3211 uint64_t pre_chk:1; 3212 uint64_t pre_strp:1; 3213 uint64_t ctl_drp:1; 3214 uint64_t ctl_bck:1; 3215 uint64_t ctl_mcst:1; 3216 uint64_t ctl_smac:1; 3217 uint64_t pre_free:1; 3218 uint64_t reserved_7_8:2; 3219 uint64_t pre_align:1; 3220 uint64_t reserved_10_63:54; 3221#endif 3222 } cn56xxp1; 3223 struct cvmx_gmxx_rxx_frm_ctl_cn58xx { 3224#ifdef __BIG_ENDIAN_BITFIELD 3225 uint64_t reserved_11_63:53; 3226 uint64_t null_dis:1; 3227 uint64_t pre_align:1; 3228 uint64_t pad_len:1; 3229 uint64_t vlan_len:1; 3230 uint64_t pre_free:1; 3231 uint64_t ctl_smac:1; 3232 uint64_t ctl_mcst:1; 3233 uint64_t ctl_bck:1; 3234 uint64_t ctl_drp:1; 3235 uint64_t pre_strp:1; 3236 uint64_t pre_chk:1; 3237#else 3238 uint64_t pre_chk:1; 3239 uint64_t pre_strp:1; 3240 uint64_t ctl_drp:1; 3241 uint64_t ctl_bck:1; 3242 uint64_t ctl_mcst:1; 3243 uint64_t ctl_smac:1; 3244 uint64_t pre_free:1; 3245 uint64_t vlan_len:1; 3246 uint64_t pad_len:1; 3247 uint64_t pre_align:1; 3248 uint64_t null_dis:1; 3249 uint64_t reserved_11_63:53; 3250#endif 3251 } cn58xx; 3252 struct cvmx_gmxx_rxx_frm_ctl_cn30xx cn58xxp1; 3253 struct cvmx_gmxx_rxx_frm_ctl_cn61xx { 3254#ifdef __BIG_ENDIAN_BITFIELD 3255 uint64_t reserved_13_63:51; 3256 uint64_t ptp_mode:1; 3257 uint64_t reserved_11_11:1; 3258 uint64_t null_dis:1; 3259 uint64_t pre_align:1; 3260 uint64_t reserved_7_8:2; 3261 uint64_t pre_free:1; 3262 uint64_t ctl_smac:1; 3263 uint64_t ctl_mcst:1; 3264 uint64_t ctl_bck:1; 3265 uint64_t ctl_drp:1; 3266 uint64_t pre_strp:1; 3267 uint64_t pre_chk:1; 3268#else 3269 uint64_t pre_chk:1; 3270 uint64_t pre_strp:1; 3271 uint64_t ctl_drp:1; 3272 uint64_t ctl_bck:1; 3273 uint64_t ctl_mcst:1; 3274 uint64_t ctl_smac:1; 3275 uint64_t pre_free:1; 3276 uint64_t reserved_7_8:2; 3277 uint64_t pre_align:1; 3278 uint64_t null_dis:1; 3279 uint64_t reserved_11_11:1; 3280 uint64_t ptp_mode:1; 3281 uint64_t reserved_13_63:51; 3282#endif 3283 } cn61xx; 3284 struct cvmx_gmxx_rxx_frm_ctl_cn61xx cn63xx; 3285 struct cvmx_gmxx_rxx_frm_ctl_cn61xx cn63xxp1; 3286 struct cvmx_gmxx_rxx_frm_ctl_cn61xx cn66xx; 3287 struct cvmx_gmxx_rxx_frm_ctl_cn61xx cn68xx; 3288 struct cvmx_gmxx_rxx_frm_ctl_cn61xx cn68xxp1; 3289 struct cvmx_gmxx_rxx_frm_ctl_cn61xx cnf71xx; 3290}; 3291 3292union cvmx_gmxx_rxx_frm_max { 3293 uint64_t u64; 3294 struct cvmx_gmxx_rxx_frm_max_s { 3295#ifdef __BIG_ENDIAN_BITFIELD 3296 uint64_t reserved_16_63:48; 3297 uint64_t len:16; 3298#else 3299 uint64_t len:16; 3300 uint64_t reserved_16_63:48; 3301#endif 3302 } s; 3303 struct cvmx_gmxx_rxx_frm_max_s cn30xx; 3304 struct cvmx_gmxx_rxx_frm_max_s cn31xx; 3305 struct cvmx_gmxx_rxx_frm_max_s cn38xx; 3306 struct cvmx_gmxx_rxx_frm_max_s cn38xxp2; 3307 struct cvmx_gmxx_rxx_frm_max_s cn58xx; 3308 struct cvmx_gmxx_rxx_frm_max_s cn58xxp1; 3309}; 3310 3311union cvmx_gmxx_rxx_frm_min { 3312 uint64_t u64; 3313 struct cvmx_gmxx_rxx_frm_min_s { 3314#ifdef __BIG_ENDIAN_BITFIELD 3315 uint64_t reserved_16_63:48; 3316 uint64_t len:16; 3317#else 3318 uint64_t len:16; 3319 uint64_t reserved_16_63:48; 3320#endif 3321 } s; 3322 struct cvmx_gmxx_rxx_frm_min_s cn30xx; 3323 struct cvmx_gmxx_rxx_frm_min_s cn31xx; 3324 struct cvmx_gmxx_rxx_frm_min_s cn38xx; 3325 struct cvmx_gmxx_rxx_frm_min_s cn38xxp2; 3326 struct cvmx_gmxx_rxx_frm_min_s cn58xx; 3327 struct cvmx_gmxx_rxx_frm_min_s cn58xxp1; 3328}; 3329 3330union cvmx_gmxx_rxx_ifg { 3331 uint64_t u64; 3332 struct cvmx_gmxx_rxx_ifg_s { 3333#ifdef __BIG_ENDIAN_BITFIELD 3334 uint64_t reserved_4_63:60; 3335 uint64_t ifg:4; 3336#else 3337 uint64_t ifg:4; 3338 uint64_t reserved_4_63:60; 3339#endif 3340 } s; 3341 struct cvmx_gmxx_rxx_ifg_s cn30xx; 3342 struct cvmx_gmxx_rxx_ifg_s cn31xx; 3343 struct cvmx_gmxx_rxx_ifg_s cn38xx; 3344 struct cvmx_gmxx_rxx_ifg_s cn38xxp2; 3345 struct cvmx_gmxx_rxx_ifg_s cn50xx; 3346 struct cvmx_gmxx_rxx_ifg_s cn52xx; 3347 struct cvmx_gmxx_rxx_ifg_s cn52xxp1; 3348 struct cvmx_gmxx_rxx_ifg_s cn56xx; 3349 struct cvmx_gmxx_rxx_ifg_s cn56xxp1; 3350 struct cvmx_gmxx_rxx_ifg_s cn58xx; 3351 struct cvmx_gmxx_rxx_ifg_s cn58xxp1; 3352 struct cvmx_gmxx_rxx_ifg_s cn61xx; 3353 struct cvmx_gmxx_rxx_ifg_s cn63xx; 3354 struct cvmx_gmxx_rxx_ifg_s cn63xxp1; 3355 struct cvmx_gmxx_rxx_ifg_s cn66xx; 3356 struct cvmx_gmxx_rxx_ifg_s cn68xx; 3357 struct cvmx_gmxx_rxx_ifg_s cn68xxp1; 3358 struct cvmx_gmxx_rxx_ifg_s cnf71xx; 3359}; 3360 3361union cvmx_gmxx_rxx_int_en { 3362 uint64_t u64; 3363 struct cvmx_gmxx_rxx_int_en_s { 3364#ifdef __BIG_ENDIAN_BITFIELD 3365 uint64_t reserved_29_63:35; 3366 uint64_t hg2cc:1; 3367 uint64_t hg2fld:1; 3368 uint64_t undat:1; 3369 uint64_t uneop:1; 3370 uint64_t unsop:1; 3371 uint64_t bad_term:1; 3372 uint64_t bad_seq:1; 3373 uint64_t rem_fault:1; 3374 uint64_t loc_fault:1; 3375 uint64_t pause_drp:1; 3376 uint64_t phy_dupx:1; 3377 uint64_t phy_spd:1; 3378 uint64_t phy_link:1; 3379 uint64_t ifgerr:1; 3380 uint64_t coldet:1; 3381 uint64_t falerr:1; 3382 uint64_t rsverr:1; 3383 uint64_t pcterr:1; 3384 uint64_t ovrerr:1; 3385 uint64_t niberr:1; 3386 uint64_t skperr:1; 3387 uint64_t rcverr:1; 3388 uint64_t lenerr:1; 3389 uint64_t alnerr:1; 3390 uint64_t fcserr:1; 3391 uint64_t jabber:1; 3392 uint64_t maxerr:1; 3393 uint64_t carext:1; 3394 uint64_t minerr:1; 3395#else 3396 uint64_t minerr:1; 3397 uint64_t carext:1; 3398 uint64_t maxerr:1; 3399 uint64_t jabber:1; 3400 uint64_t fcserr:1; 3401 uint64_t alnerr:1; 3402 uint64_t lenerr:1; 3403 uint64_t rcverr:1; 3404 uint64_t skperr:1; 3405 uint64_t niberr:1; 3406 uint64_t ovrerr:1; 3407 uint64_t pcterr:1; 3408 uint64_t rsverr:1; 3409 uint64_t falerr:1; 3410 uint64_t coldet:1; 3411 uint64_t ifgerr:1; 3412 uint64_t phy_link:1; 3413 uint64_t phy_spd:1; 3414 uint64_t phy_dupx:1; 3415 uint64_t pause_drp:1; 3416 uint64_t loc_fault:1; 3417 uint64_t rem_fault:1; 3418 uint64_t bad_seq:1; 3419 uint64_t bad_term:1; 3420 uint64_t unsop:1; 3421 uint64_t uneop:1; 3422 uint64_t undat:1; 3423 uint64_t hg2fld:1; 3424 uint64_t hg2cc:1; 3425 uint64_t reserved_29_63:35; 3426#endif 3427 } s; 3428 struct cvmx_gmxx_rxx_int_en_cn30xx { 3429#ifdef __BIG_ENDIAN_BITFIELD 3430 uint64_t reserved_19_63:45; 3431 uint64_t phy_dupx:1; 3432 uint64_t phy_spd:1; 3433 uint64_t phy_link:1; 3434 uint64_t ifgerr:1; 3435 uint64_t coldet:1; 3436 uint64_t falerr:1; 3437 uint64_t rsverr:1; 3438 uint64_t pcterr:1; 3439 uint64_t ovrerr:1; 3440 uint64_t niberr:1; 3441 uint64_t skperr:1; 3442 uint64_t rcverr:1; 3443 uint64_t lenerr:1; 3444 uint64_t alnerr:1; 3445 uint64_t fcserr:1; 3446 uint64_t jabber:1; 3447 uint64_t maxerr:1; 3448 uint64_t carext:1; 3449 uint64_t minerr:1; 3450#else 3451 uint64_t minerr:1; 3452 uint64_t carext:1; 3453 uint64_t maxerr:1; 3454 uint64_t jabber:1; 3455 uint64_t fcserr:1; 3456 uint64_t alnerr:1; 3457 uint64_t lenerr:1; 3458 uint64_t rcverr:1; 3459 uint64_t skperr:1; 3460 uint64_t niberr:1; 3461 uint64_t ovrerr:1; 3462 uint64_t pcterr:1; 3463 uint64_t rsverr:1; 3464 uint64_t falerr:1; 3465 uint64_t coldet:1; 3466 uint64_t ifgerr:1; 3467 uint64_t phy_link:1; 3468 uint64_t phy_spd:1; 3469 uint64_t phy_dupx:1; 3470 uint64_t reserved_19_63:45; 3471#endif 3472 } cn30xx; 3473 struct cvmx_gmxx_rxx_int_en_cn30xx cn31xx; 3474 struct cvmx_gmxx_rxx_int_en_cn30xx cn38xx; 3475 struct cvmx_gmxx_rxx_int_en_cn30xx cn38xxp2; 3476 struct cvmx_gmxx_rxx_int_en_cn50xx { 3477#ifdef __BIG_ENDIAN_BITFIELD 3478 uint64_t reserved_20_63:44; 3479 uint64_t pause_drp:1; 3480 uint64_t phy_dupx:1; 3481 uint64_t phy_spd:1; 3482 uint64_t phy_link:1; 3483 uint64_t ifgerr:1; 3484 uint64_t coldet:1; 3485 uint64_t falerr:1; 3486 uint64_t rsverr:1; 3487 uint64_t pcterr:1; 3488 uint64_t ovrerr:1; 3489 uint64_t niberr:1; 3490 uint64_t skperr:1; 3491 uint64_t rcverr:1; 3492 uint64_t reserved_6_6:1; 3493 uint64_t alnerr:1; 3494 uint64_t fcserr:1; 3495 uint64_t jabber:1; 3496 uint64_t reserved_2_2:1; 3497 uint64_t carext:1; 3498 uint64_t reserved_0_0:1; 3499#else 3500 uint64_t reserved_0_0:1; 3501 uint64_t carext:1; 3502 uint64_t reserved_2_2:1; 3503 uint64_t jabber:1; 3504 uint64_t fcserr:1; 3505 uint64_t alnerr:1; 3506 uint64_t reserved_6_6:1; 3507 uint64_t rcverr:1; 3508 uint64_t skperr:1; 3509 uint64_t niberr:1; 3510 uint64_t ovrerr:1; 3511 uint64_t pcterr:1; 3512 uint64_t rsverr:1; 3513 uint64_t falerr:1; 3514 uint64_t coldet:1; 3515 uint64_t ifgerr:1; 3516 uint64_t phy_link:1; 3517 uint64_t phy_spd:1; 3518 uint64_t phy_dupx:1; 3519 uint64_t pause_drp:1; 3520 uint64_t reserved_20_63:44; 3521#endif 3522 } cn50xx; 3523 struct cvmx_gmxx_rxx_int_en_cn52xx { 3524#ifdef __BIG_ENDIAN_BITFIELD 3525 uint64_t reserved_29_63:35; 3526 uint64_t hg2cc:1; 3527 uint64_t hg2fld:1; 3528 uint64_t undat:1; 3529 uint64_t uneop:1; 3530 uint64_t unsop:1; 3531 uint64_t bad_term:1; 3532 uint64_t bad_seq:1; 3533 uint64_t rem_fault:1; 3534 uint64_t loc_fault:1; 3535 uint64_t pause_drp:1; 3536 uint64_t reserved_16_18:3; 3537 uint64_t ifgerr:1; 3538 uint64_t coldet:1; 3539 uint64_t falerr:1; 3540 uint64_t rsverr:1; 3541 uint64_t pcterr:1; 3542 uint64_t ovrerr:1; 3543 uint64_t reserved_9_9:1; 3544 uint64_t skperr:1; 3545 uint64_t rcverr:1; 3546 uint64_t reserved_5_6:2; 3547 uint64_t fcserr:1; 3548 uint64_t jabber:1; 3549 uint64_t reserved_2_2:1; 3550 uint64_t carext:1; 3551 uint64_t reserved_0_0:1; 3552#else 3553 uint64_t reserved_0_0:1; 3554 uint64_t carext:1; 3555 uint64_t reserved_2_2:1; 3556 uint64_t jabber:1; 3557 uint64_t fcserr:1; 3558 uint64_t reserved_5_6:2; 3559 uint64_t rcverr:1; 3560 uint64_t skperr:1; 3561 uint64_t reserved_9_9:1; 3562 uint64_t ovrerr:1; 3563 uint64_t pcterr:1; 3564 uint64_t rsverr:1; 3565 uint64_t falerr:1; 3566 uint64_t coldet:1; 3567 uint64_t ifgerr:1; 3568 uint64_t reserved_16_18:3; 3569 uint64_t pause_drp:1; 3570 uint64_t loc_fault:1; 3571 uint64_t rem_fault:1; 3572 uint64_t bad_seq:1; 3573 uint64_t bad_term:1; 3574 uint64_t unsop:1; 3575 uint64_t uneop:1; 3576 uint64_t undat:1; 3577 uint64_t hg2fld:1; 3578 uint64_t hg2cc:1; 3579 uint64_t reserved_29_63:35; 3580#endif 3581 } cn52xx; 3582 struct cvmx_gmxx_rxx_int_en_cn52xx cn52xxp1; 3583 struct cvmx_gmxx_rxx_int_en_cn52xx cn56xx; 3584 struct cvmx_gmxx_rxx_int_en_cn56xxp1 { 3585#ifdef __BIG_ENDIAN_BITFIELD 3586 uint64_t reserved_27_63:37; 3587 uint64_t undat:1; 3588 uint64_t uneop:1; 3589 uint64_t unsop:1; 3590 uint64_t bad_term:1; 3591 uint64_t bad_seq:1; 3592 uint64_t rem_fault:1; 3593 uint64_t loc_fault:1; 3594 uint64_t pause_drp:1; 3595 uint64_t reserved_16_18:3; 3596 uint64_t ifgerr:1; 3597 uint64_t coldet:1; 3598 uint64_t falerr:1; 3599 uint64_t rsverr:1; 3600 uint64_t pcterr:1; 3601 uint64_t ovrerr:1; 3602 uint64_t reserved_9_9:1; 3603 uint64_t skperr:1; 3604 uint64_t rcverr:1; 3605 uint64_t reserved_5_6:2; 3606 uint64_t fcserr:1; 3607 uint64_t jabber:1; 3608 uint64_t reserved_2_2:1; 3609 uint64_t carext:1; 3610 uint64_t reserved_0_0:1; 3611#else 3612 uint64_t reserved_0_0:1; 3613 uint64_t carext:1; 3614 uint64_t reserved_2_2:1; 3615 uint64_t jabber:1; 3616 uint64_t fcserr:1; 3617 uint64_t reserved_5_6:2; 3618 uint64_t rcverr:1; 3619 uint64_t skperr:1; 3620 uint64_t reserved_9_9:1; 3621 uint64_t ovrerr:1; 3622 uint64_t pcterr:1; 3623 uint64_t rsverr:1; 3624 uint64_t falerr:1; 3625 uint64_t coldet:1; 3626 uint64_t ifgerr:1; 3627 uint64_t reserved_16_18:3; 3628 uint64_t pause_drp:1; 3629 uint64_t loc_fault:1; 3630 uint64_t rem_fault:1; 3631 uint64_t bad_seq:1; 3632 uint64_t bad_term:1; 3633 uint64_t unsop:1; 3634 uint64_t uneop:1; 3635 uint64_t undat:1; 3636 uint64_t reserved_27_63:37; 3637#endif 3638 } cn56xxp1; 3639 struct cvmx_gmxx_rxx_int_en_cn58xx { 3640#ifdef __BIG_ENDIAN_BITFIELD 3641 uint64_t reserved_20_63:44; 3642 uint64_t pause_drp:1; 3643 uint64_t phy_dupx:1; 3644 uint64_t phy_spd:1; 3645 uint64_t phy_link:1; 3646 uint64_t ifgerr:1; 3647 uint64_t coldet:1; 3648 uint64_t falerr:1; 3649 uint64_t rsverr:1; 3650 uint64_t pcterr:1; 3651 uint64_t ovrerr:1; 3652 uint64_t niberr:1; 3653 uint64_t skperr:1; 3654 uint64_t rcverr:1; 3655 uint64_t lenerr:1; 3656 uint64_t alnerr:1; 3657 uint64_t fcserr:1; 3658 uint64_t jabber:1; 3659 uint64_t maxerr:1; 3660 uint64_t carext:1; 3661 uint64_t minerr:1; 3662#else 3663 uint64_t minerr:1; 3664 uint64_t carext:1; 3665 uint64_t maxerr:1; 3666 uint64_t jabber:1; 3667 uint64_t fcserr:1; 3668 uint64_t alnerr:1; 3669 uint64_t lenerr:1; 3670 uint64_t rcverr:1; 3671 uint64_t skperr:1; 3672 uint64_t niberr:1; 3673 uint64_t ovrerr:1; 3674 uint64_t pcterr:1; 3675 uint64_t rsverr:1; 3676 uint64_t falerr:1; 3677 uint64_t coldet:1; 3678 uint64_t ifgerr:1; 3679 uint64_t phy_link:1; 3680 uint64_t phy_spd:1; 3681 uint64_t phy_dupx:1; 3682 uint64_t pause_drp:1; 3683 uint64_t reserved_20_63:44; 3684#endif 3685 } cn58xx; 3686 struct cvmx_gmxx_rxx_int_en_cn58xx cn58xxp1; 3687 struct cvmx_gmxx_rxx_int_en_cn61xx { 3688#ifdef __BIG_ENDIAN_BITFIELD 3689 uint64_t reserved_29_63:35; 3690 uint64_t hg2cc:1; 3691 uint64_t hg2fld:1; 3692 uint64_t undat:1; 3693 uint64_t uneop:1; 3694 uint64_t unsop:1; 3695 uint64_t bad_term:1; 3696 uint64_t bad_seq:1; 3697 uint64_t rem_fault:1; 3698 uint64_t loc_fault:1; 3699 uint64_t pause_drp:1; 3700 uint64_t reserved_16_18:3; 3701 uint64_t ifgerr:1; 3702 uint64_t coldet:1; 3703 uint64_t falerr:1; 3704 uint64_t rsverr:1; 3705 uint64_t pcterr:1; 3706 uint64_t ovrerr:1; 3707 uint64_t reserved_9_9:1; 3708 uint64_t skperr:1; 3709 uint64_t rcverr:1; 3710 uint64_t reserved_5_6:2; 3711 uint64_t fcserr:1; 3712 uint64_t jabber:1; 3713 uint64_t reserved_2_2:1; 3714 uint64_t carext:1; 3715 uint64_t minerr:1; 3716#else 3717 uint64_t minerr:1; 3718 uint64_t carext:1; 3719 uint64_t reserved_2_2:1; 3720 uint64_t jabber:1; 3721 uint64_t fcserr:1; 3722 uint64_t reserved_5_6:2; 3723 uint64_t rcverr:1; 3724 uint64_t skperr:1; 3725 uint64_t reserved_9_9:1; 3726 uint64_t ovrerr:1; 3727 uint64_t pcterr:1; 3728 uint64_t rsverr:1; 3729 uint64_t falerr:1; 3730 uint64_t coldet:1; 3731 uint64_t ifgerr:1; 3732 uint64_t reserved_16_18:3; 3733 uint64_t pause_drp:1; 3734 uint64_t loc_fault:1; 3735 uint64_t rem_fault:1; 3736 uint64_t bad_seq:1; 3737 uint64_t bad_term:1; 3738 uint64_t unsop:1; 3739 uint64_t uneop:1; 3740 uint64_t undat:1; 3741 uint64_t hg2fld:1; 3742 uint64_t hg2cc:1; 3743 uint64_t reserved_29_63:35; 3744#endif 3745 } cn61xx; 3746 struct cvmx_gmxx_rxx_int_en_cn61xx cn63xx; 3747 struct cvmx_gmxx_rxx_int_en_cn61xx cn63xxp1; 3748 struct cvmx_gmxx_rxx_int_en_cn61xx cn66xx; 3749 struct cvmx_gmxx_rxx_int_en_cn61xx cn68xx; 3750 struct cvmx_gmxx_rxx_int_en_cn61xx cn68xxp1; 3751 struct cvmx_gmxx_rxx_int_en_cn61xx cnf71xx; 3752}; 3753 3754union cvmx_gmxx_rxx_int_reg { 3755 uint64_t u64; 3756 struct cvmx_gmxx_rxx_int_reg_s { 3757#ifdef __BIG_ENDIAN_BITFIELD 3758 uint64_t reserved_29_63:35; 3759 uint64_t hg2cc:1; 3760 uint64_t hg2fld:1; 3761 uint64_t undat:1; 3762 uint64_t uneop:1; 3763 uint64_t unsop:1; 3764 uint64_t bad_term:1; 3765 uint64_t bad_seq:1; 3766 uint64_t rem_fault:1; 3767 uint64_t loc_fault:1; 3768 uint64_t pause_drp:1; 3769 uint64_t phy_dupx:1; 3770 uint64_t phy_spd:1; 3771 uint64_t phy_link:1; 3772 uint64_t ifgerr:1; 3773 uint64_t coldet:1; 3774 uint64_t falerr:1; 3775 uint64_t rsverr:1; 3776 uint64_t pcterr:1; 3777 uint64_t ovrerr:1; 3778 uint64_t niberr:1; 3779 uint64_t skperr:1; 3780 uint64_t rcverr:1; 3781 uint64_t lenerr:1; 3782 uint64_t alnerr:1; 3783 uint64_t fcserr:1; 3784 uint64_t jabber:1; 3785 uint64_t maxerr:1; 3786 uint64_t carext:1; 3787 uint64_t minerr:1; 3788#else 3789 uint64_t minerr:1; 3790 uint64_t carext:1; 3791 uint64_t maxerr:1; 3792 uint64_t jabber:1; 3793 uint64_t fcserr:1; 3794 uint64_t alnerr:1; 3795 uint64_t lenerr:1; 3796 uint64_t rcverr:1; 3797 uint64_t skperr:1; 3798 uint64_t niberr:1; 3799 uint64_t ovrerr:1; 3800 uint64_t pcterr:1; 3801 uint64_t rsverr:1; 3802 uint64_t falerr:1; 3803 uint64_t coldet:1; 3804 uint64_t ifgerr:1; 3805 uint64_t phy_link:1; 3806 uint64_t phy_spd:1; 3807 uint64_t phy_dupx:1; 3808 uint64_t pause_drp:1; 3809 uint64_t loc_fault:1; 3810 uint64_t rem_fault:1; 3811 uint64_t bad_seq:1; 3812 uint64_t bad_term:1; 3813 uint64_t unsop:1; 3814 uint64_t uneop:1; 3815 uint64_t undat:1; 3816 uint64_t hg2fld:1; 3817 uint64_t hg2cc:1; 3818 uint64_t reserved_29_63:35; 3819#endif 3820 } s; 3821 struct cvmx_gmxx_rxx_int_reg_cn30xx { 3822#ifdef __BIG_ENDIAN_BITFIELD 3823 uint64_t reserved_19_63:45; 3824 uint64_t phy_dupx:1; 3825 uint64_t phy_spd:1; 3826 uint64_t phy_link:1; 3827 uint64_t ifgerr:1; 3828 uint64_t coldet:1; 3829 uint64_t falerr:1; 3830 uint64_t rsverr:1; 3831 uint64_t pcterr:1; 3832 uint64_t ovrerr:1; 3833 uint64_t niberr:1; 3834 uint64_t skperr:1; 3835 uint64_t rcverr:1; 3836 uint64_t lenerr:1; 3837 uint64_t alnerr:1; 3838 uint64_t fcserr:1; 3839 uint64_t jabber:1; 3840 uint64_t maxerr:1; 3841 uint64_t carext:1; 3842 uint64_t minerr:1; 3843#else 3844 uint64_t minerr:1; 3845 uint64_t carext:1; 3846 uint64_t maxerr:1; 3847 uint64_t jabber:1; 3848 uint64_t fcserr:1; 3849 uint64_t alnerr:1; 3850 uint64_t lenerr:1; 3851 uint64_t rcverr:1; 3852 uint64_t skperr:1; 3853 uint64_t niberr:1; 3854 uint64_t ovrerr:1; 3855 uint64_t pcterr:1; 3856 uint64_t rsverr:1; 3857 uint64_t falerr:1; 3858 uint64_t coldet:1; 3859 uint64_t ifgerr:1; 3860 uint64_t phy_link:1; 3861 uint64_t phy_spd:1; 3862 uint64_t phy_dupx:1; 3863 uint64_t reserved_19_63:45; 3864#endif 3865 } cn30xx; 3866 struct cvmx_gmxx_rxx_int_reg_cn30xx cn31xx; 3867 struct cvmx_gmxx_rxx_int_reg_cn30xx cn38xx; 3868 struct cvmx_gmxx_rxx_int_reg_cn30xx cn38xxp2; 3869 struct cvmx_gmxx_rxx_int_reg_cn50xx { 3870#ifdef __BIG_ENDIAN_BITFIELD 3871 uint64_t reserved_20_63:44; 3872 uint64_t pause_drp:1; 3873 uint64_t phy_dupx:1; 3874 uint64_t phy_spd:1; 3875 uint64_t phy_link:1; 3876 uint64_t ifgerr:1; 3877 uint64_t coldet:1; 3878 uint64_t falerr:1; 3879 uint64_t rsverr:1; 3880 uint64_t pcterr:1; 3881 uint64_t ovrerr:1; 3882 uint64_t niberr:1; 3883 uint64_t skperr:1; 3884 uint64_t rcverr:1; 3885 uint64_t reserved_6_6:1; 3886 uint64_t alnerr:1; 3887 uint64_t fcserr:1; 3888 uint64_t jabber:1; 3889 uint64_t reserved_2_2:1; 3890 uint64_t carext:1; 3891 uint64_t reserved_0_0:1; 3892#else 3893 uint64_t reserved_0_0:1; 3894 uint64_t carext:1; 3895 uint64_t reserved_2_2:1; 3896 uint64_t jabber:1; 3897 uint64_t fcserr:1; 3898 uint64_t alnerr:1; 3899 uint64_t reserved_6_6:1; 3900 uint64_t rcverr:1; 3901 uint64_t skperr:1; 3902 uint64_t niberr:1; 3903 uint64_t ovrerr:1; 3904 uint64_t pcterr:1; 3905 uint64_t rsverr:1; 3906 uint64_t falerr:1; 3907 uint64_t coldet:1; 3908 uint64_t ifgerr:1; 3909 uint64_t phy_link:1; 3910 uint64_t phy_spd:1; 3911 uint64_t phy_dupx:1; 3912 uint64_t pause_drp:1; 3913 uint64_t reserved_20_63:44; 3914#endif 3915 } cn50xx; 3916 struct cvmx_gmxx_rxx_int_reg_cn52xx { 3917#ifdef __BIG_ENDIAN_BITFIELD 3918 uint64_t reserved_29_63:35; 3919 uint64_t hg2cc:1; 3920 uint64_t hg2fld:1; 3921 uint64_t undat:1; 3922 uint64_t uneop:1; 3923 uint64_t unsop:1; 3924 uint64_t bad_term:1; 3925 uint64_t bad_seq:1; 3926 uint64_t rem_fault:1; 3927 uint64_t loc_fault:1; 3928 uint64_t pause_drp:1; 3929 uint64_t reserved_16_18:3; 3930 uint64_t ifgerr:1; 3931 uint64_t coldet:1; 3932 uint64_t falerr:1; 3933 uint64_t rsverr:1; 3934 uint64_t pcterr:1; 3935 uint64_t ovrerr:1; 3936 uint64_t reserved_9_9:1; 3937 uint64_t skperr:1; 3938 uint64_t rcverr:1; 3939 uint64_t reserved_5_6:2; 3940 uint64_t fcserr:1; 3941 uint64_t jabber:1; 3942 uint64_t reserved_2_2:1; 3943 uint64_t carext:1; 3944 uint64_t reserved_0_0:1; 3945#else 3946 uint64_t reserved_0_0:1; 3947 uint64_t carext:1; 3948 uint64_t reserved_2_2:1; 3949 uint64_t jabber:1; 3950 uint64_t fcserr:1; 3951 uint64_t reserved_5_6:2; 3952 uint64_t rcverr:1; 3953 uint64_t skperr:1; 3954 uint64_t reserved_9_9:1; 3955 uint64_t ovrerr:1; 3956 uint64_t pcterr:1; 3957 uint64_t rsverr:1; 3958 uint64_t falerr:1; 3959 uint64_t coldet:1; 3960 uint64_t ifgerr:1; 3961 uint64_t reserved_16_18:3; 3962 uint64_t pause_drp:1; 3963 uint64_t loc_fault:1; 3964 uint64_t rem_fault:1; 3965 uint64_t bad_seq:1; 3966 uint64_t bad_term:1; 3967 uint64_t unsop:1; 3968 uint64_t uneop:1; 3969 uint64_t undat:1; 3970 uint64_t hg2fld:1; 3971 uint64_t hg2cc:1; 3972 uint64_t reserved_29_63:35; 3973#endif 3974 } cn52xx; 3975 struct cvmx_gmxx_rxx_int_reg_cn52xx cn52xxp1; 3976 struct cvmx_gmxx_rxx_int_reg_cn52xx cn56xx; 3977 struct cvmx_gmxx_rxx_int_reg_cn56xxp1 { 3978#ifdef __BIG_ENDIAN_BITFIELD 3979 uint64_t reserved_27_63:37; 3980 uint64_t undat:1; 3981 uint64_t uneop:1; 3982 uint64_t unsop:1; 3983 uint64_t bad_term:1; 3984 uint64_t bad_seq:1; 3985 uint64_t rem_fault:1; 3986 uint64_t loc_fault:1; 3987 uint64_t pause_drp:1; 3988 uint64_t reserved_16_18:3; 3989 uint64_t ifgerr:1; 3990 uint64_t coldet:1; 3991 uint64_t falerr:1; 3992 uint64_t rsverr:1; 3993 uint64_t pcterr:1; 3994 uint64_t ovrerr:1; 3995 uint64_t reserved_9_9:1; 3996 uint64_t skperr:1; 3997 uint64_t rcverr:1; 3998 uint64_t reserved_5_6:2; 3999 uint64_t fcserr:1; 4000 uint64_t jabber:1; 4001 uint64_t reserved_2_2:1; 4002 uint64_t carext:1; 4003 uint64_t reserved_0_0:1; 4004#else 4005 uint64_t reserved_0_0:1; 4006 uint64_t carext:1; 4007 uint64_t reserved_2_2:1; 4008 uint64_t jabber:1; 4009 uint64_t fcserr:1; 4010 uint64_t reserved_5_6:2; 4011 uint64_t rcverr:1; 4012 uint64_t skperr:1; 4013 uint64_t reserved_9_9:1; 4014 uint64_t ovrerr:1; 4015 uint64_t pcterr:1; 4016 uint64_t rsverr:1; 4017 uint64_t falerr:1; 4018 uint64_t coldet:1; 4019 uint64_t ifgerr:1; 4020 uint64_t reserved_16_18:3; 4021 uint64_t pause_drp:1; 4022 uint64_t loc_fault:1; 4023 uint64_t rem_fault:1; 4024 uint64_t bad_seq:1; 4025 uint64_t bad_term:1; 4026 uint64_t unsop:1; 4027 uint64_t uneop:1; 4028 uint64_t undat:1; 4029 uint64_t reserved_27_63:37; 4030#endif 4031 } cn56xxp1; 4032 struct cvmx_gmxx_rxx_int_reg_cn58xx { 4033#ifdef __BIG_ENDIAN_BITFIELD 4034 uint64_t reserved_20_63:44; 4035 uint64_t pause_drp:1; 4036 uint64_t phy_dupx:1; 4037 uint64_t phy_spd:1; 4038 uint64_t phy_link:1; 4039 uint64_t ifgerr:1; 4040 uint64_t coldet:1; 4041 uint64_t falerr:1; 4042 uint64_t rsverr:1; 4043 uint64_t pcterr:1; 4044 uint64_t ovrerr:1; 4045 uint64_t niberr:1; 4046 uint64_t skperr:1; 4047 uint64_t rcverr:1; 4048 uint64_t lenerr:1; 4049 uint64_t alnerr:1; 4050 uint64_t fcserr:1; 4051 uint64_t jabber:1; 4052 uint64_t maxerr:1; 4053 uint64_t carext:1; 4054 uint64_t minerr:1; 4055#else 4056 uint64_t minerr:1; 4057 uint64_t carext:1; 4058 uint64_t maxerr:1; 4059 uint64_t jabber:1; 4060 uint64_t fcserr:1; 4061 uint64_t alnerr:1; 4062 uint64_t lenerr:1; 4063 uint64_t rcverr:1; 4064 uint64_t skperr:1; 4065 uint64_t niberr:1; 4066 uint64_t ovrerr:1; 4067 uint64_t pcterr:1; 4068 uint64_t rsverr:1; 4069 uint64_t falerr:1; 4070 uint64_t coldet:1; 4071 uint64_t ifgerr:1; 4072 uint64_t phy_link:1; 4073 uint64_t phy_spd:1; 4074 uint64_t phy_dupx:1; 4075 uint64_t pause_drp:1; 4076 uint64_t reserved_20_63:44; 4077#endif 4078 } cn58xx; 4079 struct cvmx_gmxx_rxx_int_reg_cn58xx cn58xxp1; 4080 struct cvmx_gmxx_rxx_int_reg_cn61xx { 4081#ifdef __BIG_ENDIAN_BITFIELD 4082 uint64_t reserved_29_63:35; 4083 uint64_t hg2cc:1; 4084 uint64_t hg2fld:1; 4085 uint64_t undat:1; 4086 uint64_t uneop:1; 4087 uint64_t unsop:1; 4088 uint64_t bad_term:1; 4089 uint64_t bad_seq:1; 4090 uint64_t rem_fault:1; 4091 uint64_t loc_fault:1; 4092 uint64_t pause_drp:1; 4093 uint64_t reserved_16_18:3; 4094 uint64_t ifgerr:1; 4095 uint64_t coldet:1; 4096 uint64_t falerr:1; 4097 uint64_t rsverr:1; 4098 uint64_t pcterr:1; 4099 uint64_t ovrerr:1; 4100 uint64_t reserved_9_9:1; 4101 uint64_t skperr:1; 4102 uint64_t rcverr:1; 4103 uint64_t reserved_5_6:2; 4104 uint64_t fcserr:1; 4105 uint64_t jabber:1; 4106 uint64_t reserved_2_2:1; 4107 uint64_t carext:1; 4108 uint64_t minerr:1; 4109#else 4110 uint64_t minerr:1; 4111 uint64_t carext:1; 4112 uint64_t reserved_2_2:1; 4113 uint64_t jabber:1; 4114 uint64_t fcserr:1; 4115 uint64_t reserved_5_6:2; 4116 uint64_t rcverr:1; 4117 uint64_t skperr:1; 4118 uint64_t reserved_9_9:1; 4119 uint64_t ovrerr:1; 4120 uint64_t pcterr:1; 4121 uint64_t rsverr:1; 4122 uint64_t falerr:1; 4123 uint64_t coldet:1; 4124 uint64_t ifgerr:1; 4125 uint64_t reserved_16_18:3; 4126 uint64_t pause_drp:1; 4127 uint64_t loc_fault:1; 4128 uint64_t rem_fault:1; 4129 uint64_t bad_seq:1; 4130 uint64_t bad_term:1; 4131 uint64_t unsop:1; 4132 uint64_t uneop:1; 4133 uint64_t undat:1; 4134 uint64_t hg2fld:1; 4135 uint64_t hg2cc:1; 4136 uint64_t reserved_29_63:35; 4137#endif 4138 } cn61xx; 4139 struct cvmx_gmxx_rxx_int_reg_cn61xx cn63xx; 4140 struct cvmx_gmxx_rxx_int_reg_cn61xx cn63xxp1; 4141 struct cvmx_gmxx_rxx_int_reg_cn61xx cn66xx; 4142 struct cvmx_gmxx_rxx_int_reg_cn61xx cn68xx; 4143 struct cvmx_gmxx_rxx_int_reg_cn61xx cn68xxp1; 4144 struct cvmx_gmxx_rxx_int_reg_cn61xx cnf71xx; 4145}; 4146 4147union cvmx_gmxx_rxx_jabber { 4148 uint64_t u64; 4149 struct cvmx_gmxx_rxx_jabber_s { 4150#ifdef __BIG_ENDIAN_BITFIELD 4151 uint64_t reserved_16_63:48; 4152 uint64_t cnt:16; 4153#else 4154 uint64_t cnt:16; 4155 uint64_t reserved_16_63:48; 4156#endif 4157 } s; 4158 struct cvmx_gmxx_rxx_jabber_s cn30xx; 4159 struct cvmx_gmxx_rxx_jabber_s cn31xx; 4160 struct cvmx_gmxx_rxx_jabber_s cn38xx; 4161 struct cvmx_gmxx_rxx_jabber_s cn38xxp2; 4162 struct cvmx_gmxx_rxx_jabber_s cn50xx; 4163 struct cvmx_gmxx_rxx_jabber_s cn52xx; 4164 struct cvmx_gmxx_rxx_jabber_s cn52xxp1; 4165 struct cvmx_gmxx_rxx_jabber_s cn56xx; 4166 struct cvmx_gmxx_rxx_jabber_s cn56xxp1; 4167 struct cvmx_gmxx_rxx_jabber_s cn58xx; 4168 struct cvmx_gmxx_rxx_jabber_s cn58xxp1; 4169 struct cvmx_gmxx_rxx_jabber_s cn61xx; 4170 struct cvmx_gmxx_rxx_jabber_s cn63xx; 4171 struct cvmx_gmxx_rxx_jabber_s cn63xxp1; 4172 struct cvmx_gmxx_rxx_jabber_s cn66xx; 4173 struct cvmx_gmxx_rxx_jabber_s cn68xx; 4174 struct cvmx_gmxx_rxx_jabber_s cn68xxp1; 4175 struct cvmx_gmxx_rxx_jabber_s cnf71xx; 4176}; 4177 4178union cvmx_gmxx_rxx_pause_drop_time { 4179 uint64_t u64; 4180 struct cvmx_gmxx_rxx_pause_drop_time_s { 4181#ifdef __BIG_ENDIAN_BITFIELD 4182 uint64_t reserved_16_63:48; 4183 uint64_t status:16; 4184#else 4185 uint64_t status:16; 4186 uint64_t reserved_16_63:48; 4187#endif 4188 } s; 4189 struct cvmx_gmxx_rxx_pause_drop_time_s cn50xx; 4190 struct cvmx_gmxx_rxx_pause_drop_time_s cn52xx; 4191 struct cvmx_gmxx_rxx_pause_drop_time_s cn52xxp1; 4192 struct cvmx_gmxx_rxx_pause_drop_time_s cn56xx; 4193 struct cvmx_gmxx_rxx_pause_drop_time_s cn56xxp1; 4194 struct cvmx_gmxx_rxx_pause_drop_time_s cn58xx; 4195 struct cvmx_gmxx_rxx_pause_drop_time_s cn58xxp1; 4196 struct cvmx_gmxx_rxx_pause_drop_time_s cn61xx; 4197 struct cvmx_gmxx_rxx_pause_drop_time_s cn63xx; 4198 struct cvmx_gmxx_rxx_pause_drop_time_s cn63xxp1; 4199 struct cvmx_gmxx_rxx_pause_drop_time_s cn66xx; 4200 struct cvmx_gmxx_rxx_pause_drop_time_s cn68xx; 4201 struct cvmx_gmxx_rxx_pause_drop_time_s cn68xxp1; 4202 struct cvmx_gmxx_rxx_pause_drop_time_s cnf71xx; 4203}; 4204 4205union cvmx_gmxx_rxx_rx_inbnd { 4206 uint64_t u64; 4207 struct cvmx_gmxx_rxx_rx_inbnd_s { 4208#ifdef __BIG_ENDIAN_BITFIELD 4209 uint64_t reserved_4_63:60; 4210 uint64_t duplex:1; 4211 uint64_t speed:2; 4212 uint64_t status:1; 4213#else 4214 uint64_t status:1; 4215 uint64_t speed:2; 4216 uint64_t duplex:1; 4217 uint64_t reserved_4_63:60; 4218#endif 4219 } s; 4220 struct cvmx_gmxx_rxx_rx_inbnd_s cn30xx; 4221 struct cvmx_gmxx_rxx_rx_inbnd_s cn31xx; 4222 struct cvmx_gmxx_rxx_rx_inbnd_s cn38xx; 4223 struct cvmx_gmxx_rxx_rx_inbnd_s cn38xxp2; 4224 struct cvmx_gmxx_rxx_rx_inbnd_s cn50xx; 4225 struct cvmx_gmxx_rxx_rx_inbnd_s cn58xx; 4226 struct cvmx_gmxx_rxx_rx_inbnd_s cn58xxp1; 4227}; 4228 4229union cvmx_gmxx_rxx_stats_ctl { 4230 uint64_t u64; 4231 struct cvmx_gmxx_rxx_stats_ctl_s { 4232#ifdef __BIG_ENDIAN_BITFIELD 4233 uint64_t reserved_1_63:63; 4234 uint64_t rd_clr:1; 4235#else 4236 uint64_t rd_clr:1; 4237 uint64_t reserved_1_63:63; 4238#endif 4239 } s; 4240 struct cvmx_gmxx_rxx_stats_ctl_s cn30xx; 4241 struct cvmx_gmxx_rxx_stats_ctl_s cn31xx; 4242 struct cvmx_gmxx_rxx_stats_ctl_s cn38xx; 4243 struct cvmx_gmxx_rxx_stats_ctl_s cn38xxp2; 4244 struct cvmx_gmxx_rxx_stats_ctl_s cn50xx; 4245 struct cvmx_gmxx_rxx_stats_ctl_s cn52xx; 4246 struct cvmx_gmxx_rxx_stats_ctl_s cn52xxp1; 4247 struct cvmx_gmxx_rxx_stats_ctl_s cn56xx; 4248 struct cvmx_gmxx_rxx_stats_ctl_s cn56xxp1; 4249 struct cvmx_gmxx_rxx_stats_ctl_s cn58xx; 4250 struct cvmx_gmxx_rxx_stats_ctl_s cn58xxp1; 4251 struct cvmx_gmxx_rxx_stats_ctl_s cn61xx; 4252 struct cvmx_gmxx_rxx_stats_ctl_s cn63xx; 4253 struct cvmx_gmxx_rxx_stats_ctl_s cn63xxp1; 4254 struct cvmx_gmxx_rxx_stats_ctl_s cn66xx; 4255 struct cvmx_gmxx_rxx_stats_ctl_s cn68xx; 4256 struct cvmx_gmxx_rxx_stats_ctl_s cn68xxp1; 4257 struct cvmx_gmxx_rxx_stats_ctl_s cnf71xx; 4258}; 4259 4260union cvmx_gmxx_rxx_stats_octs { 4261 uint64_t u64; 4262 struct cvmx_gmxx_rxx_stats_octs_s { 4263#ifdef __BIG_ENDIAN_BITFIELD 4264 uint64_t reserved_48_63:16; 4265 uint64_t cnt:48; 4266#else 4267 uint64_t cnt:48; 4268 uint64_t reserved_48_63:16; 4269#endif 4270 } s; 4271 struct cvmx_gmxx_rxx_stats_octs_s cn30xx; 4272 struct cvmx_gmxx_rxx_stats_octs_s cn31xx; 4273 struct cvmx_gmxx_rxx_stats_octs_s cn38xx; 4274 struct cvmx_gmxx_rxx_stats_octs_s cn38xxp2; 4275 struct cvmx_gmxx_rxx_stats_octs_s cn50xx; 4276 struct cvmx_gmxx_rxx_stats_octs_s cn52xx; 4277 struct cvmx_gmxx_rxx_stats_octs_s cn52xxp1; 4278 struct cvmx_gmxx_rxx_stats_octs_s cn56xx; 4279 struct cvmx_gmxx_rxx_stats_octs_s cn56xxp1; 4280 struct cvmx_gmxx_rxx_stats_octs_s cn58xx; 4281 struct cvmx_gmxx_rxx_stats_octs_s cn58xxp1; 4282 struct cvmx_gmxx_rxx_stats_octs_s cn61xx; 4283 struct cvmx_gmxx_rxx_stats_octs_s cn63xx; 4284 struct cvmx_gmxx_rxx_stats_octs_s cn63xxp1; 4285 struct cvmx_gmxx_rxx_stats_octs_s cn66xx; 4286 struct cvmx_gmxx_rxx_stats_octs_s cn68xx; 4287 struct cvmx_gmxx_rxx_stats_octs_s cn68xxp1; 4288 struct cvmx_gmxx_rxx_stats_octs_s cnf71xx; 4289}; 4290 4291union cvmx_gmxx_rxx_stats_octs_ctl { 4292 uint64_t u64; 4293 struct cvmx_gmxx_rxx_stats_octs_ctl_s { 4294#ifdef __BIG_ENDIAN_BITFIELD 4295 uint64_t reserved_48_63:16; 4296 uint64_t cnt:48; 4297#else 4298 uint64_t cnt:48; 4299 uint64_t reserved_48_63:16; 4300#endif 4301 } s; 4302 struct cvmx_gmxx_rxx_stats_octs_ctl_s cn30xx; 4303 struct cvmx_gmxx_rxx_stats_octs_ctl_s cn31xx; 4304 struct cvmx_gmxx_rxx_stats_octs_ctl_s cn38xx; 4305 struct cvmx_gmxx_rxx_stats_octs_ctl_s cn38xxp2; 4306 struct cvmx_gmxx_rxx_stats_octs_ctl_s cn50xx; 4307 struct cvmx_gmxx_rxx_stats_octs_ctl_s cn52xx; 4308 struct cvmx_gmxx_rxx_stats_octs_ctl_s cn52xxp1; 4309 struct cvmx_gmxx_rxx_stats_octs_ctl_s cn56xx; 4310 struct cvmx_gmxx_rxx_stats_octs_ctl_s cn56xxp1; 4311 struct cvmx_gmxx_rxx_stats_octs_ctl_s cn58xx; 4312 struct cvmx_gmxx_rxx_stats_octs_ctl_s cn58xxp1; 4313 struct cvmx_gmxx_rxx_stats_octs_ctl_s cn61xx; 4314 struct cvmx_gmxx_rxx_stats_octs_ctl_s cn63xx; 4315 struct cvmx_gmxx_rxx_stats_octs_ctl_s cn63xxp1; 4316 struct cvmx_gmxx_rxx_stats_octs_ctl_s cn66xx; 4317 struct cvmx_gmxx_rxx_stats_octs_ctl_s cn68xx; 4318 struct cvmx_gmxx_rxx_stats_octs_ctl_s cn68xxp1; 4319 struct cvmx_gmxx_rxx_stats_octs_ctl_s cnf71xx; 4320}; 4321 4322union cvmx_gmxx_rxx_stats_octs_dmac { 4323 uint64_t u64; 4324 struct cvmx_gmxx_rxx_stats_octs_dmac_s { 4325#ifdef __BIG_ENDIAN_BITFIELD 4326 uint64_t reserved_48_63:16; 4327 uint64_t cnt:48; 4328#else 4329 uint64_t cnt:48; 4330 uint64_t reserved_48_63:16; 4331#endif 4332 } s; 4333 struct cvmx_gmxx_rxx_stats_octs_dmac_s cn30xx; 4334 struct cvmx_gmxx_rxx_stats_octs_dmac_s cn31xx; 4335 struct cvmx_gmxx_rxx_stats_octs_dmac_s cn38xx; 4336 struct cvmx_gmxx_rxx_stats_octs_dmac_s cn38xxp2; 4337 struct cvmx_gmxx_rxx_stats_octs_dmac_s cn50xx; 4338 struct cvmx_gmxx_rxx_stats_octs_dmac_s cn52xx; 4339 struct cvmx_gmxx_rxx_stats_octs_dmac_s cn52xxp1; 4340 struct cvmx_gmxx_rxx_stats_octs_dmac_s cn56xx; 4341 struct cvmx_gmxx_rxx_stats_octs_dmac_s cn56xxp1; 4342 struct cvmx_gmxx_rxx_stats_octs_dmac_s cn58xx; 4343 struct cvmx_gmxx_rxx_stats_octs_dmac_s cn58xxp1; 4344 struct cvmx_gmxx_rxx_stats_octs_dmac_s cn61xx; 4345 struct cvmx_gmxx_rxx_stats_octs_dmac_s cn63xx; 4346 struct cvmx_gmxx_rxx_stats_octs_dmac_s cn63xxp1; 4347 struct cvmx_gmxx_rxx_stats_octs_dmac_s cn66xx; 4348 struct cvmx_gmxx_rxx_stats_octs_dmac_s cn68xx; 4349 struct cvmx_gmxx_rxx_stats_octs_dmac_s cn68xxp1; 4350 struct cvmx_gmxx_rxx_stats_octs_dmac_s cnf71xx; 4351}; 4352 4353union cvmx_gmxx_rxx_stats_octs_drp { 4354 uint64_t u64; 4355 struct cvmx_gmxx_rxx_stats_octs_drp_s { 4356#ifdef __BIG_ENDIAN_BITFIELD 4357 uint64_t reserved_48_63:16; 4358 uint64_t cnt:48; 4359#else 4360 uint64_t cnt:48; 4361 uint64_t reserved_48_63:16; 4362#endif 4363 } s; 4364 struct cvmx_gmxx_rxx_stats_octs_drp_s cn30xx; 4365 struct cvmx_gmxx_rxx_stats_octs_drp_s cn31xx; 4366 struct cvmx_gmxx_rxx_stats_octs_drp_s cn38xx; 4367 struct cvmx_gmxx_rxx_stats_octs_drp_s cn38xxp2; 4368 struct cvmx_gmxx_rxx_stats_octs_drp_s cn50xx; 4369 struct cvmx_gmxx_rxx_stats_octs_drp_s cn52xx; 4370 struct cvmx_gmxx_rxx_stats_octs_drp_s cn52xxp1; 4371 struct cvmx_gmxx_rxx_stats_octs_drp_s cn56xx; 4372 struct cvmx_gmxx_rxx_stats_octs_drp_s cn56xxp1; 4373 struct cvmx_gmxx_rxx_stats_octs_drp_s cn58xx; 4374 struct cvmx_gmxx_rxx_stats_octs_drp_s cn58xxp1; 4375 struct cvmx_gmxx_rxx_stats_octs_drp_s cn61xx; 4376 struct cvmx_gmxx_rxx_stats_octs_drp_s cn63xx; 4377 struct cvmx_gmxx_rxx_stats_octs_drp_s cn63xxp1; 4378 struct cvmx_gmxx_rxx_stats_octs_drp_s cn66xx; 4379 struct cvmx_gmxx_rxx_stats_octs_drp_s cn68xx; 4380 struct cvmx_gmxx_rxx_stats_octs_drp_s cn68xxp1; 4381 struct cvmx_gmxx_rxx_stats_octs_drp_s cnf71xx; 4382}; 4383 4384union cvmx_gmxx_rxx_stats_pkts { 4385 uint64_t u64; 4386 struct cvmx_gmxx_rxx_stats_pkts_s { 4387#ifdef __BIG_ENDIAN_BITFIELD 4388 uint64_t reserved_32_63:32; 4389 uint64_t cnt:32; 4390#else 4391 uint64_t cnt:32; 4392 uint64_t reserved_32_63:32; 4393#endif 4394 } s; 4395 struct cvmx_gmxx_rxx_stats_pkts_s cn30xx; 4396 struct cvmx_gmxx_rxx_stats_pkts_s cn31xx; 4397 struct cvmx_gmxx_rxx_stats_pkts_s cn38xx; 4398 struct cvmx_gmxx_rxx_stats_pkts_s cn38xxp2; 4399 struct cvmx_gmxx_rxx_stats_pkts_s cn50xx; 4400 struct cvmx_gmxx_rxx_stats_pkts_s cn52xx; 4401 struct cvmx_gmxx_rxx_stats_pkts_s cn52xxp1; 4402 struct cvmx_gmxx_rxx_stats_pkts_s cn56xx; 4403 struct cvmx_gmxx_rxx_stats_pkts_s cn56xxp1; 4404 struct cvmx_gmxx_rxx_stats_pkts_s cn58xx; 4405 struct cvmx_gmxx_rxx_stats_pkts_s cn58xxp1; 4406 struct cvmx_gmxx_rxx_stats_pkts_s cn61xx; 4407 struct cvmx_gmxx_rxx_stats_pkts_s cn63xx; 4408 struct cvmx_gmxx_rxx_stats_pkts_s cn63xxp1; 4409 struct cvmx_gmxx_rxx_stats_pkts_s cn66xx; 4410 struct cvmx_gmxx_rxx_stats_pkts_s cn68xx; 4411 struct cvmx_gmxx_rxx_stats_pkts_s cn68xxp1; 4412 struct cvmx_gmxx_rxx_stats_pkts_s cnf71xx; 4413}; 4414 4415union cvmx_gmxx_rxx_stats_pkts_bad { 4416 uint64_t u64; 4417 struct cvmx_gmxx_rxx_stats_pkts_bad_s { 4418#ifdef __BIG_ENDIAN_BITFIELD 4419 uint64_t reserved_32_63:32; 4420 uint64_t cnt:32; 4421#else 4422 uint64_t cnt:32; 4423 uint64_t reserved_32_63:32; 4424#endif 4425 } s; 4426 struct cvmx_gmxx_rxx_stats_pkts_bad_s cn30xx; 4427 struct cvmx_gmxx_rxx_stats_pkts_bad_s cn31xx; 4428 struct cvmx_gmxx_rxx_stats_pkts_bad_s cn38xx; 4429 struct cvmx_gmxx_rxx_stats_pkts_bad_s cn38xxp2; 4430 struct cvmx_gmxx_rxx_stats_pkts_bad_s cn50xx; 4431 struct cvmx_gmxx_rxx_stats_pkts_bad_s cn52xx; 4432 struct cvmx_gmxx_rxx_stats_pkts_bad_s cn52xxp1; 4433 struct cvmx_gmxx_rxx_stats_pkts_bad_s cn56xx; 4434 struct cvmx_gmxx_rxx_stats_pkts_bad_s cn56xxp1; 4435 struct cvmx_gmxx_rxx_stats_pkts_bad_s cn58xx; 4436 struct cvmx_gmxx_rxx_stats_pkts_bad_s cn58xxp1; 4437 struct cvmx_gmxx_rxx_stats_pkts_bad_s cn61xx; 4438 struct cvmx_gmxx_rxx_stats_pkts_bad_s cn63xx; 4439 struct cvmx_gmxx_rxx_stats_pkts_bad_s cn63xxp1; 4440 struct cvmx_gmxx_rxx_stats_pkts_bad_s cn66xx; 4441 struct cvmx_gmxx_rxx_stats_pkts_bad_s cn68xx; 4442 struct cvmx_gmxx_rxx_stats_pkts_bad_s cn68xxp1; 4443 struct cvmx_gmxx_rxx_stats_pkts_bad_s cnf71xx; 4444}; 4445 4446union cvmx_gmxx_rxx_stats_pkts_ctl { 4447 uint64_t u64; 4448 struct cvmx_gmxx_rxx_stats_pkts_ctl_s { 4449#ifdef __BIG_ENDIAN_BITFIELD 4450 uint64_t reserved_32_63:32; 4451 uint64_t cnt:32; 4452#else 4453 uint64_t cnt:32; 4454 uint64_t reserved_32_63:32; 4455#endif 4456 } s; 4457 struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn30xx; 4458 struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn31xx; 4459 struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn38xx; 4460 struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn38xxp2; 4461 struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn50xx; 4462 struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn52xx; 4463 struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn52xxp1; 4464 struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn56xx; 4465 struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn56xxp1; 4466 struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn58xx; 4467 struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn58xxp1; 4468 struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn61xx; 4469 struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn63xx; 4470 struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn63xxp1; 4471 struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn66xx; 4472 struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn68xx; 4473 struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn68xxp1; 4474 struct cvmx_gmxx_rxx_stats_pkts_ctl_s cnf71xx; 4475}; 4476 4477union cvmx_gmxx_rxx_stats_pkts_dmac { 4478 uint64_t u64; 4479 struct cvmx_gmxx_rxx_stats_pkts_dmac_s { 4480#ifdef __BIG_ENDIAN_BITFIELD 4481 uint64_t reserved_32_63:32; 4482 uint64_t cnt:32; 4483#else 4484 uint64_t cnt:32; 4485 uint64_t reserved_32_63:32; 4486#endif 4487 } s; 4488 struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn30xx; 4489 struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn31xx; 4490 struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn38xx; 4491 struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn38xxp2; 4492 struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn50xx; 4493 struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn52xx; 4494 struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn52xxp1; 4495 struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn56xx; 4496 struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn56xxp1; 4497 struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn58xx; 4498 struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn58xxp1; 4499 struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn61xx; 4500 struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn63xx; 4501 struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn63xxp1; 4502 struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn66xx; 4503 struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn68xx; 4504 struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn68xxp1; 4505 struct cvmx_gmxx_rxx_stats_pkts_dmac_s cnf71xx; 4506}; 4507 4508union cvmx_gmxx_rxx_stats_pkts_drp { 4509 uint64_t u64; 4510 struct cvmx_gmxx_rxx_stats_pkts_drp_s { 4511#ifdef __BIG_ENDIAN_BITFIELD 4512 uint64_t reserved_32_63:32; 4513 uint64_t cnt:32; 4514#else 4515 uint64_t cnt:32; 4516 uint64_t reserved_32_63:32; 4517#endif 4518 } s; 4519 struct cvmx_gmxx_rxx_stats_pkts_drp_s cn30xx; 4520 struct cvmx_gmxx_rxx_stats_pkts_drp_s cn31xx; 4521 struct cvmx_gmxx_rxx_stats_pkts_drp_s cn38xx; 4522 struct cvmx_gmxx_rxx_stats_pkts_drp_s cn38xxp2; 4523 struct cvmx_gmxx_rxx_stats_pkts_drp_s cn50xx; 4524 struct cvmx_gmxx_rxx_stats_pkts_drp_s cn52xx; 4525 struct cvmx_gmxx_rxx_stats_pkts_drp_s cn52xxp1; 4526 struct cvmx_gmxx_rxx_stats_pkts_drp_s cn56xx; 4527 struct cvmx_gmxx_rxx_stats_pkts_drp_s cn56xxp1; 4528 struct cvmx_gmxx_rxx_stats_pkts_drp_s cn58xx; 4529 struct cvmx_gmxx_rxx_stats_pkts_drp_s cn58xxp1; 4530 struct cvmx_gmxx_rxx_stats_pkts_drp_s cn61xx; 4531 struct cvmx_gmxx_rxx_stats_pkts_drp_s cn63xx; 4532 struct cvmx_gmxx_rxx_stats_pkts_drp_s cn63xxp1; 4533 struct cvmx_gmxx_rxx_stats_pkts_drp_s cn66xx; 4534 struct cvmx_gmxx_rxx_stats_pkts_drp_s cn68xx; 4535 struct cvmx_gmxx_rxx_stats_pkts_drp_s cn68xxp1; 4536 struct cvmx_gmxx_rxx_stats_pkts_drp_s cnf71xx; 4537}; 4538 4539union cvmx_gmxx_rxx_udd_skp { 4540 uint64_t u64; 4541 struct cvmx_gmxx_rxx_udd_skp_s { 4542#ifdef __BIG_ENDIAN_BITFIELD 4543 uint64_t reserved_9_63:55; 4544 uint64_t fcssel:1; 4545 uint64_t reserved_7_7:1; 4546 uint64_t len:7; 4547#else 4548 uint64_t len:7; 4549 uint64_t reserved_7_7:1; 4550 uint64_t fcssel:1; 4551 uint64_t reserved_9_63:55; 4552#endif 4553 } s; 4554 struct cvmx_gmxx_rxx_udd_skp_s cn30xx; 4555 struct cvmx_gmxx_rxx_udd_skp_s cn31xx; 4556 struct cvmx_gmxx_rxx_udd_skp_s cn38xx; 4557 struct cvmx_gmxx_rxx_udd_skp_s cn38xxp2; 4558 struct cvmx_gmxx_rxx_udd_skp_s cn50xx; 4559 struct cvmx_gmxx_rxx_udd_skp_s cn52xx; 4560 struct cvmx_gmxx_rxx_udd_skp_s cn52xxp1; 4561 struct cvmx_gmxx_rxx_udd_skp_s cn56xx; 4562 struct cvmx_gmxx_rxx_udd_skp_s cn56xxp1; 4563 struct cvmx_gmxx_rxx_udd_skp_s cn58xx; 4564 struct cvmx_gmxx_rxx_udd_skp_s cn58xxp1; 4565 struct cvmx_gmxx_rxx_udd_skp_s cn61xx; 4566 struct cvmx_gmxx_rxx_udd_skp_s cn63xx; 4567 struct cvmx_gmxx_rxx_udd_skp_s cn63xxp1; 4568 struct cvmx_gmxx_rxx_udd_skp_s cn66xx; 4569 struct cvmx_gmxx_rxx_udd_skp_s cn68xx; 4570 struct cvmx_gmxx_rxx_udd_skp_s cn68xxp1; 4571 struct cvmx_gmxx_rxx_udd_skp_s cnf71xx; 4572}; 4573 4574union cvmx_gmxx_rx_bp_dropx { 4575 uint64_t u64; 4576 struct cvmx_gmxx_rx_bp_dropx_s { 4577#ifdef __BIG_ENDIAN_BITFIELD 4578 uint64_t reserved_6_63:58; 4579 uint64_t mark:6; 4580#else 4581 uint64_t mark:6; 4582 uint64_t reserved_6_63:58; 4583#endif 4584 } s; 4585 struct cvmx_gmxx_rx_bp_dropx_s cn30xx; 4586 struct cvmx_gmxx_rx_bp_dropx_s cn31xx; 4587 struct cvmx_gmxx_rx_bp_dropx_s cn38xx; 4588 struct cvmx_gmxx_rx_bp_dropx_s cn38xxp2; 4589 struct cvmx_gmxx_rx_bp_dropx_s cn50xx; 4590 struct cvmx_gmxx_rx_bp_dropx_s cn52xx; 4591 struct cvmx_gmxx_rx_bp_dropx_s cn52xxp1; 4592 struct cvmx_gmxx_rx_bp_dropx_s cn56xx; 4593 struct cvmx_gmxx_rx_bp_dropx_s cn56xxp1; 4594 struct cvmx_gmxx_rx_bp_dropx_s cn58xx; 4595 struct cvmx_gmxx_rx_bp_dropx_s cn58xxp1; 4596 struct cvmx_gmxx_rx_bp_dropx_s cn61xx; 4597 struct cvmx_gmxx_rx_bp_dropx_s cn63xx; 4598 struct cvmx_gmxx_rx_bp_dropx_s cn63xxp1; 4599 struct cvmx_gmxx_rx_bp_dropx_s cn66xx; 4600 struct cvmx_gmxx_rx_bp_dropx_s cn68xx; 4601 struct cvmx_gmxx_rx_bp_dropx_s cn68xxp1; 4602 struct cvmx_gmxx_rx_bp_dropx_s cnf71xx; 4603}; 4604 4605union cvmx_gmxx_rx_bp_offx { 4606 uint64_t u64; 4607 struct cvmx_gmxx_rx_bp_offx_s { 4608#ifdef __BIG_ENDIAN_BITFIELD 4609 uint64_t reserved_6_63:58; 4610 uint64_t mark:6; 4611#else 4612 uint64_t mark:6; 4613 uint64_t reserved_6_63:58; 4614#endif 4615 } s; 4616 struct cvmx_gmxx_rx_bp_offx_s cn30xx; 4617 struct cvmx_gmxx_rx_bp_offx_s cn31xx; 4618 struct cvmx_gmxx_rx_bp_offx_s cn38xx; 4619 struct cvmx_gmxx_rx_bp_offx_s cn38xxp2; 4620 struct cvmx_gmxx_rx_bp_offx_s cn50xx; 4621 struct cvmx_gmxx_rx_bp_offx_s cn52xx; 4622 struct cvmx_gmxx_rx_bp_offx_s cn52xxp1; 4623 struct cvmx_gmxx_rx_bp_offx_s cn56xx; 4624 struct cvmx_gmxx_rx_bp_offx_s cn56xxp1; 4625 struct cvmx_gmxx_rx_bp_offx_s cn58xx; 4626 struct cvmx_gmxx_rx_bp_offx_s cn58xxp1; 4627 struct cvmx_gmxx_rx_bp_offx_s cn61xx; 4628 struct cvmx_gmxx_rx_bp_offx_s cn63xx; 4629 struct cvmx_gmxx_rx_bp_offx_s cn63xxp1; 4630 struct cvmx_gmxx_rx_bp_offx_s cn66xx; 4631 struct cvmx_gmxx_rx_bp_offx_s cn68xx; 4632 struct cvmx_gmxx_rx_bp_offx_s cn68xxp1; 4633 struct cvmx_gmxx_rx_bp_offx_s cnf71xx; 4634}; 4635 4636union cvmx_gmxx_rx_bp_onx { 4637 uint64_t u64; 4638 struct cvmx_gmxx_rx_bp_onx_s { 4639#ifdef __BIG_ENDIAN_BITFIELD 4640 uint64_t reserved_11_63:53; 4641 uint64_t mark:11; 4642#else 4643 uint64_t mark:11; 4644 uint64_t reserved_11_63:53; 4645#endif 4646 } s; 4647 struct cvmx_gmxx_rx_bp_onx_cn30xx { 4648#ifdef __BIG_ENDIAN_BITFIELD 4649 uint64_t reserved_9_63:55; 4650 uint64_t mark:9; 4651#else 4652 uint64_t mark:9; 4653 uint64_t reserved_9_63:55; 4654#endif 4655 } cn30xx; 4656 struct cvmx_gmxx_rx_bp_onx_cn30xx cn31xx; 4657 struct cvmx_gmxx_rx_bp_onx_cn30xx cn38xx; 4658 struct cvmx_gmxx_rx_bp_onx_cn30xx cn38xxp2; 4659 struct cvmx_gmxx_rx_bp_onx_cn30xx cn50xx; 4660 struct cvmx_gmxx_rx_bp_onx_cn30xx cn52xx; 4661 struct cvmx_gmxx_rx_bp_onx_cn30xx cn52xxp1; 4662 struct cvmx_gmxx_rx_bp_onx_cn30xx cn56xx; 4663 struct cvmx_gmxx_rx_bp_onx_cn30xx cn56xxp1; 4664 struct cvmx_gmxx_rx_bp_onx_cn30xx cn58xx; 4665 struct cvmx_gmxx_rx_bp_onx_cn30xx cn58xxp1; 4666 struct cvmx_gmxx_rx_bp_onx_cn30xx cn61xx; 4667 struct cvmx_gmxx_rx_bp_onx_cn30xx cn63xx; 4668 struct cvmx_gmxx_rx_bp_onx_cn30xx cn63xxp1; 4669 struct cvmx_gmxx_rx_bp_onx_cn30xx cn66xx; 4670 struct cvmx_gmxx_rx_bp_onx_s cn68xx; 4671 struct cvmx_gmxx_rx_bp_onx_s cn68xxp1; 4672 struct cvmx_gmxx_rx_bp_onx_cn30xx cnf71xx; 4673}; 4674 4675union cvmx_gmxx_rx_hg2_status { 4676 uint64_t u64; 4677 struct cvmx_gmxx_rx_hg2_status_s { 4678#ifdef __BIG_ENDIAN_BITFIELD 4679 uint64_t reserved_48_63:16; 4680 uint64_t phtim2go:16; 4681 uint64_t xof:16; 4682 uint64_t lgtim2go:16; 4683#else 4684 uint64_t lgtim2go:16; 4685 uint64_t xof:16; 4686 uint64_t phtim2go:16; 4687 uint64_t reserved_48_63:16; 4688#endif 4689 } s; 4690 struct cvmx_gmxx_rx_hg2_status_s cn52xx; 4691 struct cvmx_gmxx_rx_hg2_status_s cn52xxp1; 4692 struct cvmx_gmxx_rx_hg2_status_s cn56xx; 4693 struct cvmx_gmxx_rx_hg2_status_s cn61xx; 4694 struct cvmx_gmxx_rx_hg2_status_s cn63xx; 4695 struct cvmx_gmxx_rx_hg2_status_s cn63xxp1; 4696 struct cvmx_gmxx_rx_hg2_status_s cn66xx; 4697 struct cvmx_gmxx_rx_hg2_status_s cn68xx; 4698 struct cvmx_gmxx_rx_hg2_status_s cn68xxp1; 4699 struct cvmx_gmxx_rx_hg2_status_s cnf71xx; 4700}; 4701 4702union cvmx_gmxx_rx_pass_en { 4703 uint64_t u64; 4704 struct cvmx_gmxx_rx_pass_en_s { 4705#ifdef __BIG_ENDIAN_BITFIELD 4706 uint64_t reserved_16_63:48; 4707 uint64_t en:16; 4708#else 4709 uint64_t en:16; 4710 uint64_t reserved_16_63:48; 4711#endif 4712 } s; 4713 struct cvmx_gmxx_rx_pass_en_s cn38xx; 4714 struct cvmx_gmxx_rx_pass_en_s cn38xxp2; 4715 struct cvmx_gmxx_rx_pass_en_s cn58xx; 4716 struct cvmx_gmxx_rx_pass_en_s cn58xxp1; 4717}; 4718 4719union cvmx_gmxx_rx_pass_mapx { 4720 uint64_t u64; 4721 struct cvmx_gmxx_rx_pass_mapx_s { 4722#ifdef __BIG_ENDIAN_BITFIELD 4723 uint64_t reserved_4_63:60; 4724 uint64_t dprt:4; 4725#else 4726 uint64_t dprt:4; 4727 uint64_t reserved_4_63:60; 4728#endif 4729 } s; 4730 struct cvmx_gmxx_rx_pass_mapx_s cn38xx; 4731 struct cvmx_gmxx_rx_pass_mapx_s cn38xxp2; 4732 struct cvmx_gmxx_rx_pass_mapx_s cn58xx; 4733 struct cvmx_gmxx_rx_pass_mapx_s cn58xxp1; 4734}; 4735 4736union cvmx_gmxx_rx_prt_info { 4737 uint64_t u64; 4738 struct cvmx_gmxx_rx_prt_info_s { 4739#ifdef __BIG_ENDIAN_BITFIELD 4740 uint64_t reserved_32_63:32; 4741 uint64_t drop:16; 4742 uint64_t commit:16; 4743#else 4744 uint64_t commit:16; 4745 uint64_t drop:16; 4746 uint64_t reserved_32_63:32; 4747#endif 4748 } s; 4749 struct cvmx_gmxx_rx_prt_info_cn30xx { 4750#ifdef __BIG_ENDIAN_BITFIELD 4751 uint64_t reserved_19_63:45; 4752 uint64_t drop:3; 4753 uint64_t reserved_3_15:13; 4754 uint64_t commit:3; 4755#else 4756 uint64_t commit:3; 4757 uint64_t reserved_3_15:13; 4758 uint64_t drop:3; 4759 uint64_t reserved_19_63:45; 4760#endif 4761 } cn30xx; 4762 struct cvmx_gmxx_rx_prt_info_cn30xx cn31xx; 4763 struct cvmx_gmxx_rx_prt_info_s cn38xx; 4764 struct cvmx_gmxx_rx_prt_info_cn30xx cn50xx; 4765 struct cvmx_gmxx_rx_prt_info_cn52xx { 4766#ifdef __BIG_ENDIAN_BITFIELD 4767 uint64_t reserved_20_63:44; 4768 uint64_t drop:4; 4769 uint64_t reserved_4_15:12; 4770 uint64_t commit:4; 4771#else 4772 uint64_t commit:4; 4773 uint64_t reserved_4_15:12; 4774 uint64_t drop:4; 4775 uint64_t reserved_20_63:44; 4776#endif 4777 } cn52xx; 4778 struct cvmx_gmxx_rx_prt_info_cn52xx cn52xxp1; 4779 struct cvmx_gmxx_rx_prt_info_cn52xx cn56xx; 4780 struct cvmx_gmxx_rx_prt_info_cn52xx cn56xxp1; 4781 struct cvmx_gmxx_rx_prt_info_s cn58xx; 4782 struct cvmx_gmxx_rx_prt_info_s cn58xxp1; 4783 struct cvmx_gmxx_rx_prt_info_cn52xx cn61xx; 4784 struct cvmx_gmxx_rx_prt_info_cn52xx cn63xx; 4785 struct cvmx_gmxx_rx_prt_info_cn52xx cn63xxp1; 4786 struct cvmx_gmxx_rx_prt_info_cn52xx cn66xx; 4787 struct cvmx_gmxx_rx_prt_info_cn52xx cn68xx; 4788 struct cvmx_gmxx_rx_prt_info_cn52xx cn68xxp1; 4789 struct cvmx_gmxx_rx_prt_info_cnf71xx { 4790#ifdef __BIG_ENDIAN_BITFIELD 4791 uint64_t reserved_18_63:46; 4792 uint64_t drop:2; 4793 uint64_t reserved_2_15:14; 4794 uint64_t commit:2; 4795#else 4796 uint64_t commit:2; 4797 uint64_t reserved_2_15:14; 4798 uint64_t drop:2; 4799 uint64_t reserved_18_63:46; 4800#endif 4801 } cnf71xx; 4802}; 4803 4804union cvmx_gmxx_rx_prts { 4805 uint64_t u64; 4806 struct cvmx_gmxx_rx_prts_s { 4807#ifdef __BIG_ENDIAN_BITFIELD 4808 uint64_t reserved_3_63:61; 4809 uint64_t prts:3; 4810#else 4811 uint64_t prts:3; 4812 uint64_t reserved_3_63:61; 4813#endif 4814 } s; 4815 struct cvmx_gmxx_rx_prts_s cn30xx; 4816 struct cvmx_gmxx_rx_prts_s cn31xx; 4817 struct cvmx_gmxx_rx_prts_s cn38xx; 4818 struct cvmx_gmxx_rx_prts_s cn38xxp2; 4819 struct cvmx_gmxx_rx_prts_s cn50xx; 4820 struct cvmx_gmxx_rx_prts_s cn52xx; 4821 struct cvmx_gmxx_rx_prts_s cn52xxp1; 4822 struct cvmx_gmxx_rx_prts_s cn56xx; 4823 struct cvmx_gmxx_rx_prts_s cn56xxp1; 4824 struct cvmx_gmxx_rx_prts_s cn58xx; 4825 struct cvmx_gmxx_rx_prts_s cn58xxp1; 4826 struct cvmx_gmxx_rx_prts_s cn61xx; 4827 struct cvmx_gmxx_rx_prts_s cn63xx; 4828 struct cvmx_gmxx_rx_prts_s cn63xxp1; 4829 struct cvmx_gmxx_rx_prts_s cn66xx; 4830 struct cvmx_gmxx_rx_prts_s cn68xx; 4831 struct cvmx_gmxx_rx_prts_s cn68xxp1; 4832 struct cvmx_gmxx_rx_prts_s cnf71xx; 4833}; 4834 4835union cvmx_gmxx_rx_tx_status { 4836 uint64_t u64; 4837 struct cvmx_gmxx_rx_tx_status_s { 4838#ifdef __BIG_ENDIAN_BITFIELD 4839 uint64_t reserved_7_63:57; 4840 uint64_t tx:3; 4841 uint64_t reserved_3_3:1; 4842 uint64_t rx:3; 4843#else 4844 uint64_t rx:3; 4845 uint64_t reserved_3_3:1; 4846 uint64_t tx:3; 4847 uint64_t reserved_7_63:57; 4848#endif 4849 } s; 4850 struct cvmx_gmxx_rx_tx_status_s cn30xx; 4851 struct cvmx_gmxx_rx_tx_status_s cn31xx; 4852 struct cvmx_gmxx_rx_tx_status_s cn50xx; 4853}; 4854 4855union cvmx_gmxx_rx_xaui_bad_col { 4856 uint64_t u64; 4857 struct cvmx_gmxx_rx_xaui_bad_col_s { 4858#ifdef __BIG_ENDIAN_BITFIELD 4859 uint64_t reserved_40_63:24; 4860 uint64_t val:1; 4861 uint64_t state:3; 4862 uint64_t lane_rxc:4; 4863 uint64_t lane_rxd:32; 4864#else 4865 uint64_t lane_rxd:32; 4866 uint64_t lane_rxc:4; 4867 uint64_t state:3; 4868 uint64_t val:1; 4869 uint64_t reserved_40_63:24; 4870#endif 4871 } s; 4872 struct cvmx_gmxx_rx_xaui_bad_col_s cn52xx; 4873 struct cvmx_gmxx_rx_xaui_bad_col_s cn52xxp1; 4874 struct cvmx_gmxx_rx_xaui_bad_col_s cn56xx; 4875 struct cvmx_gmxx_rx_xaui_bad_col_s cn56xxp1; 4876 struct cvmx_gmxx_rx_xaui_bad_col_s cn61xx; 4877 struct cvmx_gmxx_rx_xaui_bad_col_s cn63xx; 4878 struct cvmx_gmxx_rx_xaui_bad_col_s cn63xxp1; 4879 struct cvmx_gmxx_rx_xaui_bad_col_s cn66xx; 4880 struct cvmx_gmxx_rx_xaui_bad_col_s cn68xx; 4881 struct cvmx_gmxx_rx_xaui_bad_col_s cn68xxp1; 4882 struct cvmx_gmxx_rx_xaui_bad_col_s cnf71xx; 4883}; 4884 4885union cvmx_gmxx_rx_xaui_ctl { 4886 uint64_t u64; 4887 struct cvmx_gmxx_rx_xaui_ctl_s { 4888#ifdef __BIG_ENDIAN_BITFIELD 4889 uint64_t reserved_2_63:62; 4890 uint64_t status:2; 4891#else 4892 uint64_t status:2; 4893 uint64_t reserved_2_63:62; 4894#endif 4895 } s; 4896 struct cvmx_gmxx_rx_xaui_ctl_s cn52xx; 4897 struct cvmx_gmxx_rx_xaui_ctl_s cn52xxp1; 4898 struct cvmx_gmxx_rx_xaui_ctl_s cn56xx; 4899 struct cvmx_gmxx_rx_xaui_ctl_s cn56xxp1; 4900 struct cvmx_gmxx_rx_xaui_ctl_s cn61xx; 4901 struct cvmx_gmxx_rx_xaui_ctl_s cn63xx; 4902 struct cvmx_gmxx_rx_xaui_ctl_s cn63xxp1; 4903 struct cvmx_gmxx_rx_xaui_ctl_s cn66xx; 4904 struct cvmx_gmxx_rx_xaui_ctl_s cn68xx; 4905 struct cvmx_gmxx_rx_xaui_ctl_s cn68xxp1; 4906 struct cvmx_gmxx_rx_xaui_ctl_s cnf71xx; 4907}; 4908 4909union cvmx_gmxx_rxaui_ctl { 4910 uint64_t u64; 4911 struct cvmx_gmxx_rxaui_ctl_s { 4912#ifdef __BIG_ENDIAN_BITFIELD 4913 uint64_t reserved_1_63:63; 4914 uint64_t disparity:1; 4915#else 4916 uint64_t disparity:1; 4917 uint64_t reserved_1_63:63; 4918#endif 4919 } s; 4920 struct cvmx_gmxx_rxaui_ctl_s cn68xx; 4921 struct cvmx_gmxx_rxaui_ctl_s cn68xxp1; 4922}; 4923 4924union cvmx_gmxx_smacx { 4925 uint64_t u64; 4926 struct cvmx_gmxx_smacx_s { 4927#ifdef __BIG_ENDIAN_BITFIELD 4928 uint64_t reserved_48_63:16; 4929 uint64_t smac:48; 4930#else 4931 uint64_t smac:48; 4932 uint64_t reserved_48_63:16; 4933#endif 4934 } s; 4935 struct cvmx_gmxx_smacx_s cn30xx; 4936 struct cvmx_gmxx_smacx_s cn31xx; 4937 struct cvmx_gmxx_smacx_s cn38xx; 4938 struct cvmx_gmxx_smacx_s cn38xxp2; 4939 struct cvmx_gmxx_smacx_s cn50xx; 4940 struct cvmx_gmxx_smacx_s cn52xx; 4941 struct cvmx_gmxx_smacx_s cn52xxp1; 4942 struct cvmx_gmxx_smacx_s cn56xx; 4943 struct cvmx_gmxx_smacx_s cn56xxp1; 4944 struct cvmx_gmxx_smacx_s cn58xx; 4945 struct cvmx_gmxx_smacx_s cn58xxp1; 4946 struct cvmx_gmxx_smacx_s cn61xx; 4947 struct cvmx_gmxx_smacx_s cn63xx; 4948 struct cvmx_gmxx_smacx_s cn63xxp1; 4949 struct cvmx_gmxx_smacx_s cn66xx; 4950 struct cvmx_gmxx_smacx_s cn68xx; 4951 struct cvmx_gmxx_smacx_s cn68xxp1; 4952 struct cvmx_gmxx_smacx_s cnf71xx; 4953}; 4954 4955union cvmx_gmxx_soft_bist { 4956 uint64_t u64; 4957 struct cvmx_gmxx_soft_bist_s { 4958#ifdef __BIG_ENDIAN_BITFIELD 4959 uint64_t reserved_2_63:62; 4960 uint64_t start_bist:1; 4961 uint64_t clear_bist:1; 4962#else 4963 uint64_t clear_bist:1; 4964 uint64_t start_bist:1; 4965 uint64_t reserved_2_63:62; 4966#endif 4967 } s; 4968 struct cvmx_gmxx_soft_bist_s cn63xx; 4969 struct cvmx_gmxx_soft_bist_s cn63xxp1; 4970 struct cvmx_gmxx_soft_bist_s cn66xx; 4971 struct cvmx_gmxx_soft_bist_s cn68xx; 4972 struct cvmx_gmxx_soft_bist_s cn68xxp1; 4973}; 4974 4975union cvmx_gmxx_stat_bp { 4976 uint64_t u64; 4977 struct cvmx_gmxx_stat_bp_s { 4978#ifdef __BIG_ENDIAN_BITFIELD 4979 uint64_t reserved_17_63:47; 4980 uint64_t bp:1; 4981 uint64_t cnt:16; 4982#else 4983 uint64_t cnt:16; 4984 uint64_t bp:1; 4985 uint64_t reserved_17_63:47; 4986#endif 4987 } s; 4988 struct cvmx_gmxx_stat_bp_s cn30xx; 4989 struct cvmx_gmxx_stat_bp_s cn31xx; 4990 struct cvmx_gmxx_stat_bp_s cn38xx; 4991 struct cvmx_gmxx_stat_bp_s cn38xxp2; 4992 struct cvmx_gmxx_stat_bp_s cn50xx; 4993 struct cvmx_gmxx_stat_bp_s cn52xx; 4994 struct cvmx_gmxx_stat_bp_s cn52xxp1; 4995 struct cvmx_gmxx_stat_bp_s cn56xx; 4996 struct cvmx_gmxx_stat_bp_s cn56xxp1; 4997 struct cvmx_gmxx_stat_bp_s cn58xx; 4998 struct cvmx_gmxx_stat_bp_s cn58xxp1; 4999 struct cvmx_gmxx_stat_bp_s cn61xx; 5000 struct cvmx_gmxx_stat_bp_s cn63xx; 5001 struct cvmx_gmxx_stat_bp_s cn63xxp1; 5002 struct cvmx_gmxx_stat_bp_s cn66xx; 5003 struct cvmx_gmxx_stat_bp_s cn68xx; 5004 struct cvmx_gmxx_stat_bp_s cn68xxp1; 5005 struct cvmx_gmxx_stat_bp_s cnf71xx; 5006}; 5007 5008union cvmx_gmxx_tb_reg { 5009 uint64_t u64; 5010 struct cvmx_gmxx_tb_reg_s { 5011#ifdef __BIG_ENDIAN_BITFIELD 5012 uint64_t reserved_1_63:63; 5013 uint64_t wr_magic:1; 5014#else 5015 uint64_t wr_magic:1; 5016 uint64_t reserved_1_63:63; 5017#endif 5018 } s; 5019 struct cvmx_gmxx_tb_reg_s cn61xx; 5020 struct cvmx_gmxx_tb_reg_s cn66xx; 5021 struct cvmx_gmxx_tb_reg_s cn68xx; 5022 struct cvmx_gmxx_tb_reg_s cnf71xx; 5023}; 5024 5025union cvmx_gmxx_txx_append { 5026 uint64_t u64; 5027 struct cvmx_gmxx_txx_append_s { 5028#ifdef __BIG_ENDIAN_BITFIELD 5029 uint64_t reserved_4_63:60; 5030 uint64_t force_fcs:1; 5031 uint64_t fcs:1; 5032 uint64_t pad:1; 5033 uint64_t preamble:1; 5034#else 5035 uint64_t preamble:1; 5036 uint64_t pad:1; 5037 uint64_t fcs:1; 5038 uint64_t force_fcs:1; 5039 uint64_t reserved_4_63:60; 5040#endif 5041 } s; 5042 struct cvmx_gmxx_txx_append_s cn30xx; 5043 struct cvmx_gmxx_txx_append_s cn31xx; 5044 struct cvmx_gmxx_txx_append_s cn38xx; 5045 struct cvmx_gmxx_txx_append_s cn38xxp2; 5046 struct cvmx_gmxx_txx_append_s cn50xx; 5047 struct cvmx_gmxx_txx_append_s cn52xx; 5048 struct cvmx_gmxx_txx_append_s cn52xxp1; 5049 struct cvmx_gmxx_txx_append_s cn56xx; 5050 struct cvmx_gmxx_txx_append_s cn56xxp1; 5051 struct cvmx_gmxx_txx_append_s cn58xx; 5052 struct cvmx_gmxx_txx_append_s cn58xxp1; 5053 struct cvmx_gmxx_txx_append_s cn61xx; 5054 struct cvmx_gmxx_txx_append_s cn63xx; 5055 struct cvmx_gmxx_txx_append_s cn63xxp1; 5056 struct cvmx_gmxx_txx_append_s cn66xx; 5057 struct cvmx_gmxx_txx_append_s cn68xx; 5058 struct cvmx_gmxx_txx_append_s cn68xxp1; 5059 struct cvmx_gmxx_txx_append_s cnf71xx; 5060}; 5061 5062union cvmx_gmxx_txx_burst { 5063 uint64_t u64; 5064 struct cvmx_gmxx_txx_burst_s { 5065#ifdef __BIG_ENDIAN_BITFIELD 5066 uint64_t reserved_16_63:48; 5067 uint64_t burst:16; 5068#else 5069 uint64_t burst:16; 5070 uint64_t reserved_16_63:48; 5071#endif 5072 } s; 5073 struct cvmx_gmxx_txx_burst_s cn30xx; 5074 struct cvmx_gmxx_txx_burst_s cn31xx; 5075 struct cvmx_gmxx_txx_burst_s cn38xx; 5076 struct cvmx_gmxx_txx_burst_s cn38xxp2; 5077 struct cvmx_gmxx_txx_burst_s cn50xx; 5078 struct cvmx_gmxx_txx_burst_s cn52xx; 5079 struct cvmx_gmxx_txx_burst_s cn52xxp1; 5080 struct cvmx_gmxx_txx_burst_s cn56xx; 5081 struct cvmx_gmxx_txx_burst_s cn56xxp1; 5082 struct cvmx_gmxx_txx_burst_s cn58xx; 5083 struct cvmx_gmxx_txx_burst_s cn58xxp1; 5084 struct cvmx_gmxx_txx_burst_s cn61xx; 5085 struct cvmx_gmxx_txx_burst_s cn63xx; 5086 struct cvmx_gmxx_txx_burst_s cn63xxp1; 5087 struct cvmx_gmxx_txx_burst_s cn66xx; 5088 struct cvmx_gmxx_txx_burst_s cn68xx; 5089 struct cvmx_gmxx_txx_burst_s cn68xxp1; 5090 struct cvmx_gmxx_txx_burst_s cnf71xx; 5091}; 5092 5093union cvmx_gmxx_txx_cbfc_xoff { 5094 uint64_t u64; 5095 struct cvmx_gmxx_txx_cbfc_xoff_s { 5096#ifdef __BIG_ENDIAN_BITFIELD 5097 uint64_t reserved_16_63:48; 5098 uint64_t xoff:16; 5099#else 5100 uint64_t xoff:16; 5101 uint64_t reserved_16_63:48; 5102#endif 5103 } s; 5104 struct cvmx_gmxx_txx_cbfc_xoff_s cn52xx; 5105 struct cvmx_gmxx_txx_cbfc_xoff_s cn56xx; 5106 struct cvmx_gmxx_txx_cbfc_xoff_s cn61xx; 5107 struct cvmx_gmxx_txx_cbfc_xoff_s cn63xx; 5108 struct cvmx_gmxx_txx_cbfc_xoff_s cn63xxp1; 5109 struct cvmx_gmxx_txx_cbfc_xoff_s cn66xx; 5110 struct cvmx_gmxx_txx_cbfc_xoff_s cn68xx; 5111 struct cvmx_gmxx_txx_cbfc_xoff_s cn68xxp1; 5112 struct cvmx_gmxx_txx_cbfc_xoff_s cnf71xx; 5113}; 5114 5115union cvmx_gmxx_txx_cbfc_xon { 5116 uint64_t u64; 5117 struct cvmx_gmxx_txx_cbfc_xon_s { 5118#ifdef __BIG_ENDIAN_BITFIELD 5119 uint64_t reserved_16_63:48; 5120 uint64_t xon:16; 5121#else 5122 uint64_t xon:16; 5123 uint64_t reserved_16_63:48; 5124#endif 5125 } s; 5126 struct cvmx_gmxx_txx_cbfc_xon_s cn52xx; 5127 struct cvmx_gmxx_txx_cbfc_xon_s cn56xx; 5128 struct cvmx_gmxx_txx_cbfc_xon_s cn61xx; 5129 struct cvmx_gmxx_txx_cbfc_xon_s cn63xx; 5130 struct cvmx_gmxx_txx_cbfc_xon_s cn63xxp1; 5131 struct cvmx_gmxx_txx_cbfc_xon_s cn66xx; 5132 struct cvmx_gmxx_txx_cbfc_xon_s cn68xx; 5133 struct cvmx_gmxx_txx_cbfc_xon_s cn68xxp1; 5134 struct cvmx_gmxx_txx_cbfc_xon_s cnf71xx; 5135}; 5136 5137union cvmx_gmxx_txx_clk { 5138 uint64_t u64; 5139 struct cvmx_gmxx_txx_clk_s { 5140#ifdef __BIG_ENDIAN_BITFIELD 5141 uint64_t reserved_6_63:58; 5142 uint64_t clk_cnt:6; 5143#else 5144 uint64_t clk_cnt:6; 5145 uint64_t reserved_6_63:58; 5146#endif 5147 } s; 5148 struct cvmx_gmxx_txx_clk_s cn30xx; 5149 struct cvmx_gmxx_txx_clk_s cn31xx; 5150 struct cvmx_gmxx_txx_clk_s cn38xx; 5151 struct cvmx_gmxx_txx_clk_s cn38xxp2; 5152 struct cvmx_gmxx_txx_clk_s cn50xx; 5153 struct cvmx_gmxx_txx_clk_s cn58xx; 5154 struct cvmx_gmxx_txx_clk_s cn58xxp1; 5155}; 5156 5157union cvmx_gmxx_txx_ctl { 5158 uint64_t u64; 5159 struct cvmx_gmxx_txx_ctl_s { 5160#ifdef __BIG_ENDIAN_BITFIELD 5161 uint64_t reserved_2_63:62; 5162 uint64_t xsdef_en:1; 5163 uint64_t xscol_en:1; 5164#else 5165 uint64_t xscol_en:1; 5166 uint64_t xsdef_en:1; 5167 uint64_t reserved_2_63:62; 5168#endif 5169 } s; 5170 struct cvmx_gmxx_txx_ctl_s cn30xx; 5171 struct cvmx_gmxx_txx_ctl_s cn31xx; 5172 struct cvmx_gmxx_txx_ctl_s cn38xx; 5173 struct cvmx_gmxx_txx_ctl_s cn38xxp2; 5174 struct cvmx_gmxx_txx_ctl_s cn50xx; 5175 struct cvmx_gmxx_txx_ctl_s cn52xx; 5176 struct cvmx_gmxx_txx_ctl_s cn52xxp1; 5177 struct cvmx_gmxx_txx_ctl_s cn56xx; 5178 struct cvmx_gmxx_txx_ctl_s cn56xxp1; 5179 struct cvmx_gmxx_txx_ctl_s cn58xx; 5180 struct cvmx_gmxx_txx_ctl_s cn58xxp1; 5181 struct cvmx_gmxx_txx_ctl_s cn61xx; 5182 struct cvmx_gmxx_txx_ctl_s cn63xx; 5183 struct cvmx_gmxx_txx_ctl_s cn63xxp1; 5184 struct cvmx_gmxx_txx_ctl_s cn66xx; 5185 struct cvmx_gmxx_txx_ctl_s cn68xx; 5186 struct cvmx_gmxx_txx_ctl_s cn68xxp1; 5187 struct cvmx_gmxx_txx_ctl_s cnf71xx; 5188}; 5189 5190union cvmx_gmxx_txx_min_pkt { 5191 uint64_t u64; 5192 struct cvmx_gmxx_txx_min_pkt_s { 5193#ifdef __BIG_ENDIAN_BITFIELD 5194 uint64_t reserved_8_63:56; 5195 uint64_t min_size:8; 5196#else 5197 uint64_t min_size:8; 5198 uint64_t reserved_8_63:56; 5199#endif 5200 } s; 5201 struct cvmx_gmxx_txx_min_pkt_s cn30xx; 5202 struct cvmx_gmxx_txx_min_pkt_s cn31xx; 5203 struct cvmx_gmxx_txx_min_pkt_s cn38xx; 5204 struct cvmx_gmxx_txx_min_pkt_s cn38xxp2; 5205 struct cvmx_gmxx_txx_min_pkt_s cn50xx; 5206 struct cvmx_gmxx_txx_min_pkt_s cn52xx; 5207 struct cvmx_gmxx_txx_min_pkt_s cn52xxp1; 5208 struct cvmx_gmxx_txx_min_pkt_s cn56xx; 5209 struct cvmx_gmxx_txx_min_pkt_s cn56xxp1; 5210 struct cvmx_gmxx_txx_min_pkt_s cn58xx; 5211 struct cvmx_gmxx_txx_min_pkt_s cn58xxp1; 5212 struct cvmx_gmxx_txx_min_pkt_s cn61xx; 5213 struct cvmx_gmxx_txx_min_pkt_s cn63xx; 5214 struct cvmx_gmxx_txx_min_pkt_s cn63xxp1; 5215 struct cvmx_gmxx_txx_min_pkt_s cn66xx; 5216 struct cvmx_gmxx_txx_min_pkt_s cn68xx; 5217 struct cvmx_gmxx_txx_min_pkt_s cn68xxp1; 5218 struct cvmx_gmxx_txx_min_pkt_s cnf71xx; 5219}; 5220 5221union cvmx_gmxx_txx_pause_pkt_interval { 5222 uint64_t u64; 5223 struct cvmx_gmxx_txx_pause_pkt_interval_s { 5224#ifdef __BIG_ENDIAN_BITFIELD 5225 uint64_t reserved_16_63:48; 5226 uint64_t interval:16; 5227#else 5228 uint64_t interval:16; 5229 uint64_t reserved_16_63:48; 5230#endif 5231 } s; 5232 struct cvmx_gmxx_txx_pause_pkt_interval_s cn30xx; 5233 struct cvmx_gmxx_txx_pause_pkt_interval_s cn31xx; 5234 struct cvmx_gmxx_txx_pause_pkt_interval_s cn38xx; 5235 struct cvmx_gmxx_txx_pause_pkt_interval_s cn38xxp2; 5236 struct cvmx_gmxx_txx_pause_pkt_interval_s cn50xx; 5237 struct cvmx_gmxx_txx_pause_pkt_interval_s cn52xx; 5238 struct cvmx_gmxx_txx_pause_pkt_interval_s cn52xxp1; 5239 struct cvmx_gmxx_txx_pause_pkt_interval_s cn56xx; 5240 struct cvmx_gmxx_txx_pause_pkt_interval_s cn56xxp1; 5241 struct cvmx_gmxx_txx_pause_pkt_interval_s cn58xx; 5242 struct cvmx_gmxx_txx_pause_pkt_interval_s cn58xxp1; 5243 struct cvmx_gmxx_txx_pause_pkt_interval_s cn61xx; 5244 struct cvmx_gmxx_txx_pause_pkt_interval_s cn63xx; 5245 struct cvmx_gmxx_txx_pause_pkt_interval_s cn63xxp1; 5246 struct cvmx_gmxx_txx_pause_pkt_interval_s cn66xx; 5247 struct cvmx_gmxx_txx_pause_pkt_interval_s cn68xx; 5248 struct cvmx_gmxx_txx_pause_pkt_interval_s cn68xxp1; 5249 struct cvmx_gmxx_txx_pause_pkt_interval_s cnf71xx; 5250}; 5251 5252union cvmx_gmxx_txx_pause_pkt_time { 5253 uint64_t u64; 5254 struct cvmx_gmxx_txx_pause_pkt_time_s { 5255#ifdef __BIG_ENDIAN_BITFIELD 5256 uint64_t reserved_16_63:48; 5257 uint64_t time:16; 5258#else 5259 uint64_t time:16; 5260 uint64_t reserved_16_63:48; 5261#endif 5262 } s; 5263 struct cvmx_gmxx_txx_pause_pkt_time_s cn30xx; 5264 struct cvmx_gmxx_txx_pause_pkt_time_s cn31xx; 5265 struct cvmx_gmxx_txx_pause_pkt_time_s cn38xx; 5266 struct cvmx_gmxx_txx_pause_pkt_time_s cn38xxp2; 5267 struct cvmx_gmxx_txx_pause_pkt_time_s cn50xx; 5268 struct cvmx_gmxx_txx_pause_pkt_time_s cn52xx; 5269 struct cvmx_gmxx_txx_pause_pkt_time_s cn52xxp1; 5270 struct cvmx_gmxx_txx_pause_pkt_time_s cn56xx; 5271 struct cvmx_gmxx_txx_pause_pkt_time_s cn56xxp1; 5272 struct cvmx_gmxx_txx_pause_pkt_time_s cn58xx; 5273 struct cvmx_gmxx_txx_pause_pkt_time_s cn58xxp1; 5274 struct cvmx_gmxx_txx_pause_pkt_time_s cn61xx; 5275 struct cvmx_gmxx_txx_pause_pkt_time_s cn63xx; 5276 struct cvmx_gmxx_txx_pause_pkt_time_s cn63xxp1; 5277 struct cvmx_gmxx_txx_pause_pkt_time_s cn66xx; 5278 struct cvmx_gmxx_txx_pause_pkt_time_s cn68xx; 5279 struct cvmx_gmxx_txx_pause_pkt_time_s cn68xxp1; 5280 struct cvmx_gmxx_txx_pause_pkt_time_s cnf71xx; 5281}; 5282 5283union cvmx_gmxx_txx_pause_togo { 5284 uint64_t u64; 5285 struct cvmx_gmxx_txx_pause_togo_s { 5286#ifdef __BIG_ENDIAN_BITFIELD 5287 uint64_t reserved_32_63:32; 5288 uint64_t msg_time:16; 5289 uint64_t time:16; 5290#else 5291 uint64_t time:16; 5292 uint64_t msg_time:16; 5293 uint64_t reserved_32_63:32; 5294#endif 5295 } s; 5296 struct cvmx_gmxx_txx_pause_togo_cn30xx { 5297#ifdef __BIG_ENDIAN_BITFIELD 5298 uint64_t reserved_16_63:48; 5299 uint64_t time:16; 5300#else 5301 uint64_t time:16; 5302 uint64_t reserved_16_63:48; 5303#endif 5304 } cn30xx; 5305 struct cvmx_gmxx_txx_pause_togo_cn30xx cn31xx; 5306 struct cvmx_gmxx_txx_pause_togo_cn30xx cn38xx; 5307 struct cvmx_gmxx_txx_pause_togo_cn30xx cn38xxp2; 5308 struct cvmx_gmxx_txx_pause_togo_cn30xx cn50xx; 5309 struct cvmx_gmxx_txx_pause_togo_s cn52xx; 5310 struct cvmx_gmxx_txx_pause_togo_s cn52xxp1; 5311 struct cvmx_gmxx_txx_pause_togo_s cn56xx; 5312 struct cvmx_gmxx_txx_pause_togo_cn30xx cn56xxp1; 5313 struct cvmx_gmxx_txx_pause_togo_cn30xx cn58xx; 5314 struct cvmx_gmxx_txx_pause_togo_cn30xx cn58xxp1; 5315 struct cvmx_gmxx_txx_pause_togo_s cn61xx; 5316 struct cvmx_gmxx_txx_pause_togo_s cn63xx; 5317 struct cvmx_gmxx_txx_pause_togo_s cn63xxp1; 5318 struct cvmx_gmxx_txx_pause_togo_s cn66xx; 5319 struct cvmx_gmxx_txx_pause_togo_s cn68xx; 5320 struct cvmx_gmxx_txx_pause_togo_s cn68xxp1; 5321 struct cvmx_gmxx_txx_pause_togo_s cnf71xx; 5322}; 5323 5324union cvmx_gmxx_txx_pause_zero { 5325 uint64_t u64; 5326 struct cvmx_gmxx_txx_pause_zero_s { 5327#ifdef __BIG_ENDIAN_BITFIELD 5328 uint64_t reserved_1_63:63; 5329 uint64_t send:1; 5330#else 5331 uint64_t send:1; 5332 uint64_t reserved_1_63:63; 5333#endif 5334 } s; 5335 struct cvmx_gmxx_txx_pause_zero_s cn30xx; 5336 struct cvmx_gmxx_txx_pause_zero_s cn31xx; 5337 struct cvmx_gmxx_txx_pause_zero_s cn38xx; 5338 struct cvmx_gmxx_txx_pause_zero_s cn38xxp2; 5339 struct cvmx_gmxx_txx_pause_zero_s cn50xx; 5340 struct cvmx_gmxx_txx_pause_zero_s cn52xx; 5341 struct cvmx_gmxx_txx_pause_zero_s cn52xxp1; 5342 struct cvmx_gmxx_txx_pause_zero_s cn56xx; 5343 struct cvmx_gmxx_txx_pause_zero_s cn56xxp1; 5344 struct cvmx_gmxx_txx_pause_zero_s cn58xx; 5345 struct cvmx_gmxx_txx_pause_zero_s cn58xxp1; 5346 struct cvmx_gmxx_txx_pause_zero_s cn61xx; 5347 struct cvmx_gmxx_txx_pause_zero_s cn63xx; 5348 struct cvmx_gmxx_txx_pause_zero_s cn63xxp1; 5349 struct cvmx_gmxx_txx_pause_zero_s cn66xx; 5350 struct cvmx_gmxx_txx_pause_zero_s cn68xx; 5351 struct cvmx_gmxx_txx_pause_zero_s cn68xxp1; 5352 struct cvmx_gmxx_txx_pause_zero_s cnf71xx; 5353}; 5354 5355union cvmx_gmxx_txx_pipe { 5356 uint64_t u64; 5357 struct cvmx_gmxx_txx_pipe_s { 5358#ifdef __BIG_ENDIAN_BITFIELD 5359 uint64_t reserved_33_63:31; 5360 uint64_t ign_bp:1; 5361 uint64_t reserved_21_31:11; 5362 uint64_t nump:5; 5363 uint64_t reserved_7_15:9; 5364 uint64_t base:7; 5365#else 5366 uint64_t base:7; 5367 uint64_t reserved_7_15:9; 5368 uint64_t nump:5; 5369 uint64_t reserved_21_31:11; 5370 uint64_t ign_bp:1; 5371 uint64_t reserved_33_63:31; 5372#endif 5373 } s; 5374 struct cvmx_gmxx_txx_pipe_s cn68xx; 5375 struct cvmx_gmxx_txx_pipe_s cn68xxp1; 5376}; 5377 5378union cvmx_gmxx_txx_sgmii_ctl { 5379 uint64_t u64; 5380 struct cvmx_gmxx_txx_sgmii_ctl_s { 5381#ifdef __BIG_ENDIAN_BITFIELD 5382 uint64_t reserved_1_63:63; 5383 uint64_t align:1; 5384#else 5385 uint64_t align:1; 5386 uint64_t reserved_1_63:63; 5387#endif 5388 } s; 5389 struct cvmx_gmxx_txx_sgmii_ctl_s cn52xx; 5390 struct cvmx_gmxx_txx_sgmii_ctl_s cn52xxp1; 5391 struct cvmx_gmxx_txx_sgmii_ctl_s cn56xx; 5392 struct cvmx_gmxx_txx_sgmii_ctl_s cn56xxp1; 5393 struct cvmx_gmxx_txx_sgmii_ctl_s cn61xx; 5394 struct cvmx_gmxx_txx_sgmii_ctl_s cn63xx; 5395 struct cvmx_gmxx_txx_sgmii_ctl_s cn63xxp1; 5396 struct cvmx_gmxx_txx_sgmii_ctl_s cn66xx; 5397 struct cvmx_gmxx_txx_sgmii_ctl_s cn68xx; 5398 struct cvmx_gmxx_txx_sgmii_ctl_s cn68xxp1; 5399 struct cvmx_gmxx_txx_sgmii_ctl_s cnf71xx; 5400}; 5401 5402union cvmx_gmxx_txx_slot { 5403 uint64_t u64; 5404 struct cvmx_gmxx_txx_slot_s { 5405#ifdef __BIG_ENDIAN_BITFIELD 5406 uint64_t reserved_10_63:54; 5407 uint64_t slot:10; 5408#else 5409 uint64_t slot:10; 5410 uint64_t reserved_10_63:54; 5411#endif 5412 } s; 5413 struct cvmx_gmxx_txx_slot_s cn30xx; 5414 struct cvmx_gmxx_txx_slot_s cn31xx; 5415 struct cvmx_gmxx_txx_slot_s cn38xx; 5416 struct cvmx_gmxx_txx_slot_s cn38xxp2; 5417 struct cvmx_gmxx_txx_slot_s cn50xx; 5418 struct cvmx_gmxx_txx_slot_s cn52xx; 5419 struct cvmx_gmxx_txx_slot_s cn52xxp1; 5420 struct cvmx_gmxx_txx_slot_s cn56xx; 5421 struct cvmx_gmxx_txx_slot_s cn56xxp1; 5422 struct cvmx_gmxx_txx_slot_s cn58xx; 5423 struct cvmx_gmxx_txx_slot_s cn58xxp1; 5424 struct cvmx_gmxx_txx_slot_s cn61xx; 5425 struct cvmx_gmxx_txx_slot_s cn63xx; 5426 struct cvmx_gmxx_txx_slot_s cn63xxp1; 5427 struct cvmx_gmxx_txx_slot_s cn66xx; 5428 struct cvmx_gmxx_txx_slot_s cn68xx; 5429 struct cvmx_gmxx_txx_slot_s cn68xxp1; 5430 struct cvmx_gmxx_txx_slot_s cnf71xx; 5431}; 5432 5433union cvmx_gmxx_txx_soft_pause { 5434 uint64_t u64; 5435 struct cvmx_gmxx_txx_soft_pause_s { 5436#ifdef __BIG_ENDIAN_BITFIELD 5437 uint64_t reserved_16_63:48; 5438 uint64_t time:16; 5439#else 5440 uint64_t time:16; 5441 uint64_t reserved_16_63:48; 5442#endif 5443 } s; 5444 struct cvmx_gmxx_txx_soft_pause_s cn30xx; 5445 struct cvmx_gmxx_txx_soft_pause_s cn31xx; 5446 struct cvmx_gmxx_txx_soft_pause_s cn38xx; 5447 struct cvmx_gmxx_txx_soft_pause_s cn38xxp2; 5448 struct cvmx_gmxx_txx_soft_pause_s cn50xx; 5449 struct cvmx_gmxx_txx_soft_pause_s cn52xx; 5450 struct cvmx_gmxx_txx_soft_pause_s cn52xxp1; 5451 struct cvmx_gmxx_txx_soft_pause_s cn56xx; 5452 struct cvmx_gmxx_txx_soft_pause_s cn56xxp1; 5453 struct cvmx_gmxx_txx_soft_pause_s cn58xx; 5454 struct cvmx_gmxx_txx_soft_pause_s cn58xxp1; 5455 struct cvmx_gmxx_txx_soft_pause_s cn61xx; 5456 struct cvmx_gmxx_txx_soft_pause_s cn63xx; 5457 struct cvmx_gmxx_txx_soft_pause_s cn63xxp1; 5458 struct cvmx_gmxx_txx_soft_pause_s cn66xx; 5459 struct cvmx_gmxx_txx_soft_pause_s cn68xx; 5460 struct cvmx_gmxx_txx_soft_pause_s cn68xxp1; 5461 struct cvmx_gmxx_txx_soft_pause_s cnf71xx; 5462}; 5463 5464union cvmx_gmxx_txx_stat0 { 5465 uint64_t u64; 5466 struct cvmx_gmxx_txx_stat0_s { 5467#ifdef __BIG_ENDIAN_BITFIELD 5468 uint64_t xsdef:32; 5469 uint64_t xscol:32; 5470#else 5471 uint64_t xscol:32; 5472 uint64_t xsdef:32; 5473#endif 5474 } s; 5475 struct cvmx_gmxx_txx_stat0_s cn30xx; 5476 struct cvmx_gmxx_txx_stat0_s cn31xx; 5477 struct cvmx_gmxx_txx_stat0_s cn38xx; 5478 struct cvmx_gmxx_txx_stat0_s cn38xxp2; 5479 struct cvmx_gmxx_txx_stat0_s cn50xx; 5480 struct cvmx_gmxx_txx_stat0_s cn52xx; 5481 struct cvmx_gmxx_txx_stat0_s cn52xxp1; 5482 struct cvmx_gmxx_txx_stat0_s cn56xx; 5483 struct cvmx_gmxx_txx_stat0_s cn56xxp1; 5484 struct cvmx_gmxx_txx_stat0_s cn58xx; 5485 struct cvmx_gmxx_txx_stat0_s cn58xxp1; 5486 struct cvmx_gmxx_txx_stat0_s cn61xx; 5487 struct cvmx_gmxx_txx_stat0_s cn63xx; 5488 struct cvmx_gmxx_txx_stat0_s cn63xxp1; 5489 struct cvmx_gmxx_txx_stat0_s cn66xx; 5490 struct cvmx_gmxx_txx_stat0_s cn68xx; 5491 struct cvmx_gmxx_txx_stat0_s cn68xxp1; 5492 struct cvmx_gmxx_txx_stat0_s cnf71xx; 5493}; 5494 5495union cvmx_gmxx_txx_stat1 { 5496 uint64_t u64; 5497 struct cvmx_gmxx_txx_stat1_s { 5498#ifdef __BIG_ENDIAN_BITFIELD 5499 uint64_t scol:32; 5500 uint64_t mcol:32; 5501#else 5502 uint64_t mcol:32; 5503 uint64_t scol:32; 5504#endif 5505 } s; 5506 struct cvmx_gmxx_txx_stat1_s cn30xx; 5507 struct cvmx_gmxx_txx_stat1_s cn31xx; 5508 struct cvmx_gmxx_txx_stat1_s cn38xx; 5509 struct cvmx_gmxx_txx_stat1_s cn38xxp2; 5510 struct cvmx_gmxx_txx_stat1_s cn50xx; 5511 struct cvmx_gmxx_txx_stat1_s cn52xx; 5512 struct cvmx_gmxx_txx_stat1_s cn52xxp1; 5513 struct cvmx_gmxx_txx_stat1_s cn56xx; 5514 struct cvmx_gmxx_txx_stat1_s cn56xxp1; 5515 struct cvmx_gmxx_txx_stat1_s cn58xx; 5516 struct cvmx_gmxx_txx_stat1_s cn58xxp1; 5517 struct cvmx_gmxx_txx_stat1_s cn61xx; 5518 struct cvmx_gmxx_txx_stat1_s cn63xx; 5519 struct cvmx_gmxx_txx_stat1_s cn63xxp1; 5520 struct cvmx_gmxx_txx_stat1_s cn66xx; 5521 struct cvmx_gmxx_txx_stat1_s cn68xx; 5522 struct cvmx_gmxx_txx_stat1_s cn68xxp1; 5523 struct cvmx_gmxx_txx_stat1_s cnf71xx; 5524}; 5525 5526union cvmx_gmxx_txx_stat2 { 5527 uint64_t u64; 5528 struct cvmx_gmxx_txx_stat2_s { 5529#ifdef __BIG_ENDIAN_BITFIELD 5530 uint64_t reserved_48_63:16; 5531 uint64_t octs:48; 5532#else 5533 uint64_t octs:48; 5534 uint64_t reserved_48_63:16; 5535#endif 5536 } s; 5537 struct cvmx_gmxx_txx_stat2_s cn30xx; 5538 struct cvmx_gmxx_txx_stat2_s cn31xx; 5539 struct cvmx_gmxx_txx_stat2_s cn38xx; 5540 struct cvmx_gmxx_txx_stat2_s cn38xxp2; 5541 struct cvmx_gmxx_txx_stat2_s cn50xx; 5542 struct cvmx_gmxx_txx_stat2_s cn52xx; 5543 struct cvmx_gmxx_txx_stat2_s cn52xxp1; 5544 struct cvmx_gmxx_txx_stat2_s cn56xx; 5545 struct cvmx_gmxx_txx_stat2_s cn56xxp1; 5546 struct cvmx_gmxx_txx_stat2_s cn58xx; 5547 struct cvmx_gmxx_txx_stat2_s cn58xxp1; 5548 struct cvmx_gmxx_txx_stat2_s cn61xx; 5549 struct cvmx_gmxx_txx_stat2_s cn63xx; 5550 struct cvmx_gmxx_txx_stat2_s cn63xxp1; 5551 struct cvmx_gmxx_txx_stat2_s cn66xx; 5552 struct cvmx_gmxx_txx_stat2_s cn68xx; 5553 struct cvmx_gmxx_txx_stat2_s cn68xxp1; 5554 struct cvmx_gmxx_txx_stat2_s cnf71xx; 5555}; 5556 5557union cvmx_gmxx_txx_stat3 { 5558 uint64_t u64; 5559 struct cvmx_gmxx_txx_stat3_s { 5560#ifdef __BIG_ENDIAN_BITFIELD 5561 uint64_t reserved_32_63:32; 5562 uint64_t pkts:32; 5563#else 5564 uint64_t pkts:32; 5565 uint64_t reserved_32_63:32; 5566#endif 5567 } s; 5568 struct cvmx_gmxx_txx_stat3_s cn30xx; 5569 struct cvmx_gmxx_txx_stat3_s cn31xx; 5570 struct cvmx_gmxx_txx_stat3_s cn38xx; 5571 struct cvmx_gmxx_txx_stat3_s cn38xxp2; 5572 struct cvmx_gmxx_txx_stat3_s cn50xx; 5573 struct cvmx_gmxx_txx_stat3_s cn52xx; 5574 struct cvmx_gmxx_txx_stat3_s cn52xxp1; 5575 struct cvmx_gmxx_txx_stat3_s cn56xx; 5576 struct cvmx_gmxx_txx_stat3_s cn56xxp1; 5577 struct cvmx_gmxx_txx_stat3_s cn58xx; 5578 struct cvmx_gmxx_txx_stat3_s cn58xxp1; 5579 struct cvmx_gmxx_txx_stat3_s cn61xx; 5580 struct cvmx_gmxx_txx_stat3_s cn63xx; 5581 struct cvmx_gmxx_txx_stat3_s cn63xxp1; 5582 struct cvmx_gmxx_txx_stat3_s cn66xx; 5583 struct cvmx_gmxx_txx_stat3_s cn68xx; 5584 struct cvmx_gmxx_txx_stat3_s cn68xxp1; 5585 struct cvmx_gmxx_txx_stat3_s cnf71xx; 5586}; 5587 5588union cvmx_gmxx_txx_stat4 { 5589 uint64_t u64; 5590 struct cvmx_gmxx_txx_stat4_s { 5591#ifdef __BIG_ENDIAN_BITFIELD 5592 uint64_t hist1:32; 5593 uint64_t hist0:32; 5594#else 5595 uint64_t hist0:32; 5596 uint64_t hist1:32; 5597#endif 5598 } s; 5599 struct cvmx_gmxx_txx_stat4_s cn30xx; 5600 struct cvmx_gmxx_txx_stat4_s cn31xx; 5601 struct cvmx_gmxx_txx_stat4_s cn38xx; 5602 struct cvmx_gmxx_txx_stat4_s cn38xxp2; 5603 struct cvmx_gmxx_txx_stat4_s cn50xx; 5604 struct cvmx_gmxx_txx_stat4_s cn52xx; 5605 struct cvmx_gmxx_txx_stat4_s cn52xxp1; 5606 struct cvmx_gmxx_txx_stat4_s cn56xx; 5607 struct cvmx_gmxx_txx_stat4_s cn56xxp1; 5608 struct cvmx_gmxx_txx_stat4_s cn58xx; 5609 struct cvmx_gmxx_txx_stat4_s cn58xxp1; 5610 struct cvmx_gmxx_txx_stat4_s cn61xx; 5611 struct cvmx_gmxx_txx_stat4_s cn63xx; 5612 struct cvmx_gmxx_txx_stat4_s cn63xxp1; 5613 struct cvmx_gmxx_txx_stat4_s cn66xx; 5614 struct cvmx_gmxx_txx_stat4_s cn68xx; 5615 struct cvmx_gmxx_txx_stat4_s cn68xxp1; 5616 struct cvmx_gmxx_txx_stat4_s cnf71xx; 5617}; 5618 5619union cvmx_gmxx_txx_stat5 { 5620 uint64_t u64; 5621 struct cvmx_gmxx_txx_stat5_s { 5622#ifdef __BIG_ENDIAN_BITFIELD 5623 uint64_t hist3:32; 5624 uint64_t hist2:32; 5625#else 5626 uint64_t hist2:32; 5627 uint64_t hist3:32; 5628#endif 5629 } s; 5630 struct cvmx_gmxx_txx_stat5_s cn30xx; 5631 struct cvmx_gmxx_txx_stat5_s cn31xx; 5632 struct cvmx_gmxx_txx_stat5_s cn38xx; 5633 struct cvmx_gmxx_txx_stat5_s cn38xxp2; 5634 struct cvmx_gmxx_txx_stat5_s cn50xx; 5635 struct cvmx_gmxx_txx_stat5_s cn52xx; 5636 struct cvmx_gmxx_txx_stat5_s cn52xxp1; 5637 struct cvmx_gmxx_txx_stat5_s cn56xx; 5638 struct cvmx_gmxx_txx_stat5_s cn56xxp1; 5639 struct cvmx_gmxx_txx_stat5_s cn58xx; 5640 struct cvmx_gmxx_txx_stat5_s cn58xxp1; 5641 struct cvmx_gmxx_txx_stat5_s cn61xx; 5642 struct cvmx_gmxx_txx_stat5_s cn63xx; 5643 struct cvmx_gmxx_txx_stat5_s cn63xxp1; 5644 struct cvmx_gmxx_txx_stat5_s cn66xx; 5645 struct cvmx_gmxx_txx_stat5_s cn68xx; 5646 struct cvmx_gmxx_txx_stat5_s cn68xxp1; 5647 struct cvmx_gmxx_txx_stat5_s cnf71xx; 5648}; 5649 5650union cvmx_gmxx_txx_stat6 { 5651 uint64_t u64; 5652 struct cvmx_gmxx_txx_stat6_s { 5653#ifdef __BIG_ENDIAN_BITFIELD 5654 uint64_t hist5:32; 5655 uint64_t hist4:32; 5656#else 5657 uint64_t hist4:32; 5658 uint64_t hist5:32; 5659#endif 5660 } s; 5661 struct cvmx_gmxx_txx_stat6_s cn30xx; 5662 struct cvmx_gmxx_txx_stat6_s cn31xx; 5663 struct cvmx_gmxx_txx_stat6_s cn38xx; 5664 struct cvmx_gmxx_txx_stat6_s cn38xxp2; 5665 struct cvmx_gmxx_txx_stat6_s cn50xx; 5666 struct cvmx_gmxx_txx_stat6_s cn52xx; 5667 struct cvmx_gmxx_txx_stat6_s cn52xxp1; 5668 struct cvmx_gmxx_txx_stat6_s cn56xx; 5669 struct cvmx_gmxx_txx_stat6_s cn56xxp1; 5670 struct cvmx_gmxx_txx_stat6_s cn58xx; 5671 struct cvmx_gmxx_txx_stat6_s cn58xxp1; 5672 struct cvmx_gmxx_txx_stat6_s cn61xx; 5673 struct cvmx_gmxx_txx_stat6_s cn63xx; 5674 struct cvmx_gmxx_txx_stat6_s cn63xxp1; 5675 struct cvmx_gmxx_txx_stat6_s cn66xx; 5676 struct cvmx_gmxx_txx_stat6_s cn68xx; 5677 struct cvmx_gmxx_txx_stat6_s cn68xxp1; 5678 struct cvmx_gmxx_txx_stat6_s cnf71xx; 5679}; 5680 5681union cvmx_gmxx_txx_stat7 { 5682 uint64_t u64; 5683 struct cvmx_gmxx_txx_stat7_s { 5684#ifdef __BIG_ENDIAN_BITFIELD 5685 uint64_t hist7:32; 5686 uint64_t hist6:32; 5687#else 5688 uint64_t hist6:32; 5689 uint64_t hist7:32; 5690#endif 5691 } s; 5692 struct cvmx_gmxx_txx_stat7_s cn30xx; 5693 struct cvmx_gmxx_txx_stat7_s cn31xx; 5694 struct cvmx_gmxx_txx_stat7_s cn38xx; 5695 struct cvmx_gmxx_txx_stat7_s cn38xxp2; 5696 struct cvmx_gmxx_txx_stat7_s cn50xx; 5697 struct cvmx_gmxx_txx_stat7_s cn52xx; 5698 struct cvmx_gmxx_txx_stat7_s cn52xxp1; 5699 struct cvmx_gmxx_txx_stat7_s cn56xx; 5700 struct cvmx_gmxx_txx_stat7_s cn56xxp1; 5701 struct cvmx_gmxx_txx_stat7_s cn58xx; 5702 struct cvmx_gmxx_txx_stat7_s cn58xxp1; 5703 struct cvmx_gmxx_txx_stat7_s cn61xx; 5704 struct cvmx_gmxx_txx_stat7_s cn63xx; 5705 struct cvmx_gmxx_txx_stat7_s cn63xxp1; 5706 struct cvmx_gmxx_txx_stat7_s cn66xx; 5707 struct cvmx_gmxx_txx_stat7_s cn68xx; 5708 struct cvmx_gmxx_txx_stat7_s cn68xxp1; 5709 struct cvmx_gmxx_txx_stat7_s cnf71xx; 5710}; 5711 5712union cvmx_gmxx_txx_stat8 { 5713 uint64_t u64; 5714 struct cvmx_gmxx_txx_stat8_s { 5715#ifdef __BIG_ENDIAN_BITFIELD 5716 uint64_t mcst:32; 5717 uint64_t bcst:32; 5718#else 5719 uint64_t bcst:32; 5720 uint64_t mcst:32; 5721#endif 5722 } s; 5723 struct cvmx_gmxx_txx_stat8_s cn30xx; 5724 struct cvmx_gmxx_txx_stat8_s cn31xx; 5725 struct cvmx_gmxx_txx_stat8_s cn38xx; 5726 struct cvmx_gmxx_txx_stat8_s cn38xxp2; 5727 struct cvmx_gmxx_txx_stat8_s cn50xx; 5728 struct cvmx_gmxx_txx_stat8_s cn52xx; 5729 struct cvmx_gmxx_txx_stat8_s cn52xxp1; 5730 struct cvmx_gmxx_txx_stat8_s cn56xx; 5731 struct cvmx_gmxx_txx_stat8_s cn56xxp1; 5732 struct cvmx_gmxx_txx_stat8_s cn58xx; 5733 struct cvmx_gmxx_txx_stat8_s cn58xxp1; 5734 struct cvmx_gmxx_txx_stat8_s cn61xx; 5735 struct cvmx_gmxx_txx_stat8_s cn63xx; 5736 struct cvmx_gmxx_txx_stat8_s cn63xxp1; 5737 struct cvmx_gmxx_txx_stat8_s cn66xx; 5738 struct cvmx_gmxx_txx_stat8_s cn68xx; 5739 struct cvmx_gmxx_txx_stat8_s cn68xxp1; 5740 struct cvmx_gmxx_txx_stat8_s cnf71xx; 5741}; 5742 5743union cvmx_gmxx_txx_stat9 { 5744 uint64_t u64; 5745 struct cvmx_gmxx_txx_stat9_s { 5746#ifdef __BIG_ENDIAN_BITFIELD 5747 uint64_t undflw:32; 5748 uint64_t ctl:32; 5749#else 5750 uint64_t ctl:32; 5751 uint64_t undflw:32; 5752#endif 5753 } s; 5754 struct cvmx_gmxx_txx_stat9_s cn30xx; 5755 struct cvmx_gmxx_txx_stat9_s cn31xx; 5756 struct cvmx_gmxx_txx_stat9_s cn38xx; 5757 struct cvmx_gmxx_txx_stat9_s cn38xxp2; 5758 struct cvmx_gmxx_txx_stat9_s cn50xx; 5759 struct cvmx_gmxx_txx_stat9_s cn52xx; 5760 struct cvmx_gmxx_txx_stat9_s cn52xxp1; 5761 struct cvmx_gmxx_txx_stat9_s cn56xx; 5762 struct cvmx_gmxx_txx_stat9_s cn56xxp1; 5763 struct cvmx_gmxx_txx_stat9_s cn58xx; 5764 struct cvmx_gmxx_txx_stat9_s cn58xxp1; 5765 struct cvmx_gmxx_txx_stat9_s cn61xx; 5766 struct cvmx_gmxx_txx_stat9_s cn63xx; 5767 struct cvmx_gmxx_txx_stat9_s cn63xxp1; 5768 struct cvmx_gmxx_txx_stat9_s cn66xx; 5769 struct cvmx_gmxx_txx_stat9_s cn68xx; 5770 struct cvmx_gmxx_txx_stat9_s cn68xxp1; 5771 struct cvmx_gmxx_txx_stat9_s cnf71xx; 5772}; 5773 5774union cvmx_gmxx_txx_stats_ctl { 5775 uint64_t u64; 5776 struct cvmx_gmxx_txx_stats_ctl_s { 5777#ifdef __BIG_ENDIAN_BITFIELD 5778 uint64_t reserved_1_63:63; 5779 uint64_t rd_clr:1; 5780#else 5781 uint64_t rd_clr:1; 5782 uint64_t reserved_1_63:63; 5783#endif 5784 } s; 5785 struct cvmx_gmxx_txx_stats_ctl_s cn30xx; 5786 struct cvmx_gmxx_txx_stats_ctl_s cn31xx; 5787 struct cvmx_gmxx_txx_stats_ctl_s cn38xx; 5788 struct cvmx_gmxx_txx_stats_ctl_s cn38xxp2; 5789 struct cvmx_gmxx_txx_stats_ctl_s cn50xx; 5790 struct cvmx_gmxx_txx_stats_ctl_s cn52xx; 5791 struct cvmx_gmxx_txx_stats_ctl_s cn52xxp1; 5792 struct cvmx_gmxx_txx_stats_ctl_s cn56xx; 5793 struct cvmx_gmxx_txx_stats_ctl_s cn56xxp1; 5794 struct cvmx_gmxx_txx_stats_ctl_s cn58xx; 5795 struct cvmx_gmxx_txx_stats_ctl_s cn58xxp1; 5796 struct cvmx_gmxx_txx_stats_ctl_s cn61xx; 5797 struct cvmx_gmxx_txx_stats_ctl_s cn63xx; 5798 struct cvmx_gmxx_txx_stats_ctl_s cn63xxp1; 5799 struct cvmx_gmxx_txx_stats_ctl_s cn66xx; 5800 struct cvmx_gmxx_txx_stats_ctl_s cn68xx; 5801 struct cvmx_gmxx_txx_stats_ctl_s cn68xxp1; 5802 struct cvmx_gmxx_txx_stats_ctl_s cnf71xx; 5803}; 5804 5805union cvmx_gmxx_txx_thresh { 5806 uint64_t u64; 5807 struct cvmx_gmxx_txx_thresh_s { 5808#ifdef __BIG_ENDIAN_BITFIELD 5809 uint64_t reserved_10_63:54; 5810 uint64_t cnt:10; 5811#else 5812 uint64_t cnt:10; 5813 uint64_t reserved_10_63:54; 5814#endif 5815 } s; 5816 struct cvmx_gmxx_txx_thresh_cn30xx { 5817#ifdef __BIG_ENDIAN_BITFIELD 5818 uint64_t reserved_7_63:57; 5819 uint64_t cnt:7; 5820#else 5821 uint64_t cnt:7; 5822 uint64_t reserved_7_63:57; 5823#endif 5824 } cn30xx; 5825 struct cvmx_gmxx_txx_thresh_cn30xx cn31xx; 5826 struct cvmx_gmxx_txx_thresh_cn38xx { 5827#ifdef __BIG_ENDIAN_BITFIELD 5828 uint64_t reserved_9_63:55; 5829 uint64_t cnt:9; 5830#else 5831 uint64_t cnt:9; 5832 uint64_t reserved_9_63:55; 5833#endif 5834 } cn38xx; 5835 struct cvmx_gmxx_txx_thresh_cn38xx cn38xxp2; 5836 struct cvmx_gmxx_txx_thresh_cn30xx cn50xx; 5837 struct cvmx_gmxx_txx_thresh_cn38xx cn52xx; 5838 struct cvmx_gmxx_txx_thresh_cn38xx cn52xxp1; 5839 struct cvmx_gmxx_txx_thresh_cn38xx cn56xx; 5840 struct cvmx_gmxx_txx_thresh_cn38xx cn56xxp1; 5841 struct cvmx_gmxx_txx_thresh_cn38xx cn58xx; 5842 struct cvmx_gmxx_txx_thresh_cn38xx cn58xxp1; 5843 struct cvmx_gmxx_txx_thresh_cn38xx cn61xx; 5844 struct cvmx_gmxx_txx_thresh_cn38xx cn63xx; 5845 struct cvmx_gmxx_txx_thresh_cn38xx cn63xxp1; 5846 struct cvmx_gmxx_txx_thresh_cn38xx cn66xx; 5847 struct cvmx_gmxx_txx_thresh_s cn68xx; 5848 struct cvmx_gmxx_txx_thresh_s cn68xxp1; 5849 struct cvmx_gmxx_txx_thresh_cn38xx cnf71xx; 5850}; 5851 5852union cvmx_gmxx_tx_bp { 5853 uint64_t u64; 5854 struct cvmx_gmxx_tx_bp_s { 5855#ifdef __BIG_ENDIAN_BITFIELD 5856 uint64_t reserved_4_63:60; 5857 uint64_t bp:4; 5858#else 5859 uint64_t bp:4; 5860 uint64_t reserved_4_63:60; 5861#endif 5862 } s; 5863 struct cvmx_gmxx_tx_bp_cn30xx { 5864#ifdef __BIG_ENDIAN_BITFIELD 5865 uint64_t reserved_3_63:61; 5866 uint64_t bp:3; 5867#else 5868 uint64_t bp:3; 5869 uint64_t reserved_3_63:61; 5870#endif 5871 } cn30xx; 5872 struct cvmx_gmxx_tx_bp_cn30xx cn31xx; 5873 struct cvmx_gmxx_tx_bp_s cn38xx; 5874 struct cvmx_gmxx_tx_bp_s cn38xxp2; 5875 struct cvmx_gmxx_tx_bp_cn30xx cn50xx; 5876 struct cvmx_gmxx_tx_bp_s cn52xx; 5877 struct cvmx_gmxx_tx_bp_s cn52xxp1; 5878 struct cvmx_gmxx_tx_bp_s cn56xx; 5879 struct cvmx_gmxx_tx_bp_s cn56xxp1; 5880 struct cvmx_gmxx_tx_bp_s cn58xx; 5881 struct cvmx_gmxx_tx_bp_s cn58xxp1; 5882 struct cvmx_gmxx_tx_bp_s cn61xx; 5883 struct cvmx_gmxx_tx_bp_s cn63xx; 5884 struct cvmx_gmxx_tx_bp_s cn63xxp1; 5885 struct cvmx_gmxx_tx_bp_s cn66xx; 5886 struct cvmx_gmxx_tx_bp_s cn68xx; 5887 struct cvmx_gmxx_tx_bp_s cn68xxp1; 5888 struct cvmx_gmxx_tx_bp_cnf71xx { 5889#ifdef __BIG_ENDIAN_BITFIELD 5890 uint64_t reserved_2_63:62; 5891 uint64_t bp:2; 5892#else 5893 uint64_t bp:2; 5894 uint64_t reserved_2_63:62; 5895#endif 5896 } cnf71xx; 5897}; 5898 5899union cvmx_gmxx_tx_clk_mskx { 5900 uint64_t u64; 5901 struct cvmx_gmxx_tx_clk_mskx_s { 5902#ifdef __BIG_ENDIAN_BITFIELD 5903 uint64_t reserved_1_63:63; 5904 uint64_t msk:1; 5905#else 5906 uint64_t msk:1; 5907 uint64_t reserved_1_63:63; 5908#endif 5909 } s; 5910 struct cvmx_gmxx_tx_clk_mskx_s cn30xx; 5911 struct cvmx_gmxx_tx_clk_mskx_s cn50xx; 5912}; 5913 5914union cvmx_gmxx_tx_col_attempt { 5915 uint64_t u64; 5916 struct cvmx_gmxx_tx_col_attempt_s { 5917#ifdef __BIG_ENDIAN_BITFIELD 5918 uint64_t reserved_5_63:59; 5919 uint64_t limit:5; 5920#else 5921 uint64_t limit:5; 5922 uint64_t reserved_5_63:59; 5923#endif 5924 } s; 5925 struct cvmx_gmxx_tx_col_attempt_s cn30xx; 5926 struct cvmx_gmxx_tx_col_attempt_s cn31xx; 5927 struct cvmx_gmxx_tx_col_attempt_s cn38xx; 5928 struct cvmx_gmxx_tx_col_attempt_s cn38xxp2; 5929 struct cvmx_gmxx_tx_col_attempt_s cn50xx; 5930 struct cvmx_gmxx_tx_col_attempt_s cn52xx; 5931 struct cvmx_gmxx_tx_col_attempt_s cn52xxp1; 5932 struct cvmx_gmxx_tx_col_attempt_s cn56xx; 5933 struct cvmx_gmxx_tx_col_attempt_s cn56xxp1; 5934 struct cvmx_gmxx_tx_col_attempt_s cn58xx; 5935 struct cvmx_gmxx_tx_col_attempt_s cn58xxp1; 5936 struct cvmx_gmxx_tx_col_attempt_s cn61xx; 5937 struct cvmx_gmxx_tx_col_attempt_s cn63xx; 5938 struct cvmx_gmxx_tx_col_attempt_s cn63xxp1; 5939 struct cvmx_gmxx_tx_col_attempt_s cn66xx; 5940 struct cvmx_gmxx_tx_col_attempt_s cn68xx; 5941 struct cvmx_gmxx_tx_col_attempt_s cn68xxp1; 5942 struct cvmx_gmxx_tx_col_attempt_s cnf71xx; 5943}; 5944 5945union cvmx_gmxx_tx_corrupt { 5946 uint64_t u64; 5947 struct cvmx_gmxx_tx_corrupt_s { 5948#ifdef __BIG_ENDIAN_BITFIELD 5949 uint64_t reserved_4_63:60; 5950 uint64_t corrupt:4; 5951#else 5952 uint64_t corrupt:4; 5953 uint64_t reserved_4_63:60; 5954#endif 5955 } s; 5956 struct cvmx_gmxx_tx_corrupt_cn30xx { 5957#ifdef __BIG_ENDIAN_BITFIELD 5958 uint64_t reserved_3_63:61; 5959 uint64_t corrupt:3; 5960#else 5961 uint64_t corrupt:3; 5962 uint64_t reserved_3_63:61; 5963#endif 5964 } cn30xx; 5965 struct cvmx_gmxx_tx_corrupt_cn30xx cn31xx; 5966 struct cvmx_gmxx_tx_corrupt_s cn38xx; 5967 struct cvmx_gmxx_tx_corrupt_s cn38xxp2; 5968 struct cvmx_gmxx_tx_corrupt_cn30xx cn50xx; 5969 struct cvmx_gmxx_tx_corrupt_s cn52xx; 5970 struct cvmx_gmxx_tx_corrupt_s cn52xxp1; 5971 struct cvmx_gmxx_tx_corrupt_s cn56xx; 5972 struct cvmx_gmxx_tx_corrupt_s cn56xxp1; 5973 struct cvmx_gmxx_tx_corrupt_s cn58xx; 5974 struct cvmx_gmxx_tx_corrupt_s cn58xxp1; 5975 struct cvmx_gmxx_tx_corrupt_s cn61xx; 5976 struct cvmx_gmxx_tx_corrupt_s cn63xx; 5977 struct cvmx_gmxx_tx_corrupt_s cn63xxp1; 5978 struct cvmx_gmxx_tx_corrupt_s cn66xx; 5979 struct cvmx_gmxx_tx_corrupt_s cn68xx; 5980 struct cvmx_gmxx_tx_corrupt_s cn68xxp1; 5981 struct cvmx_gmxx_tx_corrupt_cnf71xx { 5982#ifdef __BIG_ENDIAN_BITFIELD 5983 uint64_t reserved_2_63:62; 5984 uint64_t corrupt:2; 5985#else 5986 uint64_t corrupt:2; 5987 uint64_t reserved_2_63:62; 5988#endif 5989 } cnf71xx; 5990}; 5991 5992union cvmx_gmxx_tx_hg2_reg1 { 5993 uint64_t u64; 5994 struct cvmx_gmxx_tx_hg2_reg1_s { 5995#ifdef __BIG_ENDIAN_BITFIELD 5996 uint64_t reserved_16_63:48; 5997 uint64_t tx_xof:16; 5998#else 5999 uint64_t tx_xof:16; 6000 uint64_t reserved_16_63:48; 6001#endif 6002 } s; 6003 struct cvmx_gmxx_tx_hg2_reg1_s cn52xx; 6004 struct cvmx_gmxx_tx_hg2_reg1_s cn52xxp1; 6005 struct cvmx_gmxx_tx_hg2_reg1_s cn56xx; 6006 struct cvmx_gmxx_tx_hg2_reg1_s cn61xx; 6007 struct cvmx_gmxx_tx_hg2_reg1_s cn63xx; 6008 struct cvmx_gmxx_tx_hg2_reg1_s cn63xxp1; 6009 struct cvmx_gmxx_tx_hg2_reg1_s cn66xx; 6010 struct cvmx_gmxx_tx_hg2_reg1_s cn68xx; 6011 struct cvmx_gmxx_tx_hg2_reg1_s cn68xxp1; 6012 struct cvmx_gmxx_tx_hg2_reg1_s cnf71xx; 6013}; 6014 6015union cvmx_gmxx_tx_hg2_reg2 { 6016 uint64_t u64; 6017 struct cvmx_gmxx_tx_hg2_reg2_s { 6018#ifdef __BIG_ENDIAN_BITFIELD 6019 uint64_t reserved_16_63:48; 6020 uint64_t tx_xon:16; 6021#else 6022 uint64_t tx_xon:16; 6023 uint64_t reserved_16_63:48; 6024#endif 6025 } s; 6026 struct cvmx_gmxx_tx_hg2_reg2_s cn52xx; 6027 struct cvmx_gmxx_tx_hg2_reg2_s cn52xxp1; 6028 struct cvmx_gmxx_tx_hg2_reg2_s cn56xx; 6029 struct cvmx_gmxx_tx_hg2_reg2_s cn61xx; 6030 struct cvmx_gmxx_tx_hg2_reg2_s cn63xx; 6031 struct cvmx_gmxx_tx_hg2_reg2_s cn63xxp1; 6032 struct cvmx_gmxx_tx_hg2_reg2_s cn66xx; 6033 struct cvmx_gmxx_tx_hg2_reg2_s cn68xx; 6034 struct cvmx_gmxx_tx_hg2_reg2_s cn68xxp1; 6035 struct cvmx_gmxx_tx_hg2_reg2_s cnf71xx; 6036}; 6037 6038union cvmx_gmxx_tx_ifg { 6039 uint64_t u64; 6040 struct cvmx_gmxx_tx_ifg_s { 6041#ifdef __BIG_ENDIAN_BITFIELD 6042 uint64_t reserved_8_63:56; 6043 uint64_t ifg2:4; 6044 uint64_t ifg1:4; 6045#else 6046 uint64_t ifg1:4; 6047 uint64_t ifg2:4; 6048 uint64_t reserved_8_63:56; 6049#endif 6050 } s; 6051 struct cvmx_gmxx_tx_ifg_s cn30xx; 6052 struct cvmx_gmxx_tx_ifg_s cn31xx; 6053 struct cvmx_gmxx_tx_ifg_s cn38xx; 6054 struct cvmx_gmxx_tx_ifg_s cn38xxp2; 6055 struct cvmx_gmxx_tx_ifg_s cn50xx; 6056 struct cvmx_gmxx_tx_ifg_s cn52xx; 6057 struct cvmx_gmxx_tx_ifg_s cn52xxp1; 6058 struct cvmx_gmxx_tx_ifg_s cn56xx; 6059 struct cvmx_gmxx_tx_ifg_s cn56xxp1; 6060 struct cvmx_gmxx_tx_ifg_s cn58xx; 6061 struct cvmx_gmxx_tx_ifg_s cn58xxp1; 6062 struct cvmx_gmxx_tx_ifg_s cn61xx; 6063 struct cvmx_gmxx_tx_ifg_s cn63xx; 6064 struct cvmx_gmxx_tx_ifg_s cn63xxp1; 6065 struct cvmx_gmxx_tx_ifg_s cn66xx; 6066 struct cvmx_gmxx_tx_ifg_s cn68xx; 6067 struct cvmx_gmxx_tx_ifg_s cn68xxp1; 6068 struct cvmx_gmxx_tx_ifg_s cnf71xx; 6069}; 6070 6071union cvmx_gmxx_tx_int_en { 6072 uint64_t u64; 6073 struct cvmx_gmxx_tx_int_en_s { 6074#ifdef __BIG_ENDIAN_BITFIELD 6075 uint64_t reserved_25_63:39; 6076 uint64_t xchange:1; 6077 uint64_t ptp_lost:4; 6078 uint64_t late_col:4; 6079 uint64_t xsdef:4; 6080 uint64_t xscol:4; 6081 uint64_t reserved_6_7:2; 6082 uint64_t undflw:4; 6083 uint64_t reserved_1_1:1; 6084 uint64_t pko_nxa:1; 6085#else 6086 uint64_t pko_nxa:1; 6087 uint64_t reserved_1_1:1; 6088 uint64_t undflw:4; 6089 uint64_t reserved_6_7:2; 6090 uint64_t xscol:4; 6091 uint64_t xsdef:4; 6092 uint64_t late_col:4; 6093 uint64_t ptp_lost:4; 6094 uint64_t xchange:1; 6095 uint64_t reserved_25_63:39; 6096#endif 6097 } s; 6098 struct cvmx_gmxx_tx_int_en_cn30xx { 6099#ifdef __BIG_ENDIAN_BITFIELD 6100 uint64_t reserved_19_63:45; 6101 uint64_t late_col:3; 6102 uint64_t reserved_15_15:1; 6103 uint64_t xsdef:3; 6104 uint64_t reserved_11_11:1; 6105 uint64_t xscol:3; 6106 uint64_t reserved_5_7:3; 6107 uint64_t undflw:3; 6108 uint64_t reserved_1_1:1; 6109 uint64_t pko_nxa:1; 6110#else 6111 uint64_t pko_nxa:1; 6112 uint64_t reserved_1_1:1; 6113 uint64_t undflw:3; 6114 uint64_t reserved_5_7:3; 6115 uint64_t xscol:3; 6116 uint64_t reserved_11_11:1; 6117 uint64_t xsdef:3; 6118 uint64_t reserved_15_15:1; 6119 uint64_t late_col:3; 6120 uint64_t reserved_19_63:45; 6121#endif 6122 } cn30xx; 6123 struct cvmx_gmxx_tx_int_en_cn31xx { 6124#ifdef __BIG_ENDIAN_BITFIELD 6125 uint64_t reserved_15_63:49; 6126 uint64_t xsdef:3; 6127 uint64_t reserved_11_11:1; 6128 uint64_t xscol:3; 6129 uint64_t reserved_5_7:3; 6130 uint64_t undflw:3; 6131 uint64_t reserved_1_1:1; 6132 uint64_t pko_nxa:1; 6133#else 6134 uint64_t pko_nxa:1; 6135 uint64_t reserved_1_1:1; 6136 uint64_t undflw:3; 6137 uint64_t reserved_5_7:3; 6138 uint64_t xscol:3; 6139 uint64_t reserved_11_11:1; 6140 uint64_t xsdef:3; 6141 uint64_t reserved_15_63:49; 6142#endif 6143 } cn31xx; 6144 struct cvmx_gmxx_tx_int_en_cn38xx { 6145#ifdef __BIG_ENDIAN_BITFIELD 6146 uint64_t reserved_20_63:44; 6147 uint64_t late_col:4; 6148 uint64_t xsdef:4; 6149 uint64_t xscol:4; 6150 uint64_t reserved_6_7:2; 6151 uint64_t undflw:4; 6152 uint64_t ncb_nxa:1; 6153 uint64_t pko_nxa:1; 6154#else 6155 uint64_t pko_nxa:1; 6156 uint64_t ncb_nxa:1; 6157 uint64_t undflw:4; 6158 uint64_t reserved_6_7:2; 6159 uint64_t xscol:4; 6160 uint64_t xsdef:4; 6161 uint64_t late_col:4; 6162 uint64_t reserved_20_63:44; 6163#endif 6164 } cn38xx; 6165 struct cvmx_gmxx_tx_int_en_cn38xxp2 { 6166#ifdef __BIG_ENDIAN_BITFIELD 6167 uint64_t reserved_16_63:48; 6168 uint64_t xsdef:4; 6169 uint64_t xscol:4; 6170 uint64_t reserved_6_7:2; 6171 uint64_t undflw:4; 6172 uint64_t ncb_nxa:1; 6173 uint64_t pko_nxa:1; 6174#else 6175 uint64_t pko_nxa:1; 6176 uint64_t ncb_nxa:1; 6177 uint64_t undflw:4; 6178 uint64_t reserved_6_7:2; 6179 uint64_t xscol:4; 6180 uint64_t xsdef:4; 6181 uint64_t reserved_16_63:48; 6182#endif 6183 } cn38xxp2; 6184 struct cvmx_gmxx_tx_int_en_cn30xx cn50xx; 6185 struct cvmx_gmxx_tx_int_en_cn52xx { 6186#ifdef __BIG_ENDIAN_BITFIELD 6187 uint64_t reserved_20_63:44; 6188 uint64_t late_col:4; 6189 uint64_t xsdef:4; 6190 uint64_t xscol:4; 6191 uint64_t reserved_6_7:2; 6192 uint64_t undflw:4; 6193 uint64_t reserved_1_1:1; 6194 uint64_t pko_nxa:1; 6195#else 6196 uint64_t pko_nxa:1; 6197 uint64_t reserved_1_1:1; 6198 uint64_t undflw:4; 6199 uint64_t reserved_6_7:2; 6200 uint64_t xscol:4; 6201 uint64_t xsdef:4; 6202 uint64_t late_col:4; 6203 uint64_t reserved_20_63:44; 6204#endif 6205 } cn52xx; 6206 struct cvmx_gmxx_tx_int_en_cn52xx cn52xxp1; 6207 struct cvmx_gmxx_tx_int_en_cn52xx cn56xx; 6208 struct cvmx_gmxx_tx_int_en_cn52xx cn56xxp1; 6209 struct cvmx_gmxx_tx_int_en_cn38xx cn58xx; 6210 struct cvmx_gmxx_tx_int_en_cn38xx cn58xxp1; 6211 struct cvmx_gmxx_tx_int_en_s cn61xx; 6212 struct cvmx_gmxx_tx_int_en_cn63xx { 6213#ifdef __BIG_ENDIAN_BITFIELD 6214 uint64_t reserved_24_63:40; 6215 uint64_t ptp_lost:4; 6216 uint64_t late_col:4; 6217 uint64_t xsdef:4; 6218 uint64_t xscol:4; 6219 uint64_t reserved_6_7:2; 6220 uint64_t undflw:4; 6221 uint64_t reserved_1_1:1; 6222 uint64_t pko_nxa:1; 6223#else 6224 uint64_t pko_nxa:1; 6225 uint64_t reserved_1_1:1; 6226 uint64_t undflw:4; 6227 uint64_t reserved_6_7:2; 6228 uint64_t xscol:4; 6229 uint64_t xsdef:4; 6230 uint64_t late_col:4; 6231 uint64_t ptp_lost:4; 6232 uint64_t reserved_24_63:40; 6233#endif 6234 } cn63xx; 6235 struct cvmx_gmxx_tx_int_en_cn63xx cn63xxp1; 6236 struct cvmx_gmxx_tx_int_en_s cn66xx; 6237 struct cvmx_gmxx_tx_int_en_cn68xx { 6238#ifdef __BIG_ENDIAN_BITFIELD 6239 uint64_t reserved_25_63:39; 6240 uint64_t xchange:1; 6241 uint64_t ptp_lost:4; 6242 uint64_t late_col:4; 6243 uint64_t xsdef:4; 6244 uint64_t xscol:4; 6245 uint64_t reserved_6_7:2; 6246 uint64_t undflw:4; 6247 uint64_t pko_nxp:1; 6248 uint64_t pko_nxa:1; 6249#else 6250 uint64_t pko_nxa:1; 6251 uint64_t pko_nxp:1; 6252 uint64_t undflw:4; 6253 uint64_t reserved_6_7:2; 6254 uint64_t xscol:4; 6255 uint64_t xsdef:4; 6256 uint64_t late_col:4; 6257 uint64_t ptp_lost:4; 6258 uint64_t xchange:1; 6259 uint64_t reserved_25_63:39; 6260#endif 6261 } cn68xx; 6262 struct cvmx_gmxx_tx_int_en_cn68xx cn68xxp1; 6263 struct cvmx_gmxx_tx_int_en_cnf71xx { 6264#ifdef __BIG_ENDIAN_BITFIELD 6265 uint64_t reserved_25_63:39; 6266 uint64_t xchange:1; 6267 uint64_t reserved_22_23:2; 6268 uint64_t ptp_lost:2; 6269 uint64_t reserved_18_19:2; 6270 uint64_t late_col:2; 6271 uint64_t reserved_14_15:2; 6272 uint64_t xsdef:2; 6273 uint64_t reserved_10_11:2; 6274 uint64_t xscol:2; 6275 uint64_t reserved_4_7:4; 6276 uint64_t undflw:2; 6277 uint64_t reserved_1_1:1; 6278 uint64_t pko_nxa:1; 6279#else 6280 uint64_t pko_nxa:1; 6281 uint64_t reserved_1_1:1; 6282 uint64_t undflw:2; 6283 uint64_t reserved_4_7:4; 6284 uint64_t xscol:2; 6285 uint64_t reserved_10_11:2; 6286 uint64_t xsdef:2; 6287 uint64_t reserved_14_15:2; 6288 uint64_t late_col:2; 6289 uint64_t reserved_18_19:2; 6290 uint64_t ptp_lost:2; 6291 uint64_t reserved_22_23:2; 6292 uint64_t xchange:1; 6293 uint64_t reserved_25_63:39; 6294#endif 6295 } cnf71xx; 6296}; 6297 6298union cvmx_gmxx_tx_int_reg { 6299 uint64_t u64; 6300 struct cvmx_gmxx_tx_int_reg_s { 6301#ifdef __BIG_ENDIAN_BITFIELD 6302 uint64_t reserved_25_63:39; 6303 uint64_t xchange:1; 6304 uint64_t ptp_lost:4; 6305 uint64_t late_col:4; 6306 uint64_t xsdef:4; 6307 uint64_t xscol:4; 6308 uint64_t reserved_6_7:2; 6309 uint64_t undflw:4; 6310 uint64_t reserved_1_1:1; 6311 uint64_t pko_nxa:1; 6312#else 6313 uint64_t pko_nxa:1; 6314 uint64_t reserved_1_1:1; 6315 uint64_t undflw:4; 6316 uint64_t reserved_6_7:2; 6317 uint64_t xscol:4; 6318 uint64_t xsdef:4; 6319 uint64_t late_col:4; 6320 uint64_t ptp_lost:4; 6321 uint64_t xchange:1; 6322 uint64_t reserved_25_63:39; 6323#endif 6324 } s; 6325 struct cvmx_gmxx_tx_int_reg_cn30xx { 6326#ifdef __BIG_ENDIAN_BITFIELD 6327 uint64_t reserved_19_63:45; 6328 uint64_t late_col:3; 6329 uint64_t reserved_15_15:1; 6330 uint64_t xsdef:3; 6331 uint64_t reserved_11_11:1; 6332 uint64_t xscol:3; 6333 uint64_t reserved_5_7:3; 6334 uint64_t undflw:3; 6335 uint64_t reserved_1_1:1; 6336 uint64_t pko_nxa:1; 6337#else 6338 uint64_t pko_nxa:1; 6339 uint64_t reserved_1_1:1; 6340 uint64_t undflw:3; 6341 uint64_t reserved_5_7:3; 6342 uint64_t xscol:3; 6343 uint64_t reserved_11_11:1; 6344 uint64_t xsdef:3; 6345 uint64_t reserved_15_15:1; 6346 uint64_t late_col:3; 6347 uint64_t reserved_19_63:45; 6348#endif 6349 } cn30xx; 6350 struct cvmx_gmxx_tx_int_reg_cn31xx { 6351#ifdef __BIG_ENDIAN_BITFIELD 6352 uint64_t reserved_15_63:49; 6353 uint64_t xsdef:3; 6354 uint64_t reserved_11_11:1; 6355 uint64_t xscol:3; 6356 uint64_t reserved_5_7:3; 6357 uint64_t undflw:3; 6358 uint64_t reserved_1_1:1; 6359 uint64_t pko_nxa:1; 6360#else 6361 uint64_t pko_nxa:1; 6362 uint64_t reserved_1_1:1; 6363 uint64_t undflw:3; 6364 uint64_t reserved_5_7:3; 6365 uint64_t xscol:3; 6366 uint64_t reserved_11_11:1; 6367 uint64_t xsdef:3; 6368 uint64_t reserved_15_63:49; 6369#endif 6370 } cn31xx; 6371 struct cvmx_gmxx_tx_int_reg_cn38xx { 6372#ifdef __BIG_ENDIAN_BITFIELD 6373 uint64_t reserved_20_63:44; 6374 uint64_t late_col:4; 6375 uint64_t xsdef:4; 6376 uint64_t xscol:4; 6377 uint64_t reserved_6_7:2; 6378 uint64_t undflw:4; 6379 uint64_t ncb_nxa:1; 6380 uint64_t pko_nxa:1; 6381#else 6382 uint64_t pko_nxa:1; 6383 uint64_t ncb_nxa:1; 6384 uint64_t undflw:4; 6385 uint64_t reserved_6_7:2; 6386 uint64_t xscol:4; 6387 uint64_t xsdef:4; 6388 uint64_t late_col:4; 6389 uint64_t reserved_20_63:44; 6390#endif 6391 } cn38xx; 6392 struct cvmx_gmxx_tx_int_reg_cn38xxp2 { 6393#ifdef __BIG_ENDIAN_BITFIELD 6394 uint64_t reserved_16_63:48; 6395 uint64_t xsdef:4; 6396 uint64_t xscol:4; 6397 uint64_t reserved_6_7:2; 6398 uint64_t undflw:4; 6399 uint64_t ncb_nxa:1; 6400 uint64_t pko_nxa:1; 6401#else 6402 uint64_t pko_nxa:1; 6403 uint64_t ncb_nxa:1; 6404 uint64_t undflw:4; 6405 uint64_t reserved_6_7:2; 6406 uint64_t xscol:4; 6407 uint64_t xsdef:4; 6408 uint64_t reserved_16_63:48; 6409#endif 6410 } cn38xxp2; 6411 struct cvmx_gmxx_tx_int_reg_cn30xx cn50xx; 6412 struct cvmx_gmxx_tx_int_reg_cn52xx { 6413#ifdef __BIG_ENDIAN_BITFIELD 6414 uint64_t reserved_20_63:44; 6415 uint64_t late_col:4; 6416 uint64_t xsdef:4; 6417 uint64_t xscol:4; 6418 uint64_t reserved_6_7:2; 6419 uint64_t undflw:4; 6420 uint64_t reserved_1_1:1; 6421 uint64_t pko_nxa:1; 6422#else 6423 uint64_t pko_nxa:1; 6424 uint64_t reserved_1_1:1; 6425 uint64_t undflw:4; 6426 uint64_t reserved_6_7:2; 6427 uint64_t xscol:4; 6428 uint64_t xsdef:4; 6429 uint64_t late_col:4; 6430 uint64_t reserved_20_63:44; 6431#endif 6432 } cn52xx; 6433 struct cvmx_gmxx_tx_int_reg_cn52xx cn52xxp1; 6434 struct cvmx_gmxx_tx_int_reg_cn52xx cn56xx; 6435 struct cvmx_gmxx_tx_int_reg_cn52xx cn56xxp1; 6436 struct cvmx_gmxx_tx_int_reg_cn38xx cn58xx; 6437 struct cvmx_gmxx_tx_int_reg_cn38xx cn58xxp1; 6438 struct cvmx_gmxx_tx_int_reg_s cn61xx; 6439 struct cvmx_gmxx_tx_int_reg_cn63xx { 6440#ifdef __BIG_ENDIAN_BITFIELD 6441 uint64_t reserved_24_63:40; 6442 uint64_t ptp_lost:4; 6443 uint64_t late_col:4; 6444 uint64_t xsdef:4; 6445 uint64_t xscol:4; 6446 uint64_t reserved_6_7:2; 6447 uint64_t undflw:4; 6448 uint64_t reserved_1_1:1; 6449 uint64_t pko_nxa:1; 6450#else 6451 uint64_t pko_nxa:1; 6452 uint64_t reserved_1_1:1; 6453 uint64_t undflw:4; 6454 uint64_t reserved_6_7:2; 6455 uint64_t xscol:4; 6456 uint64_t xsdef:4; 6457 uint64_t late_col:4; 6458 uint64_t ptp_lost:4; 6459 uint64_t reserved_24_63:40; 6460#endif 6461 } cn63xx; 6462 struct cvmx_gmxx_tx_int_reg_cn63xx cn63xxp1; 6463 struct cvmx_gmxx_tx_int_reg_s cn66xx; 6464 struct cvmx_gmxx_tx_int_reg_cn68xx { 6465#ifdef __BIG_ENDIAN_BITFIELD 6466 uint64_t reserved_25_63:39; 6467 uint64_t xchange:1; 6468 uint64_t ptp_lost:4; 6469 uint64_t late_col:4; 6470 uint64_t xsdef:4; 6471 uint64_t xscol:4; 6472 uint64_t reserved_6_7:2; 6473 uint64_t undflw:4; 6474 uint64_t pko_nxp:1; 6475 uint64_t pko_nxa:1; 6476#else 6477 uint64_t pko_nxa:1; 6478 uint64_t pko_nxp:1; 6479 uint64_t undflw:4; 6480 uint64_t reserved_6_7:2; 6481 uint64_t xscol:4; 6482 uint64_t xsdef:4; 6483 uint64_t late_col:4; 6484 uint64_t ptp_lost:4; 6485 uint64_t xchange:1; 6486 uint64_t reserved_25_63:39; 6487#endif 6488 } cn68xx; 6489 struct cvmx_gmxx_tx_int_reg_cn68xx cn68xxp1; 6490 struct cvmx_gmxx_tx_int_reg_cnf71xx { 6491#ifdef __BIG_ENDIAN_BITFIELD 6492 uint64_t reserved_25_63:39; 6493 uint64_t xchange:1; 6494 uint64_t reserved_22_23:2; 6495 uint64_t ptp_lost:2; 6496 uint64_t reserved_18_19:2; 6497 uint64_t late_col:2; 6498 uint64_t reserved_14_15:2; 6499 uint64_t xsdef:2; 6500 uint64_t reserved_10_11:2; 6501 uint64_t xscol:2; 6502 uint64_t reserved_4_7:4; 6503 uint64_t undflw:2; 6504 uint64_t reserved_1_1:1; 6505 uint64_t pko_nxa:1; 6506#else 6507 uint64_t pko_nxa:1; 6508 uint64_t reserved_1_1:1; 6509 uint64_t undflw:2; 6510 uint64_t reserved_4_7:4; 6511 uint64_t xscol:2; 6512 uint64_t reserved_10_11:2; 6513 uint64_t xsdef:2; 6514 uint64_t reserved_14_15:2; 6515 uint64_t late_col:2; 6516 uint64_t reserved_18_19:2; 6517 uint64_t ptp_lost:2; 6518 uint64_t reserved_22_23:2; 6519 uint64_t xchange:1; 6520 uint64_t reserved_25_63:39; 6521#endif 6522 } cnf71xx; 6523}; 6524 6525union cvmx_gmxx_tx_jam { 6526 uint64_t u64; 6527 struct cvmx_gmxx_tx_jam_s { 6528#ifdef __BIG_ENDIAN_BITFIELD 6529 uint64_t reserved_8_63:56; 6530 uint64_t jam:8; 6531#else 6532 uint64_t jam:8; 6533 uint64_t reserved_8_63:56; 6534#endif 6535 } s; 6536 struct cvmx_gmxx_tx_jam_s cn30xx; 6537 struct cvmx_gmxx_tx_jam_s cn31xx; 6538 struct cvmx_gmxx_tx_jam_s cn38xx; 6539 struct cvmx_gmxx_tx_jam_s cn38xxp2; 6540 struct cvmx_gmxx_tx_jam_s cn50xx; 6541 struct cvmx_gmxx_tx_jam_s cn52xx; 6542 struct cvmx_gmxx_tx_jam_s cn52xxp1; 6543 struct cvmx_gmxx_tx_jam_s cn56xx; 6544 struct cvmx_gmxx_tx_jam_s cn56xxp1; 6545 struct cvmx_gmxx_tx_jam_s cn58xx; 6546 struct cvmx_gmxx_tx_jam_s cn58xxp1; 6547 struct cvmx_gmxx_tx_jam_s cn61xx; 6548 struct cvmx_gmxx_tx_jam_s cn63xx; 6549 struct cvmx_gmxx_tx_jam_s cn63xxp1; 6550 struct cvmx_gmxx_tx_jam_s cn66xx; 6551 struct cvmx_gmxx_tx_jam_s cn68xx; 6552 struct cvmx_gmxx_tx_jam_s cn68xxp1; 6553 struct cvmx_gmxx_tx_jam_s cnf71xx; 6554}; 6555 6556union cvmx_gmxx_tx_lfsr { 6557 uint64_t u64; 6558 struct cvmx_gmxx_tx_lfsr_s { 6559#ifdef __BIG_ENDIAN_BITFIELD 6560 uint64_t reserved_16_63:48; 6561 uint64_t lfsr:16; 6562#else 6563 uint64_t lfsr:16; 6564 uint64_t reserved_16_63:48; 6565#endif 6566 } s; 6567 struct cvmx_gmxx_tx_lfsr_s cn30xx; 6568 struct cvmx_gmxx_tx_lfsr_s cn31xx; 6569 struct cvmx_gmxx_tx_lfsr_s cn38xx; 6570 struct cvmx_gmxx_tx_lfsr_s cn38xxp2; 6571 struct cvmx_gmxx_tx_lfsr_s cn50xx; 6572 struct cvmx_gmxx_tx_lfsr_s cn52xx; 6573 struct cvmx_gmxx_tx_lfsr_s cn52xxp1; 6574 struct cvmx_gmxx_tx_lfsr_s cn56xx; 6575 struct cvmx_gmxx_tx_lfsr_s cn56xxp1; 6576 struct cvmx_gmxx_tx_lfsr_s cn58xx; 6577 struct cvmx_gmxx_tx_lfsr_s cn58xxp1; 6578 struct cvmx_gmxx_tx_lfsr_s cn61xx; 6579 struct cvmx_gmxx_tx_lfsr_s cn63xx; 6580 struct cvmx_gmxx_tx_lfsr_s cn63xxp1; 6581 struct cvmx_gmxx_tx_lfsr_s cn66xx; 6582 struct cvmx_gmxx_tx_lfsr_s cn68xx; 6583 struct cvmx_gmxx_tx_lfsr_s cn68xxp1; 6584 struct cvmx_gmxx_tx_lfsr_s cnf71xx; 6585}; 6586 6587union cvmx_gmxx_tx_ovr_bp { 6588 uint64_t u64; 6589 struct cvmx_gmxx_tx_ovr_bp_s { 6590#ifdef __BIG_ENDIAN_BITFIELD 6591 uint64_t reserved_48_63:16; 6592 uint64_t tx_prt_bp:16; 6593 uint64_t reserved_12_31:20; 6594 uint64_t en:4; 6595 uint64_t bp:4; 6596 uint64_t ign_full:4; 6597#else 6598 uint64_t ign_full:4; 6599 uint64_t bp:4; 6600 uint64_t en:4; 6601 uint64_t reserved_12_31:20; 6602 uint64_t tx_prt_bp:16; 6603 uint64_t reserved_48_63:16; 6604#endif 6605 } s; 6606 struct cvmx_gmxx_tx_ovr_bp_cn30xx { 6607#ifdef __BIG_ENDIAN_BITFIELD 6608 uint64_t reserved_11_63:53; 6609 uint64_t en:3; 6610 uint64_t reserved_7_7:1; 6611 uint64_t bp:3; 6612 uint64_t reserved_3_3:1; 6613 uint64_t ign_full:3; 6614#else 6615 uint64_t ign_full:3; 6616 uint64_t reserved_3_3:1; 6617 uint64_t bp:3; 6618 uint64_t reserved_7_7:1; 6619 uint64_t en:3; 6620 uint64_t reserved_11_63:53; 6621#endif 6622 } cn30xx; 6623 struct cvmx_gmxx_tx_ovr_bp_cn30xx cn31xx; 6624 struct cvmx_gmxx_tx_ovr_bp_cn38xx { 6625#ifdef __BIG_ENDIAN_BITFIELD 6626 uint64_t reserved_12_63:52; 6627 uint64_t en:4; 6628 uint64_t bp:4; 6629 uint64_t ign_full:4; 6630#else 6631 uint64_t ign_full:4; 6632 uint64_t bp:4; 6633 uint64_t en:4; 6634 uint64_t reserved_12_63:52; 6635#endif 6636 } cn38xx; 6637 struct cvmx_gmxx_tx_ovr_bp_cn38xx cn38xxp2; 6638 struct cvmx_gmxx_tx_ovr_bp_cn30xx cn50xx; 6639 struct cvmx_gmxx_tx_ovr_bp_s cn52xx; 6640 struct cvmx_gmxx_tx_ovr_bp_s cn52xxp1; 6641 struct cvmx_gmxx_tx_ovr_bp_s cn56xx; 6642 struct cvmx_gmxx_tx_ovr_bp_s cn56xxp1; 6643 struct cvmx_gmxx_tx_ovr_bp_cn38xx cn58xx; 6644 struct cvmx_gmxx_tx_ovr_bp_cn38xx cn58xxp1; 6645 struct cvmx_gmxx_tx_ovr_bp_s cn61xx; 6646 struct cvmx_gmxx_tx_ovr_bp_s cn63xx; 6647 struct cvmx_gmxx_tx_ovr_bp_s cn63xxp1; 6648 struct cvmx_gmxx_tx_ovr_bp_s cn66xx; 6649 struct cvmx_gmxx_tx_ovr_bp_s cn68xx; 6650 struct cvmx_gmxx_tx_ovr_bp_s cn68xxp1; 6651 struct cvmx_gmxx_tx_ovr_bp_cnf71xx { 6652#ifdef __BIG_ENDIAN_BITFIELD 6653 uint64_t reserved_48_63:16; 6654 uint64_t tx_prt_bp:16; 6655 uint64_t reserved_10_31:22; 6656 uint64_t en:2; 6657 uint64_t reserved_6_7:2; 6658 uint64_t bp:2; 6659 uint64_t reserved_2_3:2; 6660 uint64_t ign_full:2; 6661#else 6662 uint64_t ign_full:2; 6663 uint64_t reserved_2_3:2; 6664 uint64_t bp:2; 6665 uint64_t reserved_6_7:2; 6666 uint64_t en:2; 6667 uint64_t reserved_10_31:22; 6668 uint64_t tx_prt_bp:16; 6669 uint64_t reserved_48_63:16; 6670#endif 6671 } cnf71xx; 6672}; 6673 6674union cvmx_gmxx_tx_pause_pkt_dmac { 6675 uint64_t u64; 6676 struct cvmx_gmxx_tx_pause_pkt_dmac_s { 6677#ifdef __BIG_ENDIAN_BITFIELD 6678 uint64_t reserved_48_63:16; 6679 uint64_t dmac:48; 6680#else 6681 uint64_t dmac:48; 6682 uint64_t reserved_48_63:16; 6683#endif 6684 } s; 6685 struct cvmx_gmxx_tx_pause_pkt_dmac_s cn30xx; 6686 struct cvmx_gmxx_tx_pause_pkt_dmac_s cn31xx; 6687 struct cvmx_gmxx_tx_pause_pkt_dmac_s cn38xx; 6688 struct cvmx_gmxx_tx_pause_pkt_dmac_s cn38xxp2; 6689 struct cvmx_gmxx_tx_pause_pkt_dmac_s cn50xx; 6690 struct cvmx_gmxx_tx_pause_pkt_dmac_s cn52xx; 6691 struct cvmx_gmxx_tx_pause_pkt_dmac_s cn52xxp1; 6692 struct cvmx_gmxx_tx_pause_pkt_dmac_s cn56xx; 6693 struct cvmx_gmxx_tx_pause_pkt_dmac_s cn56xxp1; 6694 struct cvmx_gmxx_tx_pause_pkt_dmac_s cn58xx; 6695 struct cvmx_gmxx_tx_pause_pkt_dmac_s cn58xxp1; 6696 struct cvmx_gmxx_tx_pause_pkt_dmac_s cn61xx; 6697 struct cvmx_gmxx_tx_pause_pkt_dmac_s cn63xx; 6698 struct cvmx_gmxx_tx_pause_pkt_dmac_s cn63xxp1; 6699 struct cvmx_gmxx_tx_pause_pkt_dmac_s cn66xx; 6700 struct cvmx_gmxx_tx_pause_pkt_dmac_s cn68xx; 6701 struct cvmx_gmxx_tx_pause_pkt_dmac_s cn68xxp1; 6702 struct cvmx_gmxx_tx_pause_pkt_dmac_s cnf71xx; 6703}; 6704 6705union cvmx_gmxx_tx_pause_pkt_type { 6706 uint64_t u64; 6707 struct cvmx_gmxx_tx_pause_pkt_type_s { 6708#ifdef __BIG_ENDIAN_BITFIELD 6709 uint64_t reserved_16_63:48; 6710 uint64_t type:16; 6711#else 6712 uint64_t type:16; 6713 uint64_t reserved_16_63:48; 6714#endif 6715 } s; 6716 struct cvmx_gmxx_tx_pause_pkt_type_s cn30xx; 6717 struct cvmx_gmxx_tx_pause_pkt_type_s cn31xx; 6718 struct cvmx_gmxx_tx_pause_pkt_type_s cn38xx; 6719 struct cvmx_gmxx_tx_pause_pkt_type_s cn38xxp2; 6720 struct cvmx_gmxx_tx_pause_pkt_type_s cn50xx; 6721 struct cvmx_gmxx_tx_pause_pkt_type_s cn52xx; 6722 struct cvmx_gmxx_tx_pause_pkt_type_s cn52xxp1; 6723 struct cvmx_gmxx_tx_pause_pkt_type_s cn56xx; 6724 struct cvmx_gmxx_tx_pause_pkt_type_s cn56xxp1; 6725 struct cvmx_gmxx_tx_pause_pkt_type_s cn58xx; 6726 struct cvmx_gmxx_tx_pause_pkt_type_s cn58xxp1; 6727 struct cvmx_gmxx_tx_pause_pkt_type_s cn61xx; 6728 struct cvmx_gmxx_tx_pause_pkt_type_s cn63xx; 6729 struct cvmx_gmxx_tx_pause_pkt_type_s cn63xxp1; 6730 struct cvmx_gmxx_tx_pause_pkt_type_s cn66xx; 6731 struct cvmx_gmxx_tx_pause_pkt_type_s cn68xx; 6732 struct cvmx_gmxx_tx_pause_pkt_type_s cn68xxp1; 6733 struct cvmx_gmxx_tx_pause_pkt_type_s cnf71xx; 6734}; 6735 6736union cvmx_gmxx_tx_prts { 6737 uint64_t u64; 6738 struct cvmx_gmxx_tx_prts_s { 6739#ifdef __BIG_ENDIAN_BITFIELD 6740 uint64_t reserved_5_63:59; 6741 uint64_t prts:5; 6742#else 6743 uint64_t prts:5; 6744 uint64_t reserved_5_63:59; 6745#endif 6746 } s; 6747 struct cvmx_gmxx_tx_prts_s cn30xx; 6748 struct cvmx_gmxx_tx_prts_s cn31xx; 6749 struct cvmx_gmxx_tx_prts_s cn38xx; 6750 struct cvmx_gmxx_tx_prts_s cn38xxp2; 6751 struct cvmx_gmxx_tx_prts_s cn50xx; 6752 struct cvmx_gmxx_tx_prts_s cn52xx; 6753 struct cvmx_gmxx_tx_prts_s cn52xxp1; 6754 struct cvmx_gmxx_tx_prts_s cn56xx; 6755 struct cvmx_gmxx_tx_prts_s cn56xxp1; 6756 struct cvmx_gmxx_tx_prts_s cn58xx; 6757 struct cvmx_gmxx_tx_prts_s cn58xxp1; 6758 struct cvmx_gmxx_tx_prts_s cn61xx; 6759 struct cvmx_gmxx_tx_prts_s cn63xx; 6760 struct cvmx_gmxx_tx_prts_s cn63xxp1; 6761 struct cvmx_gmxx_tx_prts_s cn66xx; 6762 struct cvmx_gmxx_tx_prts_s cn68xx; 6763 struct cvmx_gmxx_tx_prts_s cn68xxp1; 6764 struct cvmx_gmxx_tx_prts_s cnf71xx; 6765}; 6766 6767union cvmx_gmxx_tx_spi_ctl { 6768 uint64_t u64; 6769 struct cvmx_gmxx_tx_spi_ctl_s { 6770#ifdef __BIG_ENDIAN_BITFIELD 6771 uint64_t reserved_2_63:62; 6772 uint64_t tpa_clr:1; 6773 uint64_t cont_pkt:1; 6774#else 6775 uint64_t cont_pkt:1; 6776 uint64_t tpa_clr:1; 6777 uint64_t reserved_2_63:62; 6778#endif 6779 } s; 6780 struct cvmx_gmxx_tx_spi_ctl_s cn38xx; 6781 struct cvmx_gmxx_tx_spi_ctl_s cn38xxp2; 6782 struct cvmx_gmxx_tx_spi_ctl_s cn58xx; 6783 struct cvmx_gmxx_tx_spi_ctl_s cn58xxp1; 6784}; 6785 6786union cvmx_gmxx_tx_spi_drain { 6787 uint64_t u64; 6788 struct cvmx_gmxx_tx_spi_drain_s { 6789#ifdef __BIG_ENDIAN_BITFIELD 6790 uint64_t reserved_16_63:48; 6791 uint64_t drain:16; 6792#else 6793 uint64_t drain:16; 6794 uint64_t reserved_16_63:48; 6795#endif 6796 } s; 6797 struct cvmx_gmxx_tx_spi_drain_s cn38xx; 6798 struct cvmx_gmxx_tx_spi_drain_s cn58xx; 6799 struct cvmx_gmxx_tx_spi_drain_s cn58xxp1; 6800}; 6801 6802union cvmx_gmxx_tx_spi_max { 6803 uint64_t u64; 6804 struct cvmx_gmxx_tx_spi_max_s { 6805#ifdef __BIG_ENDIAN_BITFIELD 6806 uint64_t reserved_23_63:41; 6807 uint64_t slice:7; 6808 uint64_t max2:8; 6809 uint64_t max1:8; 6810#else 6811 uint64_t max1:8; 6812 uint64_t max2:8; 6813 uint64_t slice:7; 6814 uint64_t reserved_23_63:41; 6815#endif 6816 } s; 6817 struct cvmx_gmxx_tx_spi_max_cn38xx { 6818#ifdef __BIG_ENDIAN_BITFIELD 6819 uint64_t reserved_16_63:48; 6820 uint64_t max2:8; 6821 uint64_t max1:8; 6822#else 6823 uint64_t max1:8; 6824 uint64_t max2:8; 6825 uint64_t reserved_16_63:48; 6826#endif 6827 } cn38xx; 6828 struct cvmx_gmxx_tx_spi_max_cn38xx cn38xxp2; 6829 struct cvmx_gmxx_tx_spi_max_s cn58xx; 6830 struct cvmx_gmxx_tx_spi_max_s cn58xxp1; 6831}; 6832 6833union cvmx_gmxx_tx_spi_roundx { 6834 uint64_t u64; 6835 struct cvmx_gmxx_tx_spi_roundx_s { 6836#ifdef __BIG_ENDIAN_BITFIELD 6837 uint64_t reserved_16_63:48; 6838 uint64_t round:16; 6839#else 6840 uint64_t round:16; 6841 uint64_t reserved_16_63:48; 6842#endif 6843 } s; 6844 struct cvmx_gmxx_tx_spi_roundx_s cn58xx; 6845 struct cvmx_gmxx_tx_spi_roundx_s cn58xxp1; 6846}; 6847 6848union cvmx_gmxx_tx_spi_thresh { 6849 uint64_t u64; 6850 struct cvmx_gmxx_tx_spi_thresh_s { 6851#ifdef __BIG_ENDIAN_BITFIELD 6852 uint64_t reserved_6_63:58; 6853 uint64_t thresh:6; 6854#else 6855 uint64_t thresh:6; 6856 uint64_t reserved_6_63:58; 6857#endif 6858 } s; 6859 struct cvmx_gmxx_tx_spi_thresh_s cn38xx; 6860 struct cvmx_gmxx_tx_spi_thresh_s cn38xxp2; 6861 struct cvmx_gmxx_tx_spi_thresh_s cn58xx; 6862 struct cvmx_gmxx_tx_spi_thresh_s cn58xxp1; 6863}; 6864 6865union cvmx_gmxx_tx_xaui_ctl { 6866 uint64_t u64; 6867 struct cvmx_gmxx_tx_xaui_ctl_s { 6868#ifdef __BIG_ENDIAN_BITFIELD 6869 uint64_t reserved_11_63:53; 6870 uint64_t hg_pause_hgi:2; 6871 uint64_t hg_en:1; 6872 uint64_t reserved_7_7:1; 6873 uint64_t ls_byp:1; 6874 uint64_t ls:2; 6875 uint64_t reserved_2_3:2; 6876 uint64_t uni_en:1; 6877 uint64_t dic_en:1; 6878#else 6879 uint64_t dic_en:1; 6880 uint64_t uni_en:1; 6881 uint64_t reserved_2_3:2; 6882 uint64_t ls:2; 6883 uint64_t ls_byp:1; 6884 uint64_t reserved_7_7:1; 6885 uint64_t hg_en:1; 6886 uint64_t hg_pause_hgi:2; 6887 uint64_t reserved_11_63:53; 6888#endif 6889 } s; 6890 struct cvmx_gmxx_tx_xaui_ctl_s cn52xx; 6891 struct cvmx_gmxx_tx_xaui_ctl_s cn52xxp1; 6892 struct cvmx_gmxx_tx_xaui_ctl_s cn56xx; 6893 struct cvmx_gmxx_tx_xaui_ctl_s cn56xxp1; 6894 struct cvmx_gmxx_tx_xaui_ctl_s cn61xx; 6895 struct cvmx_gmxx_tx_xaui_ctl_s cn63xx; 6896 struct cvmx_gmxx_tx_xaui_ctl_s cn63xxp1; 6897 struct cvmx_gmxx_tx_xaui_ctl_s cn66xx; 6898 struct cvmx_gmxx_tx_xaui_ctl_s cn68xx; 6899 struct cvmx_gmxx_tx_xaui_ctl_s cn68xxp1; 6900 struct cvmx_gmxx_tx_xaui_ctl_s cnf71xx; 6901}; 6902 6903union cvmx_gmxx_xaui_ext_loopback { 6904 uint64_t u64; 6905 struct cvmx_gmxx_xaui_ext_loopback_s { 6906#ifdef __BIG_ENDIAN_BITFIELD 6907 uint64_t reserved_5_63:59; 6908 uint64_t en:1; 6909 uint64_t thresh:4; 6910#else 6911 uint64_t thresh:4; 6912 uint64_t en:1; 6913 uint64_t reserved_5_63:59; 6914#endif 6915 } s; 6916 struct cvmx_gmxx_xaui_ext_loopback_s cn52xx; 6917 struct cvmx_gmxx_xaui_ext_loopback_s cn52xxp1; 6918 struct cvmx_gmxx_xaui_ext_loopback_s cn56xx; 6919 struct cvmx_gmxx_xaui_ext_loopback_s cn56xxp1; 6920 struct cvmx_gmxx_xaui_ext_loopback_s cn61xx; 6921 struct cvmx_gmxx_xaui_ext_loopback_s cn63xx; 6922 struct cvmx_gmxx_xaui_ext_loopback_s cn63xxp1; 6923 struct cvmx_gmxx_xaui_ext_loopback_s cn66xx; 6924 struct cvmx_gmxx_xaui_ext_loopback_s cn68xx; 6925 struct cvmx_gmxx_xaui_ext_loopback_s cn68xxp1; 6926 struct cvmx_gmxx_xaui_ext_loopback_s cnf71xx; 6927}; 6928 6929#endif 6930