1/* 2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights 3 * reserved. 4 * 5 * This software is available to you under a choice of one of two 6 * licenses. You may choose to be licensed under the terms of the GNU 7 * General Public License (GPL) Version 2, available from the file 8 * COPYING in the main directory of this source tree, or the NetLogic 9 * license below: 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in 19 * the documentation and/or other materials provided with the 20 * distribution. 21 * 22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE 31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN 32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35#ifndef _ASM_NLM_XLR_PIC_H 36#define _ASM_NLM_XLR_PIC_H 37 38#define PIC_CLK_HZ 66666666 39#define pic_timer_freq() PIC_CLK_HZ 40 41/* PIC hardware interrupt numbers */ 42#define PIC_IRT_WD_INDEX 0 43#define PIC_IRT_TIMER_0_INDEX 1 44#define PIC_IRT_TIMER_INDEX(i) ((i) + PIC_IRT_TIMER_0_INDEX) 45#define PIC_IRT_TIMER_1_INDEX 2 46#define PIC_IRT_TIMER_2_INDEX 3 47#define PIC_IRT_TIMER_3_INDEX 4 48#define PIC_IRT_TIMER_4_INDEX 5 49#define PIC_IRT_TIMER_5_INDEX 6 50#define PIC_IRT_TIMER_6_INDEX 7 51#define PIC_IRT_TIMER_7_INDEX 8 52#define PIC_IRT_CLOCK_INDEX PIC_IRT_TIMER_7_INDEX 53#define PIC_IRT_UART_0_INDEX 9 54#define PIC_IRT_UART_1_INDEX 10 55#define PIC_IRT_I2C_0_INDEX 11 56#define PIC_IRT_I2C_1_INDEX 12 57#define PIC_IRT_PCMCIA_INDEX 13 58#define PIC_IRT_GPIO_INDEX 14 59#define PIC_IRT_HYPER_INDEX 15 60#define PIC_IRT_PCIX_INDEX 16 61/* XLS */ 62#define PIC_IRT_CDE_INDEX 15 63#define PIC_IRT_BRIDGE_TB_XLS_INDEX 16 64/* XLS */ 65#define PIC_IRT_GMAC0_INDEX 17 66#define PIC_IRT_GMAC1_INDEX 18 67#define PIC_IRT_GMAC2_INDEX 19 68#define PIC_IRT_GMAC3_INDEX 20 69#define PIC_IRT_XGS0_INDEX 21 70#define PIC_IRT_XGS1_INDEX 22 71#define PIC_IRT_HYPER_FATAL_INDEX 23 72#define PIC_IRT_PCIX_FATAL_INDEX 24 73#define PIC_IRT_BRIDGE_AERR_INDEX 25 74#define PIC_IRT_BRIDGE_BERR_INDEX 26 75#define PIC_IRT_BRIDGE_TB_XLR_INDEX 27 76#define PIC_IRT_BRIDGE_AERR_NMI_INDEX 28 77/* XLS */ 78#define PIC_IRT_GMAC4_INDEX 21 79#define PIC_IRT_GMAC5_INDEX 22 80#define PIC_IRT_GMAC6_INDEX 23 81#define PIC_IRT_GMAC7_INDEX 24 82#define PIC_IRT_BRIDGE_ERR_INDEX 25 83#define PIC_IRT_PCIE_LINK0_INDEX 26 84#define PIC_IRT_PCIE_LINK1_INDEX 27 85#define PIC_IRT_PCIE_LINK2_INDEX 23 86#define PIC_IRT_PCIE_LINK3_INDEX 24 87#define PIC_IRT_PCIE_XLSB0_LINK2_INDEX 28 88#define PIC_IRT_PCIE_XLSB0_LINK3_INDEX 29 89#define PIC_IRT_SRIO_LINK0_INDEX 26 90#define PIC_IRT_SRIO_LINK1_INDEX 27 91#define PIC_IRT_SRIO_LINK2_INDEX 28 92#define PIC_IRT_SRIO_LINK3_INDEX 29 93#define PIC_IRT_PCIE_INT_INDEX 28 94#define PIC_IRT_PCIE_FATAL_INDEX 29 95#define PIC_IRT_GPIO_B_INDEX 30 96#define PIC_IRT_USB_INDEX 31 97/* XLS */ 98#define PIC_NUM_IRTS 32 99 100 101#define PIC_CLOCK_TIMER 7 102 103/* PIC Registers */ 104#define PIC_CTRL 0x00 105#define PIC_CTRL_STE 8 /* timer enable start bit */ 106#define PIC_IPI 0x04 107#define PIC_INT_ACK 0x06 108 109#define WD_MAX_VAL_0 0x08 110#define WD_MAX_VAL_1 0x09 111#define WD_MASK_0 0x0a 112#define WD_MASK_1 0x0b 113#define WD_HEARBEAT_0 0x0c 114#define WD_HEARBEAT_1 0x0d 115 116#define PIC_IRT_0_BASE 0x40 117#define PIC_IRT_1_BASE 0x80 118#define PIC_TIMER_MAXVAL_0_BASE 0x100 119#define PIC_TIMER_MAXVAL_1_BASE 0x110 120#define PIC_TIMER_COUNT_0_BASE 0x120 121#define PIC_TIMER_COUNT_1_BASE 0x130 122 123#define PIC_IRT_0(picintr) (PIC_IRT_0_BASE + (picintr)) 124#define PIC_IRT_1(picintr) (PIC_IRT_1_BASE + (picintr)) 125 126#define PIC_TIMER_MAXVAL_0(i) (PIC_TIMER_MAXVAL_0_BASE + (i)) 127#define PIC_TIMER_MAXVAL_1(i) (PIC_TIMER_MAXVAL_1_BASE + (i)) 128#define PIC_TIMER_COUNT_0(i) (PIC_TIMER_COUNT_0_BASE + (i)) 129#define PIC_TIMER_COUNT_1(i) (PIC_TIMER_COUNT_0_BASE + (i)) 130 131/* 132 * Mapping between hardware interrupt numbers and IRQs on CPU 133 * we use a simple scheme to map PIC interrupts 0-31 to IRQs 134 * 8-39. This leaves the IRQ 0-7 for cpu interrupts like 135 * count/compare and FMN 136 */ 137#define PIC_IRQ_BASE 8 138#define PIC_INTR_TO_IRQ(i) (PIC_IRQ_BASE + (i)) 139#define PIC_IRQ_TO_INTR(i) ((i) - PIC_IRQ_BASE) 140 141#define PIC_IRT_FIRST_IRQ PIC_IRQ_BASE 142#define PIC_WD_IRQ PIC_INTR_TO_IRQ(PIC_IRT_WD_INDEX) 143#define PIC_TIMER_0_IRQ PIC_INTR_TO_IRQ(PIC_IRT_TIMER_0_INDEX) 144#define PIC_TIMER_1_IRQ PIC_INTR_TO_IRQ(PIC_IRT_TIMER_1_INDEX) 145#define PIC_TIMER_2_IRQ PIC_INTR_TO_IRQ(PIC_IRT_TIMER_2_INDEX) 146#define PIC_TIMER_3_IRQ PIC_INTR_TO_IRQ(PIC_IRT_TIMER_3_INDEX) 147#define PIC_TIMER_4_IRQ PIC_INTR_TO_IRQ(PIC_IRT_TIMER_4_INDEX) 148#define PIC_TIMER_5_IRQ PIC_INTR_TO_IRQ(PIC_IRT_TIMER_5_INDEX) 149#define PIC_TIMER_6_IRQ PIC_INTR_TO_IRQ(PIC_IRT_TIMER_6_INDEX) 150#define PIC_TIMER_7_IRQ PIC_INTR_TO_IRQ(PIC_IRT_TIMER_7_INDEX) 151#define PIC_CLOCK_IRQ (PIC_TIMER_7_IRQ) 152#define PIC_UART_0_IRQ PIC_INTR_TO_IRQ(PIC_IRT_UART_0_INDEX) 153#define PIC_UART_1_IRQ PIC_INTR_TO_IRQ(PIC_IRT_UART_1_INDEX) 154#define PIC_I2C_0_IRQ PIC_INTR_TO_IRQ(PIC_IRT_I2C_0_INDEX) 155#define PIC_I2C_1_IRQ PIC_INTR_TO_IRQ(PIC_IRT_I2C_1_INDEX) 156#define PIC_PCMCIA_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCMCIA_INDEX) 157#define PIC_GPIO_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GPIO_INDEX) 158#define PIC_HYPER_IRQ PIC_INTR_TO_IRQ(PIC_IRT_HYPER_INDEX) 159#define PIC_PCIX_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIX_INDEX) 160/* XLS */ 161#define PIC_CDE_IRQ PIC_INTR_TO_IRQ(PIC_IRT_CDE_INDEX) 162#define PIC_BRIDGE_TB_XLS_IRQ PIC_INTR_TO_IRQ(PIC_IRT_BRIDGE_TB_XLS_INDEX) 163/* end XLS */ 164#define PIC_GMAC_0_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GMAC0_INDEX) 165#define PIC_GMAC_1_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GMAC1_INDEX) 166#define PIC_GMAC_2_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GMAC2_INDEX) 167#define PIC_GMAC_3_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GMAC3_INDEX) 168#define PIC_XGS_0_IRQ PIC_INTR_TO_IRQ(PIC_IRT_XGS0_INDEX) 169#define PIC_XGS_1_IRQ PIC_INTR_TO_IRQ(PIC_IRT_XGS1_INDEX) 170#define PIC_HYPER_FATAL_IRQ PIC_INTR_TO_IRQ(PIC_IRT_HYPER_FATAL_INDEX) 171#define PIC_PCIX_FATAL_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIX_FATAL_INDEX) 172#define PIC_BRIDGE_AERR_IRQ PIC_INTR_TO_IRQ(PIC_IRT_BRIDGE_AERR_INDEX) 173#define PIC_BRIDGE_BERR_IRQ PIC_INTR_TO_IRQ(PIC_IRT_BRIDGE_BERR_INDEX) 174#define PIC_BRIDGE_TB_XLR_IRQ PIC_INTR_TO_IRQ(PIC_IRT_BRIDGE_TB_XLR_INDEX) 175#define PIC_BRIDGE_AERR_NMI_IRQ PIC_INTR_TO_IRQ(PIC_IRT_BRIDGE_AERR_NMI_INDEX) 176/* XLS defines */ 177#define PIC_GMAC_4_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GMAC4_INDEX) 178#define PIC_GMAC_5_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GMAC5_INDEX) 179#define PIC_GMAC_6_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GMAC6_INDEX) 180#define PIC_GMAC_7_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GMAC7_INDEX) 181#define PIC_BRIDGE_ERR_IRQ PIC_INTR_TO_IRQ(PIC_IRT_BRIDGE_ERR_INDEX) 182#define PIC_PCIE_LINK0_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIE_LINK0_INDEX) 183#define PIC_PCIE_LINK1_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIE_LINK1_INDEX) 184#define PIC_PCIE_LINK2_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIE_LINK2_INDEX) 185#define PIC_PCIE_LINK3_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIE_LINK3_INDEX) 186#define PIC_PCIE_XLSB0_LINK2_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIE_XLSB0_LINK2_INDEX) 187#define PIC_PCIE_XLSB0_LINK3_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIE_XLSB0_LINK3_INDEX) 188#define PIC_SRIO_LINK0_IRQ PIC_INTR_TO_IRQ(PIC_IRT_SRIO_LINK0_INDEX) 189#define PIC_SRIO_LINK1_IRQ PIC_INTR_TO_IRQ(PIC_IRT_SRIO_LINK1_INDEX) 190#define PIC_SRIO_LINK2_IRQ PIC_INTR_TO_IRQ(PIC_IRT_SRIO_LINK2_INDEX) 191#define PIC_SRIO_LINK3_IRQ PIC_INTR_TO_IRQ(PIC_IRT_SRIO_LINK3_INDEX) 192#define PIC_PCIE_INT_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIE_INT__INDEX) 193#define PIC_PCIE_FATAL_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIE_FATAL_INDEX) 194#define PIC_GPIO_B_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GPIO_B_INDEX) 195#define PIC_USB_IRQ PIC_INTR_TO_IRQ(PIC_IRT_USB_INDEX) 196#define PIC_IRT_LAST_IRQ PIC_USB_IRQ 197/* end XLS */ 198 199#ifndef __ASSEMBLY__ 200 201#define PIC_IRQ_IS_EDGE_TRIGGERED(irq) (((irq) >= PIC_TIMER_0_IRQ) && \ 202 ((irq) <= PIC_TIMER_7_IRQ)) 203#define PIC_IRQ_IS_IRT(irq) (((irq) >= PIC_IRT_FIRST_IRQ) && \ 204 ((irq) <= PIC_IRT_LAST_IRQ)) 205 206static inline int 207nlm_irq_to_irt(int irq) 208{ 209 if (PIC_IRQ_IS_IRT(irq) == 0) 210 return -1; 211 212 return PIC_IRQ_TO_INTR(irq); 213} 214 215static inline int 216nlm_irt_to_irq(int irt) 217{ 218 219 return PIC_INTR_TO_IRQ(irt); 220} 221 222static inline void 223nlm_pic_enable_irt(uint64_t base, int irt) 224{ 225 uint32_t reg; 226 227 reg = nlm_read_reg(base, PIC_IRT_1(irt)); 228 nlm_write_reg(base, PIC_IRT_1(irt), reg | (1u << 31)); 229} 230 231static inline void 232nlm_pic_disable_irt(uint64_t base, int irt) 233{ 234 uint32_t reg; 235 236 reg = nlm_read_reg(base, PIC_IRT_1(irt)); 237 nlm_write_reg(base, PIC_IRT_1(irt), reg & ~(1u << 31)); 238} 239 240static inline void 241nlm_pic_send_ipi(uint64_t base, int hwt, int irq, int nmi) 242{ 243 unsigned int tid, pid; 244 245 tid = hwt & 0x3; 246 pid = (hwt >> 2) & 0x07; 247 nlm_write_reg(base, PIC_IPI, 248 (pid << 20) | (tid << 16) | (nmi << 8) | irq); 249} 250 251static inline void 252nlm_pic_ack(uint64_t base, int irt) 253{ 254 nlm_write_reg(base, PIC_INT_ACK, 1u << irt); 255} 256 257static inline void 258nlm_pic_init_irt(uint64_t base, int irt, int irq, int hwt, int en) 259{ 260 nlm_write_reg(base, PIC_IRT_0(irt), (1u << hwt)); 261 /* local scheduling, invalid, level by default */ 262 nlm_write_reg(base, PIC_IRT_1(irt), 263 (en << 30) | (1 << 6) | irq); 264} 265 266static inline uint64_t 267nlm_pic_read_timer(uint64_t base, int timer) 268{ 269 uint32_t up1, up2, low; 270 271 up1 = nlm_read_reg(base, PIC_TIMER_COUNT_1(timer)); 272 low = nlm_read_reg(base, PIC_TIMER_COUNT_0(timer)); 273 up2 = nlm_read_reg(base, PIC_TIMER_COUNT_1(timer)); 274 275 if (up1 != up2) /* wrapped, get the new low */ 276 low = nlm_read_reg(base, PIC_TIMER_COUNT_0(timer)); 277 return ((uint64_t)up2 << 32) | low; 278 279} 280 281static inline uint32_t 282nlm_pic_read_timer32(uint64_t base, int timer) 283{ 284 return nlm_read_reg(base, PIC_TIMER_COUNT_0(timer)); 285} 286 287static inline void 288nlm_pic_set_timer(uint64_t base, int timer, uint64_t value, int irq, int cpu) 289{ 290 uint32_t up, low; 291 uint64_t pic_ctrl = nlm_read_reg(base, PIC_CTRL); 292 int en; 293 294 en = (irq > 0); 295 up = value >> 32; 296 low = value & 0xFFFFFFFF; 297 nlm_write_reg(base, PIC_TIMER_MAXVAL_0(timer), low); 298 nlm_write_reg(base, PIC_TIMER_MAXVAL_1(timer), up); 299 nlm_pic_init_irt(base, PIC_IRT_TIMER_INDEX(timer), irq, cpu, 0); 300 301 /* enable the timer */ 302 pic_ctrl |= (1 << (PIC_CTRL_STE + timer)); 303 nlm_write_reg(base, PIC_CTRL, pic_ctrl); 304} 305#endif 306#endif /* _ASM_NLM_XLR_PIC_H */ 307