1/* 2 * Copyright (C) 2009 Lemote, Inc. 3 * Author: Wu Zhangjin <wuzhangjin@gmail.com> 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License as published by the 7 * Free Software Foundation; either version 2 of the License, or (at your 8 * option) any later version. 9 */ 10 11#ifndef __ASM_MACH_LOONGSON_LOONGSON_H 12#define __ASM_MACH_LOONGSON_LOONGSON_H 13 14#include <linux/io.h> 15#include <linux/init.h> 16#include <linux/irq.h> 17#include <linux/kconfig.h> 18#include <boot_param.h> 19 20/* loongson internal northbridge initialization */ 21extern void bonito_irq_init(void); 22 23/* machine-specific reboot/halt operation */ 24extern void mach_prepare_reboot(void); 25extern void mach_prepare_shutdown(void); 26 27/* environment arguments from bootloader */ 28extern u32 cpu_clock_freq; 29extern u32 memsize, highmemsize; 30extern struct plat_smp_ops loongson3_smp_ops; 31 32/* loongson-specific command line, env and memory initialization */ 33extern void __init prom_init_memory(void); 34extern void __init prom_init_cmdline(void); 35extern void __init prom_init_machtype(void); 36extern void __init prom_init_env(void); 37#ifdef CONFIG_LOONGSON_UART_BASE 38extern unsigned long _loongson_uart_base[], loongson_uart_base[]; 39extern void prom_init_loongson_uart_base(void); 40#endif 41 42static inline void prom_init_uart_base(void) 43{ 44#ifdef CONFIG_LOONGSON_UART_BASE 45 prom_init_loongson_uart_base(); 46#endif 47} 48 49/* irq operation functions */ 50extern void bonito_irqdispatch(void); 51extern void __init bonito_irq_init(void); 52extern void __init mach_init_irq(void); 53extern void mach_irq_dispatch(unsigned int pending); 54extern int mach_i8259_irq(void); 55 56/* We need this in some places... */ 57#define delay() ({ \ 58 int x; \ 59 for (x = 0; x < 100000; x++) \ 60 __asm__ __volatile__(""); \ 61}) 62 63#define LOONGSON_REG(x) \ 64 (*(volatile u32 *)((char *)CKSEG1ADDR(LOONGSON_REG_BASE) + (x))) 65 66#define LOONGSON3_REG8(base, x) \ 67 (*(volatile u8 *)((char *)TO_UNCAC(base) + (x))) 68 69#define LOONGSON3_REG32(base, x) \ 70 (*(volatile u32 *)((char *)TO_UNCAC(base) + (x))) 71 72#define LOONGSON_IRQ_BASE 32 73#define LOONGSON2_PERFCNT_IRQ (MIPS_CPU_IRQ_BASE + 6) /* cpu perf counter */ 74 75#include <linux/interrupt.h> 76static inline void do_perfcnt_IRQ(void) 77{ 78#if IS_ENABLED(CONFIG_OPROFILE) 79 do_IRQ(LOONGSON2_PERFCNT_IRQ); 80#endif 81} 82 83#define LOONGSON_FLASH_BASE 0x1c000000 84#define LOONGSON_FLASH_SIZE 0x02000000 /* 32M */ 85#define LOONGSON_FLASH_TOP (LOONGSON_FLASH_BASE+LOONGSON_FLASH_SIZE-1) 86 87#define LOONGSON_LIO0_BASE 0x1e000000 88#define LOONGSON_LIO0_SIZE 0x01C00000 /* 28M */ 89#define LOONGSON_LIO0_TOP (LOONGSON_LIO0_BASE+LOONGSON_LIO0_SIZE-1) 90 91#define LOONGSON_BOOT_BASE 0x1fc00000 92#define LOONGSON_BOOT_SIZE 0x00100000 /* 1M */ 93#define LOONGSON_BOOT_TOP (LOONGSON_BOOT_BASE+LOONGSON_BOOT_SIZE-1) 94#define LOONGSON_REG_BASE 0x1fe00000 95#define LOONGSON_REG_SIZE 0x00100000 /* 256Bytes + 256Bytes + ??? */ 96#define LOONGSON_REG_TOP (LOONGSON_REG_BASE+LOONGSON_REG_SIZE-1) 97/* Loongson-3 specific registers */ 98#define LOONGSON3_REG_BASE 0x3ff00000 99#define LOONGSON3_REG_SIZE 0x00100000 /* 256Bytes + 256Bytes + ??? */ 100#define LOONGSON3_REG_TOP (LOONGSON3_REG_BASE+LOONGSON3_REG_SIZE-1) 101 102#define LOONGSON_LIO1_BASE 0x1ff00000 103#define LOONGSON_LIO1_SIZE 0x00100000 /* 1M */ 104#define LOONGSON_LIO1_TOP (LOONGSON_LIO1_BASE+LOONGSON_LIO1_SIZE-1) 105 106#define LOONGSON_PCILO0_BASE 0x10000000 107#define LOONGSON_PCILO1_BASE 0x14000000 108#define LOONGSON_PCILO2_BASE 0x18000000 109#define LOONGSON_PCILO_BASE LOONGSON_PCILO0_BASE 110#define LOONGSON_PCILO_SIZE 0x0c000000 /* 64M * 3 */ 111#define LOONGSON_PCILO_TOP (LOONGSON_PCILO0_BASE+LOONGSON_PCILO_SIZE-1) 112 113#define LOONGSON_PCICFG_BASE 0x1fe80000 114#define LOONGSON_PCICFG_SIZE 0x00000800 /* 2K */ 115#define LOONGSON_PCICFG_TOP (LOONGSON_PCICFG_BASE+LOONGSON_PCICFG_SIZE-1) 116 117#if defined(CONFIG_HT_PCI) 118#define LOONGSON_PCIIO_BASE loongson_sysconf.pci_io_base 119#else 120#define LOONGSON_PCIIO_BASE 0x1fd00000 121#endif 122 123#define LOONGSON_PCIIO_SIZE 0x00100000 /* 1M */ 124#define LOONGSON_PCIIO_TOP (LOONGSON_PCIIO_BASE+LOONGSON_PCIIO_SIZE-1) 125 126/* Loongson Register Bases */ 127 128#define LOONGSON_PCICONFIGBASE 0x00 129#define LOONGSON_REGBASE 0x100 130 131/* PCI Configuration Registers */ 132 133#define LOONGSON_PCI_REG(x) LOONGSON_REG(LOONGSON_PCICONFIGBASE + (x)) 134#define LOONGSON_PCIDID LOONGSON_PCI_REG(0x00) 135#define LOONGSON_PCICMD LOONGSON_PCI_REG(0x04) 136#define LOONGSON_PCICLASS LOONGSON_PCI_REG(0x08) 137#define LOONGSON_PCILTIMER LOONGSON_PCI_REG(0x0c) 138#define LOONGSON_PCIBASE0 LOONGSON_PCI_REG(0x10) 139#define LOONGSON_PCIBASE1 LOONGSON_PCI_REG(0x14) 140#define LOONGSON_PCIBASE2 LOONGSON_PCI_REG(0x18) 141#define LOONGSON_PCIBASE3 LOONGSON_PCI_REG(0x1c) 142#define LOONGSON_PCIBASE4 LOONGSON_PCI_REG(0x20) 143#define LOONGSON_PCIEXPRBASE LOONGSON_PCI_REG(0x30) 144#define LOONGSON_PCIINT LOONGSON_PCI_REG(0x3c) 145 146#define LOONGSON_PCI_ISR4C LOONGSON_PCI_REG(0x4c) 147 148#define LOONGSON_PCICMD_PERR_CLR 0x80000000 149#define LOONGSON_PCICMD_SERR_CLR 0x40000000 150#define LOONGSON_PCICMD_MABORT_CLR 0x20000000 151#define LOONGSON_PCICMD_MTABORT_CLR 0x10000000 152#define LOONGSON_PCICMD_TABORT_CLR 0x08000000 153#define LOONGSON_PCICMD_MPERR_CLR 0x01000000 154#define LOONGSON_PCICMD_PERRRESPEN 0x00000040 155#define LOONGSON_PCICMD_ASTEPEN 0x00000080 156#define LOONGSON_PCICMD_SERREN 0x00000100 157#define LOONGSON_PCILTIMER_BUSLATENCY 0x0000ff00 158#define LOONGSON_PCILTIMER_BUSLATENCY_SHIFT 8 159 160/* Loongson h/w Configuration */ 161 162#define LOONGSON_GENCFG_OFFSET 0x4 163#define LOONGSON_GENCFG LOONGSON_REG(LOONGSON_REGBASE + LOONGSON_GENCFG_OFFSET) 164 165#define LOONGSON_GENCFG_DEBUGMODE 0x00000001 166#define LOONGSON_GENCFG_SNOOPEN 0x00000002 167#define LOONGSON_GENCFG_CPUSELFRESET 0x00000004 168 169#define LOONGSON_GENCFG_FORCE_IRQA 0x00000008 170#define LOONGSON_GENCFG_IRQA_ISOUT 0x00000010 171#define LOONGSON_GENCFG_IRQA_FROM_INT1 0x00000020 172#define LOONGSON_GENCFG_BYTESWAP 0x00000040 173 174#define LOONGSON_GENCFG_UNCACHED 0x00000080 175#define LOONGSON_GENCFG_PREFETCHEN 0x00000100 176#define LOONGSON_GENCFG_WBEHINDEN 0x00000200 177#define LOONGSON_GENCFG_CACHEALG 0x00000c00 178#define LOONGSON_GENCFG_CACHEALG_SHIFT 10 179#define LOONGSON_GENCFG_PCIQUEUE 0x00001000 180#define LOONGSON_GENCFG_CACHESTOP 0x00002000 181#define LOONGSON_GENCFG_MSTRBYTESWAP 0x00004000 182#define LOONGSON_GENCFG_BUSERREN 0x00008000 183#define LOONGSON_GENCFG_NORETRYTIMEOUT 0x00010000 184#define LOONGSON_GENCFG_SHORTCOPYTIMEOUT 0x00020000 185 186/* PCI address map control */ 187 188#define LOONGSON_PCIMAP LOONGSON_REG(LOONGSON_REGBASE + 0x10) 189#define LOONGSON_PCIMEMBASECFG LOONGSON_REG(LOONGSON_REGBASE + 0x14) 190#define LOONGSON_PCIMAP_CFG LOONGSON_REG(LOONGSON_REGBASE + 0x18) 191 192/* GPIO Regs - r/w */ 193 194#define LOONGSON_GPIODATA LOONGSON_REG(LOONGSON_REGBASE + 0x1c) 195#define LOONGSON_GPIOIE LOONGSON_REG(LOONGSON_REGBASE + 0x20) 196 197/* ICU Configuration Regs - r/w */ 198 199#define LOONGSON_INTEDGE LOONGSON_REG(LOONGSON_REGBASE + 0x24) 200#define LOONGSON_INTSTEER LOONGSON_REG(LOONGSON_REGBASE + 0x28) 201#define LOONGSON_INTPOL LOONGSON_REG(LOONGSON_REGBASE + 0x2c) 202 203/* ICU Enable Regs - IntEn & IntISR are r/o. */ 204 205#define LOONGSON_INTENSET LOONGSON_REG(LOONGSON_REGBASE + 0x30) 206#define LOONGSON_INTENCLR LOONGSON_REG(LOONGSON_REGBASE + 0x34) 207#define LOONGSON_INTEN LOONGSON_REG(LOONGSON_REGBASE + 0x38) 208#define LOONGSON_INTISR LOONGSON_REG(LOONGSON_REGBASE + 0x3c) 209 210/* ICU */ 211#define LOONGSON_ICU_MBOXES 0x0000000f 212#define LOONGSON_ICU_MBOXES_SHIFT 0 213#define LOONGSON_ICU_DMARDY 0x00000010 214#define LOONGSON_ICU_DMAEMPTY 0x00000020 215#define LOONGSON_ICU_COPYRDY 0x00000040 216#define LOONGSON_ICU_COPYEMPTY 0x00000080 217#define LOONGSON_ICU_COPYERR 0x00000100 218#define LOONGSON_ICU_PCIIRQ 0x00000200 219#define LOONGSON_ICU_MASTERERR 0x00000400 220#define LOONGSON_ICU_SYSTEMERR 0x00000800 221#define LOONGSON_ICU_DRAMPERR 0x00001000 222#define LOONGSON_ICU_RETRYERR 0x00002000 223#define LOONGSON_ICU_GPIOS 0x01ff0000 224#define LOONGSON_ICU_GPIOS_SHIFT 16 225#define LOONGSON_ICU_GPINS 0x7e000000 226#define LOONGSON_ICU_GPINS_SHIFT 25 227#define LOONGSON_ICU_MBOX(N) (1<<(LOONGSON_ICU_MBOXES_SHIFT+(N))) 228#define LOONGSON_ICU_GPIO(N) (1<<(LOONGSON_ICU_GPIOS_SHIFT+(N))) 229#define LOONGSON_ICU_GPIN(N) (1<<(LOONGSON_ICU_GPINS_SHIFT+(N))) 230 231/* PCI prefetch window base & mask */ 232 233#define LOONGSON_MEM_WIN_BASE_L LOONGSON_REG(LOONGSON_REGBASE + 0x40) 234#define LOONGSON_MEM_WIN_BASE_H LOONGSON_REG(LOONGSON_REGBASE + 0x44) 235#define LOONGSON_MEM_WIN_MASK_L LOONGSON_REG(LOONGSON_REGBASE + 0x48) 236#define LOONGSON_MEM_WIN_MASK_H LOONGSON_REG(LOONGSON_REGBASE + 0x4c) 237 238/* PCI_Hit*_Sel_* */ 239 240#define LOONGSON_PCI_HIT0_SEL_L LOONGSON_REG(LOONGSON_REGBASE + 0x50) 241#define LOONGSON_PCI_HIT0_SEL_H LOONGSON_REG(LOONGSON_REGBASE + 0x54) 242#define LOONGSON_PCI_HIT1_SEL_L LOONGSON_REG(LOONGSON_REGBASE + 0x58) 243#define LOONGSON_PCI_HIT1_SEL_H LOONGSON_REG(LOONGSON_REGBASE + 0x5c) 244#define LOONGSON_PCI_HIT2_SEL_L LOONGSON_REG(LOONGSON_REGBASE + 0x60) 245#define LOONGSON_PCI_HIT2_SEL_H LOONGSON_REG(LOONGSON_REGBASE + 0x64) 246 247/* PXArb Config & Status */ 248 249#define LOONGSON_PXARB_CFG LOONGSON_REG(LOONGSON_REGBASE + 0x68) 250#define LOONGSON_PXARB_STATUS LOONGSON_REG(LOONGSON_REGBASE + 0x6c) 251 252#define MAX_PACKAGES 4 253 254/* Chip Config registor of each physical cpu package, PRid >= Loongson-2F */ 255extern u64 loongson_chipcfg[MAX_PACKAGES]; 256#define LOONGSON_CHIPCFG(id) (*(volatile u32 *)(loongson_chipcfg[id])) 257 258/* Chip Temperature registor of each physical cpu package, PRid >= Loongson-3A */ 259extern u64 loongson_chiptemp[MAX_PACKAGES]; 260#define LOONGSON_CHIPTEMP(id) (*(volatile u32 *)(loongson_chiptemp[id])) 261 262/* Freq Control register of each physical cpu package, PRid >= Loongson-3B */ 263extern u64 loongson_freqctrl[MAX_PACKAGES]; 264#define LOONGSON_FREQCTRL(id) (*(volatile u32 *)(loongson_freqctrl[id])) 265 266/* pcimap */ 267 268#define LOONGSON_PCIMAP_PCIMAP_LO0 0x0000003f 269#define LOONGSON_PCIMAP_PCIMAP_LO0_SHIFT 0 270#define LOONGSON_PCIMAP_PCIMAP_LO1 0x00000fc0 271#define LOONGSON_PCIMAP_PCIMAP_LO1_SHIFT 6 272#define LOONGSON_PCIMAP_PCIMAP_LO2 0x0003f000 273#define LOONGSON_PCIMAP_PCIMAP_LO2_SHIFT 12 274#define LOONGSON_PCIMAP_PCIMAP_2 0x00040000 275#define LOONGSON_PCIMAP_WIN(WIN, ADDR) \ 276 ((((ADDR)>>26) & LOONGSON_PCIMAP_PCIMAP_LO0) << ((WIN)*6)) 277 278#ifdef CONFIG_CPU_SUPPORTS_CPUFREQ 279#include <linux/cpufreq.h> 280extern struct cpufreq_frequency_table loongson2_clockmod_table[]; 281#endif 282 283/* 284 * address windows configuration module 285 * 286 * loongson2e do not have this module 287 */ 288#ifdef CONFIG_CPU_SUPPORTS_ADDRWINCFG 289 290/* address window config module base address */ 291#define LOONGSON_ADDRWINCFG_BASE 0x3ff00000ul 292#define LOONGSON_ADDRWINCFG_SIZE 0x180 293 294extern unsigned long _loongson_addrwincfg_base; 295#define LOONGSON_ADDRWINCFG(offset) \ 296 (*(volatile u64 *)(_loongson_addrwincfg_base + (offset))) 297 298#define CPU_WIN0_BASE LOONGSON_ADDRWINCFG(0x00) 299#define CPU_WIN1_BASE LOONGSON_ADDRWINCFG(0x08) 300#define CPU_WIN2_BASE LOONGSON_ADDRWINCFG(0x10) 301#define CPU_WIN3_BASE LOONGSON_ADDRWINCFG(0x18) 302 303#define CPU_WIN0_MASK LOONGSON_ADDRWINCFG(0x20) 304#define CPU_WIN1_MASK LOONGSON_ADDRWINCFG(0x28) 305#define CPU_WIN2_MASK LOONGSON_ADDRWINCFG(0x30) 306#define CPU_WIN3_MASK LOONGSON_ADDRWINCFG(0x38) 307 308#define CPU_WIN0_MMAP LOONGSON_ADDRWINCFG(0x40) 309#define CPU_WIN1_MMAP LOONGSON_ADDRWINCFG(0x48) 310#define CPU_WIN2_MMAP LOONGSON_ADDRWINCFG(0x50) 311#define CPU_WIN3_MMAP LOONGSON_ADDRWINCFG(0x58) 312 313#define PCIDMA_WIN0_BASE LOONGSON_ADDRWINCFG(0x60) 314#define PCIDMA_WIN1_BASE LOONGSON_ADDRWINCFG(0x68) 315#define PCIDMA_WIN2_BASE LOONGSON_ADDRWINCFG(0x70) 316#define PCIDMA_WIN3_BASE LOONGSON_ADDRWINCFG(0x78) 317 318#define PCIDMA_WIN0_MASK LOONGSON_ADDRWINCFG(0x80) 319#define PCIDMA_WIN1_MASK LOONGSON_ADDRWINCFG(0x88) 320#define PCIDMA_WIN2_MASK LOONGSON_ADDRWINCFG(0x90) 321#define PCIDMA_WIN3_MASK LOONGSON_ADDRWINCFG(0x98) 322 323#define PCIDMA_WIN0_MMAP LOONGSON_ADDRWINCFG(0xa0) 324#define PCIDMA_WIN1_MMAP LOONGSON_ADDRWINCFG(0xa8) 325#define PCIDMA_WIN2_MMAP LOONGSON_ADDRWINCFG(0xb0) 326#define PCIDMA_WIN3_MMAP LOONGSON_ADDRWINCFG(0xb8) 327 328#define ADDRWIN_WIN0 0 329#define ADDRWIN_WIN1 1 330#define ADDRWIN_WIN2 2 331#define ADDRWIN_WIN3 3 332 333#define ADDRWIN_MAP_DST_DDR 0 334#define ADDRWIN_MAP_DST_PCI 1 335#define ADDRWIN_MAP_DST_LIO 1 336 337/* 338 * s: CPU, PCIDMA 339 * d: DDR, PCI, LIO 340 * win: 0, 1, 2, 3 341 * src: map source 342 * dst: map destination 343 * size: ~mask + 1 344 */ 345#define LOONGSON_ADDRWIN_CFG(s, d, w, src, dst, size) do {\ 346 s##_WIN##w##_BASE = (src); \ 347 s##_WIN##w##_MMAP = (dst) | ADDRWIN_MAP_DST_##d; \ 348 s##_WIN##w##_MASK = ~(size-1); \ 349} while (0) 350 351#define LOONGSON_ADDRWIN_CPUTOPCI(win, src, dst, size) \ 352 LOONGSON_ADDRWIN_CFG(CPU, PCI, win, src, dst, size) 353#define LOONGSON_ADDRWIN_CPUTODDR(win, src, dst, size) \ 354 LOONGSON_ADDRWIN_CFG(CPU, DDR, win, src, dst, size) 355#define LOONGSON_ADDRWIN_PCITODDR(win, src, dst, size) \ 356 LOONGSON_ADDRWIN_CFG(PCIDMA, DDR, win, src, dst, size) 357 358#endif /* ! CONFIG_CPU_SUPPORTS_ADDRWINCFG */ 359 360#endif /* __ASM_MACH_LOONGSON_LOONGSON_H */ 361