1/ {
2	#address-cells = <1>;
3	#size-cells = <1>;
4	compatible = "brcm,bcm6328";
5
6	cpus {
7		#address-cells = <1>;
8		#size-cells = <0>;
9
10		mips-hpt-frequency = <160000000>;
11
12		cpu@0 {
13			compatible = "brcm,bmips4350";
14			device_type = "cpu";
15			reg = <0>;
16		};
17
18		cpu@1 {
19			compatible = "brcm,bmips4350";
20			device_type = "cpu";
21			reg = <1>;
22		};
23	};
24
25	clocks {
26		periph_clk: periph_clk {
27			compatible = "fixed-clock";
28			#clock-cells = <0>;
29			clock-frequency = <50000000>;
30		};
31	};
32
33	aliases {
34		uart0 = &uart0;
35	};
36
37	cpu_intc: cpu_intc {
38		#address-cells = <0>;
39		compatible = "mti,cpu-interrupt-controller";
40
41		interrupt-controller;
42		#interrupt-cells = <1>;
43	};
44
45	ubus {
46		#address-cells = <1>;
47		#size-cells = <1>;
48
49		compatible = "simple-bus";
50		ranges;
51
52		periph_intc: periph_intc@10000020 {
53			compatible = "brcm,bcm3380-l2-intc";
54			reg = <0x10000024 0x4 0x1000002c 0x4>,
55			      <0x10000020 0x4 0x10000028 0x4>;
56
57			interrupt-controller;
58			#interrupt-cells = <1>;
59
60			interrupt-parent = <&cpu_intc>;
61			interrupts = <2>;
62		};
63
64		uart0: serial@10000100 {
65			compatible = "brcm,bcm6345-uart";
66			reg = <0x10000100 0x18>;
67			interrupt-parent = <&periph_intc>;
68			interrupts = <28>;
69			clocks = <&periph_clk>;
70			status = "disabled";
71		};
72
73		timer: timer@10000040 {
74			compatible = "syscon";
75			reg = <0x10000040 0x2c>;
76			little-endian;
77		};
78
79		reboot {
80			compatible = "syscon-reboot";
81			regmap = <&timer>;
82			offset = <0x28>;
83			mask = <0x1>;
84		};
85	};
86};
87