1/*
2 * General Purpose functions for the global management of the
3 * Communication Processor Module.
4 *
5 * Copyright (c) 2000 Michael Leslie <mleslie@lineo.com>
6 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
7 *
8 * In addition to the individual control of the communication
9 * channels, there are a few functions that globally affect the
10 * communication processor.
11 *
12 * Buffer descriptors must be allocated from the dual ported memory
13 * space.  The allocator for that is here.  When the communication
14 * process is reset, we reclaim the memory available.  There is
15 * currently no deallocator for this memory.
16 * The amount of space available is platform dependent.  On the
17 * MBX, the EPPC software loads additional microcode into the
18 * communication processor, and uses some of the DP ram for this
19 * purpose.  Current, the first 512 bytes and the last 256 bytes of
20 * memory are used.  Right now I am conservative and only use the
21 * memory that can never be used for microcode.  If there are
22 * applications that require more DP ram, we can expand the boundaries
23 * but then we have to be careful of any downloaded microcode.
24 *
25 */
26
27/*
28 * Michael Leslie <mleslie@lineo.com>
29 * adapted Dan Malek's ppc8xx drivers to M68360
30 *
31 */
32
33#include <linux/errno.h>
34#include <linux/init.h>
35#include <linux/sched.h>
36#include <linux/kernel.h>
37#include <linux/param.h>
38#include <linux/string.h>
39#include <linux/mm.h>
40#include <linux/interrupt.h>
41#include <asm/irq.h>
42#include <asm/m68360.h>
43#include <asm/commproc.h>
44
45/* #include <asm/page.h> */
46/* #include <asm/pgtable.h> */
47extern void *_quicc_base;
48extern unsigned int system_clock;
49
50
51static uint dp_alloc_base;	/* Starting offset in DP ram */
52static uint dp_alloc_top;	/* Max offset + 1 */
53
54#if 0
55static	void	*host_buffer;	/* One page of host buffer */
56static	void	*host_end;	    /* end + 1 */
57#endif
58
59/* struct  cpm360_t *cpmp; */         /* Pointer to comm processor space */
60
61QUICC  *pquicc;
62/* QUICC  *quicc_dpram; */ /* mleslie - temporary; use extern pquicc elsewhere instead */
63
64
65/* CPM interrupt vector functions. */
66struct	cpm_action {
67	irq_handler_t	handler;
68	void		*dev_id;
69};
70static	struct	cpm_action cpm_vecs[CPMVEC_NR];
71static	void	cpm_interrupt(int irq, void * dev, struct pt_regs * regs);
72static	void	cpm_error_interrupt(void *);
73
74/* prototypes: */
75void cpm_install_handler(int vec, irq_handler_t handler, void *dev_id);
76void m360_cpm_reset(void);
77
78
79
80
81void __init m360_cpm_reset()
82{
83/* 	pte_t		   *pte; */
84
85	pquicc = (struct quicc *)(_quicc_base); /* initialized in crt0_rXm.S */
86
87	/* Perform a CPM reset. */
88	pquicc->cp_cr = (SOFTWARE_RESET | CMD_FLAG);
89
90	/* Wait for CPM to become ready (should be 2 clocks). */
91	while (pquicc->cp_cr & CMD_FLAG);
92
93	/* On the recommendation of the 68360 manual, p. 7-60
94	 * - Set sdma interrupt service mask to 7
95	 * - Set sdma arbitration ID to 4
96	 */
97	pquicc->sdma_sdcr = 0x0740;
98
99
100	/* Claim the DP memory for our use.
101	 */
102	dp_alloc_base = CPM_DATAONLY_BASE;
103	dp_alloc_top = dp_alloc_base + CPM_DATAONLY_SIZE;
104
105
106	/* Set the host page for allocation.
107	 */
108	/* 	host_buffer = host_page_addr; */
109	/* 	host_end = host_page_addr + PAGE_SIZE; */
110
111	/* 	pte = find_pte(&init_mm, host_page_addr); */
112	/* 	pte_val(*pte) |= _PAGE_NO_CACHE; */
113	/* 	flush_tlb_page(current->mm->mmap, host_buffer); */
114
115	/* Tell everyone where the comm processor resides.
116	*/
117/* 	cpmp = (cpm360_t *)commproc; */
118}
119
120
121/* This is called during init_IRQ.  We used to do it above, but this
122 * was too early since init_IRQ was not yet called.
123 */
124void
125cpm_interrupt_init(void)
126{
127	/* Initialize the CPM interrupt controller.
128	 * NOTE THAT pquicc had better have been initialized!
129	 * reference: MC68360UM p. 7-377
130	 */
131	pquicc->intr_cicr =
132		(CICR_SCD_SCC4 | CICR_SCC_SCC3 | CICR_SCB_SCC2 | CICR_SCA_SCC1) |
133		(CPM_INTERRUPT << 13) |
134		CICR_HP_MASK |
135		(CPM_VECTOR_BASE << 5) |
136		CICR_SPS;
137
138	/* mask all CPM interrupts from reaching the cpu32 core: */
139	pquicc->intr_cimr = 0;
140
141
142	/* mles - If I understand correctly, the 360 just pops over to the CPM
143	 * specific vector, obviating the necessity to vector through the IRQ
144	 * whose priority the CPM is set to. This needs a closer look, though.
145	 */
146
147	/* Set our interrupt handler with the core CPU. */
148/* 	if (request_irq(CPM_INTERRUPT, cpm_interrupt, 0, "cpm", NULL) != 0) */
149/* 		panic("Could not allocate CPM IRQ!"); */
150
151	/* Install our own error handler.
152	 */
153	/* I think we want to hold off on this one for the moment - mles */
154	/* cpm_install_handler(CPMVEC_ERROR, cpm_error_interrupt, NULL); */
155
156	/* master CPM interrupt enable */
157	/* pquicc->intr_cicr |= CICR_IEN; */ /* no such animal for 360 */
158}
159
160
161
162/* CPM interrupt controller interrupt.
163*/
164static	void
165cpm_interrupt(int irq, void * dev, struct pt_regs * regs)
166{
167	/* uint	vec; */
168
169	/* mles: Note that this stuff is currently being performed by
170	 * M68360_do_irq(int vec, struct pt_regs *fp), in ../ints.c  */
171
172	/* figure out the vector */
173	/* call that vector's handler */
174	/* clear the irq's bit in the service register */
175
176#if 0 /* old 860 stuff: */
177	/* Get the vector by setting the ACK bit and then reading
178	 * the register.
179	 */
180	((volatile immap_t *)IMAP_ADDR)->im_cpic.cpic_civr = 1;
181	vec = ((volatile immap_t *)IMAP_ADDR)->im_cpic.cpic_civr;
182	vec >>= 11;
183
184
185	if (cpm_vecs[vec].handler != 0)
186		(*cpm_vecs[vec].handler)(cpm_vecs[vec].dev_id);
187	else
188		((immap_t *)IMAP_ADDR)->im_cpic.cpic_cimr &= ~(1 << vec);
189
190	/* After servicing the interrupt, we have to remove the status
191	 * indicator.
192	 */
193	((immap_t *)IMAP_ADDR)->im_cpic.cpic_cisr |= (1 << vec);
194#endif
195
196}
197
198/* The CPM can generate the error interrupt when there is a race condition
199 * between generating and masking interrupts.  All we have to do is ACK it
200 * and return.  This is a no-op function so we don't need any special
201 * tests in the interrupt handler.
202 */
203static	void
204cpm_error_interrupt(void *dev)
205{
206}
207
208/* Install a CPM interrupt handler.
209*/
210void
211cpm_install_handler(int vec, irq_handler_t handler, void *dev_id)
212{
213
214	request_irq(vec, handler, 0, "timer", dev_id);
215
216/* 	if (cpm_vecs[vec].handler != 0) */
217/* 		printk(KERN_INFO "CPM interrupt %x replacing %x\n", */
218/* 			(uint)handler, (uint)cpm_vecs[vec].handler); */
219/* 	cpm_vecs[vec].handler = handler; */
220/* 	cpm_vecs[vec].dev_id = dev_id; */
221
222	/*              ((immap_t *)IMAP_ADDR)->im_cpic.cpic_cimr |= (1 << vec); */
223/* 	pquicc->intr_cimr |= (1 << vec); */
224
225}
226
227/* Free a CPM interrupt handler.
228*/
229void
230cpm_free_handler(int vec)
231{
232	cpm_vecs[vec].handler = NULL;
233	cpm_vecs[vec].dev_id = NULL;
234	/* ((immap_t *)IMAP_ADDR)->im_cpic.cpic_cimr &= ~(1 << vec); */
235	pquicc->intr_cimr &= ~(1 << vec);
236}
237
238
239
240
241/* Allocate some memory from the dual ported ram.  We may want to
242 * enforce alignment restrictions, but right now everyone is a good
243 * citizen.
244 */
245uint
246m360_cpm_dpalloc(uint size)
247{
248        uint    retloc;
249
250        if ((dp_alloc_base + size) >= dp_alloc_top)
251                return(CPM_DP_NOSPACE);
252
253        retloc = dp_alloc_base;
254        dp_alloc_base += size;
255
256        return(retloc);
257}
258
259
260#if 0 /* mleslie - for now these are simply kmalloc'd */
261/* We also own one page of host buffer space for the allocation of
262 * UART "fifos" and the like.
263 */
264uint
265m360_cpm_hostalloc(uint size)
266{
267	uint	retloc;
268
269	if ((host_buffer + size) >= host_end)
270		return(0);
271
272	retloc = host_buffer;
273	host_buffer += size;
274
275	return(retloc);
276}
277#endif
278
279
280/* Set a baud rate generator.  This needs lots of work.  There are
281 * four BRGs, any of which can be wired to any channel.
282 * The internal baud rate clock is the system clock divided by 16.
283 * This assumes the baudrate is 16x oversampled by the uart.
284 */
285/* #define BRG_INT_CLK	(((bd_t *)__res)->bi_intfreq * 1000000) */
286#define BRG_INT_CLK		system_clock
287#define BRG_UART_CLK	(BRG_INT_CLK/16)
288
289void
290m360_cpm_setbrg(uint brg, uint rate)
291{
292	volatile uint	*bp;
293
294	/* This is good enough to get SMCs running.....
295	 */
296	/* bp = (uint *)&cpmp->cp_brgc1; */
297	bp = (volatile uint *)(&pquicc->brgc[0].l);
298	bp += brg;
299	*bp = ((BRG_UART_CLK / rate - 1) << 1) | CPM_BRG_EN;
300}
301
302
303/*
304 * Local variables:
305 *  c-indent-level: 4
306 *  c-basic-offset: 4
307 *  tab-width: 4
308 * End:
309 */
310