1/*
2 *  linux/arch/m32r/platforms/m32700ut/setup.c
3 *
4 *  Setup routines for Renesas M32700UT Board
5 *
6 *  Copyright (c) 2002-2005  Hiroyuki Kondo, Hirokazu Takata,
7 *                           Hitoshi Yamamoto, Takeo Takahashi
8 *
9 *  This file is subject to the terms and conditions of the GNU General
10 *  Public License.  See the file "COPYING" in the main directory of this
11 *  archive for more details.
12 */
13
14#include <linux/irq.h>
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/platform_device.h>
18
19#include <asm/m32r.h>
20#include <asm/io.h>
21
22/*
23 * M32700 Interrupt Control Unit (Level 1)
24 */
25#define irq2port(x) (M32R_ICU_CR1_PORTL + ((x - 1) * sizeof(unsigned long)))
26
27icu_data_t icu_data[M32700UT_NUM_CPU_IRQ];
28
29static void disable_m32700ut_irq(unsigned int irq)
30{
31	unsigned long port, data;
32
33	port = irq2port(irq);
34	data = icu_data[irq].icucr|M32R_ICUCR_ILEVEL7;
35	outl(data, port);
36}
37
38static void enable_m32700ut_irq(unsigned int irq)
39{
40	unsigned long port, data;
41
42	port = irq2port(irq);
43	data = icu_data[irq].icucr|M32R_ICUCR_IEN|M32R_ICUCR_ILEVEL6;
44	outl(data, port);
45}
46
47static void mask_m32700ut(struct irq_data *data)
48{
49	disable_m32700ut_irq(data->irq);
50}
51
52static void unmask_m32700ut(struct irq_data *data)
53{
54	enable_m32700ut_irq(data->irq);
55}
56
57static void shutdown_m32700ut(struct irq_data *data)
58{
59	unsigned long port;
60
61	port = irq2port(data->irq);
62	outl(M32R_ICUCR_ILEVEL7, port);
63}
64
65static struct irq_chip m32700ut_irq_type =
66{
67	.name		= "M32700UT-IRQ",
68	.irq_shutdown	= shutdown_m32700ut,
69	.irq_mask	= mask_m32700ut,
70	.irq_unmask	= unmask_m32700ut
71};
72
73/*
74 * Interrupt Control Unit of PLD on M32700UT (Level 2)
75 */
76#define irq2pldirq(x)		((x) - M32700UT_PLD_IRQ_BASE)
77#define pldirq2port(x)		(unsigned long)((int)PLD_ICUCR1 + \
78				 (((x) - 1) * sizeof(unsigned short)))
79
80typedef struct {
81	unsigned short icucr;  /* ICU Control Register */
82} pld_icu_data_t;
83
84static pld_icu_data_t pld_icu_data[M32700UT_NUM_PLD_IRQ];
85
86static void disable_m32700ut_pld_irq(unsigned int irq)
87{
88	unsigned long port, data;
89	unsigned int pldirq;
90
91	pldirq = irq2pldirq(irq);
92	port = pldirq2port(pldirq);
93	data = pld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7;
94	outw(data, port);
95}
96
97static void enable_m32700ut_pld_irq(unsigned int irq)
98{
99	unsigned long port, data;
100	unsigned int pldirq;
101
102	pldirq = irq2pldirq(irq);
103	port = pldirq2port(pldirq);
104	data = pld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6;
105	outw(data, port);
106}
107
108static void mask_m32700ut_pld(struct irq_data *data)
109{
110	disable_m32700ut_pld_irq(data->irq);
111}
112
113static void unmask_m32700ut_pld(struct irq_data *data)
114{
115	enable_m32700ut_pld_irq(data->irq);
116	enable_m32700ut_irq(M32R_IRQ_INT1);
117}
118
119static void shutdown_m32700ut_pld_irq(struct irq_data *data)
120{
121	unsigned long port;
122	unsigned int pldirq;
123
124	pldirq = irq2pldirq(data->irq);
125	port = pldirq2port(pldirq);
126	outw(PLD_ICUCR_ILEVEL7, port);
127}
128
129static struct irq_chip m32700ut_pld_irq_type =
130{
131	.name		= "M32700UT-PLD-IRQ",
132	.irq_shutdown	= shutdown_m32700ut_pld_irq,
133	.irq_mask	= mask_m32700ut_pld,
134	.irq_unmask	= unmask_m32700ut_pld,
135};
136
137/*
138 * Interrupt Control Unit of PLD on M32700UT-LAN (Level 2)
139 */
140#define irq2lanpldirq(x)	((x) - M32700UT_LAN_PLD_IRQ_BASE)
141#define lanpldirq2port(x)	(unsigned long)((int)M32700UT_LAN_ICUCR1 + \
142				 (((x) - 1) * sizeof(unsigned short)))
143
144static pld_icu_data_t lanpld_icu_data[M32700UT_NUM_LAN_PLD_IRQ];
145
146static void disable_m32700ut_lanpld_irq(unsigned int irq)
147{
148	unsigned long port, data;
149	unsigned int pldirq;
150
151	pldirq = irq2lanpldirq(irq);
152	port = lanpldirq2port(pldirq);
153	data = lanpld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7;
154	outw(data, port);
155}
156
157static void enable_m32700ut_lanpld_irq(unsigned int irq)
158{
159	unsigned long port, data;
160	unsigned int pldirq;
161
162	pldirq = irq2lanpldirq(irq);
163	port = lanpldirq2port(pldirq);
164	data = lanpld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6;
165	outw(data, port);
166}
167
168static void mask_m32700ut_lanpld(struct irq_data *data)
169{
170	disable_m32700ut_lanpld_irq(data->irq);
171}
172
173static void unmask_m32700ut_lanpld(struct irq_data *data)
174{
175	enable_m32700ut_lanpld_irq(data->irq);
176	enable_m32700ut_irq(M32R_IRQ_INT0);
177}
178
179static void shutdown_m32700ut_lanpld(struct irq_data *data)
180{
181	unsigned long port;
182	unsigned int pldirq;
183
184	pldirq = irq2lanpldirq(data->irq);
185	port = lanpldirq2port(pldirq);
186	outw(PLD_ICUCR_ILEVEL7, port);
187}
188
189static struct irq_chip m32700ut_lanpld_irq_type =
190{
191	.name		= "M32700UT-PLD-LAN-IRQ",
192	.irq_shutdown	= shutdown_m32700ut_lanpld,
193	.irq_mask	= mask_m32700ut_lanpld,
194	.irq_unmask	= unmask_m32700ut_lanpld,
195};
196
197/*
198 * Interrupt Control Unit of PLD on M32700UT-LCD (Level 2)
199 */
200#define irq2lcdpldirq(x)	((x) - M32700UT_LCD_PLD_IRQ_BASE)
201#define lcdpldirq2port(x)	(unsigned long)((int)M32700UT_LCD_ICUCR1 + \
202				 (((x) - 1) * sizeof(unsigned short)))
203
204static pld_icu_data_t lcdpld_icu_data[M32700UT_NUM_LCD_PLD_IRQ];
205
206static void disable_m32700ut_lcdpld_irq(unsigned int irq)
207{
208	unsigned long port, data;
209	unsigned int pldirq;
210
211	pldirq = irq2lcdpldirq(irq);
212	port = lcdpldirq2port(pldirq);
213	data = lcdpld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7;
214	outw(data, port);
215}
216
217static void enable_m32700ut_lcdpld_irq(unsigned int irq)
218{
219	unsigned long port, data;
220	unsigned int pldirq;
221
222	pldirq = irq2lcdpldirq(irq);
223	port = lcdpldirq2port(pldirq);
224	data = lcdpld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6;
225	outw(data, port);
226}
227
228static void mask_m32700ut_lcdpld(struct irq_data *data)
229{
230	disable_m32700ut_lcdpld_irq(data->irq);
231}
232
233static void unmask_m32700ut_lcdpld(struct irq_data *data)
234{
235	enable_m32700ut_lcdpld_irq(data->irq);
236	enable_m32700ut_irq(M32R_IRQ_INT2);
237}
238
239static void shutdown_m32700ut_lcdpld(struct irq_data *data)
240{
241	unsigned long port;
242	unsigned int pldirq;
243
244	pldirq = irq2lcdpldirq(data->irq);
245	port = lcdpldirq2port(pldirq);
246	outw(PLD_ICUCR_ILEVEL7, port);
247}
248
249static struct irq_chip m32700ut_lcdpld_irq_type =
250{
251	.name		= "M32700UT-PLD-LCD-IRQ",
252	.irq_shutdown	= shutdown_m32700ut_lcdpld,
253	.irq_mask	= mask_m32700ut_lcdpld,
254	.irq_unmask	= unmask_m32700ut_lcdpld,
255};
256
257void __init init_IRQ(void)
258{
259#if defined(CONFIG_SMC91X)
260	/* INT#0: LAN controller on M32700UT-LAN (SMC91C111)*/
261	irq_set_chip_and_handler(M32700UT_LAN_IRQ_LAN,
262				 &m32700ut_lanpld_irq_type, handle_level_irq);
263	lanpld_icu_data[irq2lanpldirq(M32700UT_LAN_IRQ_LAN)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02;	/* "H" edge sense */
264	disable_m32700ut_lanpld_irq(M32700UT_LAN_IRQ_LAN);
265#endif  /* CONFIG_SMC91X */
266
267	/* MFT2 : system timer */
268	irq_set_chip_and_handler(M32R_IRQ_MFT2, &m32700ut_irq_type,
269				 handle_level_irq);
270	icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
271	disable_m32700ut_irq(M32R_IRQ_MFT2);
272
273	/* SIO0 : receive */
274	irq_set_chip_and_handler(M32R_IRQ_SIO0_R, &m32700ut_irq_type,
275				 handle_level_irq);
276	icu_data[M32R_IRQ_SIO0_R].icucr = 0;
277	disable_m32700ut_irq(M32R_IRQ_SIO0_R);
278
279	/* SIO0 : send */
280	irq_set_chip_and_handler(M32R_IRQ_SIO0_S, &m32700ut_irq_type,
281				 handle_level_irq);
282	icu_data[M32R_IRQ_SIO0_S].icucr = 0;
283	disable_m32700ut_irq(M32R_IRQ_SIO0_S);
284
285	/* SIO1 : receive */
286	irq_set_chip_and_handler(M32R_IRQ_SIO1_R, &m32700ut_irq_type,
287				 handle_level_irq);
288	icu_data[M32R_IRQ_SIO1_R].icucr = 0;
289	disable_m32700ut_irq(M32R_IRQ_SIO1_R);
290
291	/* SIO1 : send */
292	irq_set_chip_and_handler(M32R_IRQ_SIO1_S, &m32700ut_irq_type,
293				 handle_level_irq);
294	icu_data[M32R_IRQ_SIO1_S].icucr = 0;
295	disable_m32700ut_irq(M32R_IRQ_SIO1_S);
296
297	/* DMA1 : */
298	irq_set_chip_and_handler(M32R_IRQ_DMA1, &m32700ut_irq_type,
299				 handle_level_irq);
300	icu_data[M32R_IRQ_DMA1].icucr = 0;
301	disable_m32700ut_irq(M32R_IRQ_DMA1);
302
303#ifdef CONFIG_SERIAL_M32R_PLDSIO
304	/* INT#1: SIO0 Receive on PLD */
305	irq_set_chip_and_handler(PLD_IRQ_SIO0_RCV, &m32700ut_pld_irq_type,
306				 handle_level_irq);
307	pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_RCV)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03;
308	disable_m32700ut_pld_irq(PLD_IRQ_SIO0_RCV);
309
310	/* INT#1: SIO0 Send on PLD */
311	irq_set_chip_and_handler(PLD_IRQ_SIO0_SND, &m32700ut_pld_irq_type,
312				 handle_level_irq);
313	pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_SND)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03;
314	disable_m32700ut_pld_irq(PLD_IRQ_SIO0_SND);
315#endif  /* CONFIG_SERIAL_M32R_PLDSIO */
316
317	/* INT#1: CFC IREQ on PLD */
318	irq_set_chip_and_handler(PLD_IRQ_CFIREQ, &m32700ut_pld_irq_type,
319				 handle_level_irq);
320	pld_icu_data[irq2pldirq(PLD_IRQ_CFIREQ)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01;	/* 'L' level sense */
321	disable_m32700ut_pld_irq(PLD_IRQ_CFIREQ);
322
323	/* INT#1: CFC Insert on PLD */
324	irq_set_chip_and_handler(PLD_IRQ_CFC_INSERT, &m32700ut_pld_irq_type,
325				 handle_level_irq);
326	pld_icu_data[irq2pldirq(PLD_IRQ_CFC_INSERT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD00;	/* 'L' edge sense */
327	disable_m32700ut_pld_irq(PLD_IRQ_CFC_INSERT);
328
329	/* INT#1: CFC Eject on PLD */
330	irq_set_chip_and_handler(PLD_IRQ_CFC_EJECT, &m32700ut_pld_irq_type,
331				 handle_level_irq);
332	pld_icu_data[irq2pldirq(PLD_IRQ_CFC_EJECT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02;	/* 'H' edge sense */
333	disable_m32700ut_pld_irq(PLD_IRQ_CFC_EJECT);
334
335	/*
336	 * INT0# is used for LAN, DIO
337	 * We enable it here.
338	 */
339	icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD11;
340	enable_m32700ut_irq(M32R_IRQ_INT0);
341
342	/*
343	 * INT1# is used for UART, MMC, CF Controller in FPGA.
344	 * We enable it here.
345	 */
346	icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD11;
347	enable_m32700ut_irq(M32R_IRQ_INT1);
348
349#if defined(CONFIG_USB)
350	outw(USBCR_OTGS, USBCR); 	/* USBCR: non-OTG */
351	irq_set_chip_and_handler(M32700UT_LCD_IRQ_USB_INT1,
352				 &m32700ut_lcdpld_irq_type, handle_level_irq);
353
354	lcdpld_icu_data[irq2lcdpldirq(M32700UT_LCD_IRQ_USB_INT1)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01;	/* "L" level sense */
355	disable_m32700ut_lcdpld_irq(M32700UT_LCD_IRQ_USB_INT1);
356#endif
357	/*
358	 * INT2# is used for BAT, USB, AUDIO
359	 * We enable it here.
360	 */
361	icu_data[M32R_IRQ_INT2].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD01;
362	enable_m32700ut_irq(M32R_IRQ_INT2);
363
364#if defined(CONFIG_VIDEO_M32R_AR)
365	/*
366	 * INT3# is used for AR
367	 */
368	irq_set_chip_and_handler(M32R_IRQ_INT3, &m32700ut_irq_type,
369				 handle_level_irq);
370	icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
371	disable_m32700ut_irq(M32R_IRQ_INT3);
372#endif	/* CONFIG_VIDEO_M32R_AR */
373}
374
375#if defined(CONFIG_SMC91X)
376
377#define LAN_IOSTART     0x300
378#define LAN_IOEND       0x320
379static struct resource smc91x_resources[] = {
380	[0] = {
381		.start  = (LAN_IOSTART),
382		.end    = (LAN_IOEND),
383		.flags  = IORESOURCE_MEM,
384	},
385	[1] = {
386		.start  = M32700UT_LAN_IRQ_LAN,
387		.end    = M32700UT_LAN_IRQ_LAN,
388		.flags  = IORESOURCE_IRQ,
389	}
390};
391
392static struct platform_device smc91x_device = {
393	.name		= "smc91x",
394	.id		= 0,
395	.num_resources  = ARRAY_SIZE(smc91x_resources),
396	.resource       = smc91x_resources,
397};
398#endif
399
400#if defined(CONFIG_FB_S1D13XXX)
401
402#include <video/s1d13xxxfb.h>
403#include <asm/s1d13806.h>
404
405static struct s1d13xxxfb_pdata s1d13xxxfb_data = {
406	.initregs		= s1d13xxxfb_initregs,
407	.initregssize		= ARRAY_SIZE(s1d13xxxfb_initregs),
408	.platform_init_video	= NULL,
409#ifdef CONFIG_PM
410	.platform_suspend_video	= NULL,
411	.platform_resume_video	= NULL,
412#endif
413};
414
415static struct resource s1d13xxxfb_resources[] = {
416	[0] = {
417		.start  = 0x10600000UL,
418		.end    = 0x1073FFFFUL,
419		.flags  = IORESOURCE_MEM,
420	},
421	[1] = {
422		.start  = 0x10400000UL,
423		.end    = 0x104001FFUL,
424		.flags  = IORESOURCE_MEM,
425	}
426};
427
428static struct platform_device s1d13xxxfb_device = {
429	.name		= S1D_DEVICENAME,
430	.id		= 0,
431	.dev            = {
432		.platform_data  = &s1d13xxxfb_data,
433	},
434	.num_resources  = ARRAY_SIZE(s1d13xxxfb_resources),
435	.resource       = s1d13xxxfb_resources,
436};
437#endif
438
439static int __init platform_init(void)
440{
441#if defined(CONFIG_SMC91X)
442	platform_device_register(&smc91x_device);
443#endif
444#if defined(CONFIG_FB_S1D13XXX)
445	platform_device_register(&s1d13xxxfb_device);
446#endif
447	return 0;
448}
449arch_initcall(platform_init);
450