1/* mach/dma.h - arch-specific DMA defines 2 * 3 * Copyright 2004-2008 Analog Devices Inc. 4 * 5 * Licensed under the GPL-2 or later. 6 */ 7 8#ifndef _MACH_DMA_H_ 9#define _MACH_DMA_H_ 10 11#define CH_SPORT0_RX 0 12#define CH_SPORT0_TX 1 13#define CH_SPORT1_RX 2 14#define CH_SPORT1_TX 3 15#define CH_SPI0 4 16#define CH_SPI1 5 17#define CH_UART0_RX 6 18#define CH_UART0_TX 7 19#define CH_UART1_RX 8 20#define CH_UART1_TX 9 21#define CH_ATAPI_RX 10 22#define CH_ATAPI_TX 11 23#define CH_EPPI0 12 24#define CH_EPPI1 13 25#define CH_EPPI2 14 26#define CH_PIXC_IMAGE 15 27#define CH_PIXC_OVERLAY 16 28#define CH_PIXC_OUTPUT 17 29#define CH_SPORT2_RX 18 30#define CH_SPORT2_TX 19 31#define CH_SPORT3_RX 20 32#define CH_SPORT3_TX 21 33#define CH_SDH 22 34#define CH_NFC 22 35#define CH_SPI2 23 36 37#if defined(CONFIG_UART2_DMA_RX_ON_DMA13) 38#define CH_UART2_RX 13 39#define IRQ_UART2_RX BFIN_IRQ(37) /* UART2 RX USE EPP1 (DMA13) Interrupt */ 40#define CH_UART2_TX 14 41#define IRQ_UART2_TX BFIN_IRQ(38) /* UART2 RX USE EPP1 (DMA14) Interrupt */ 42#else /* Default USE SPORT2's DMA Channel */ 43#define CH_UART2_RX 18 44#define IRQ_UART2_RX BFIN_IRQ(33) /* UART2 RX (DMA18) Interrupt */ 45#define CH_UART2_TX 19 46#define IRQ_UART2_TX BFIN_IRQ(34) /* UART2 TX (DMA19) Interrupt */ 47#endif 48 49#if defined(CONFIG_UART3_DMA_RX_ON_DMA15) 50#define CH_UART3_RX 15 51#define IRQ_UART3_RX BFIN_IRQ(64) /* UART3 RX USE PIXC IN0 (DMA15) Interrupt */ 52#define CH_UART3_TX 16 53#define IRQ_UART3_TX BFIN_IRQ(65) /* UART3 TX USE PIXC IN1 (DMA16) Interrupt */ 54#else /* Default USE SPORT3's DMA Channel */ 55#define CH_UART3_RX 20 56#define IRQ_UART3_RX BFIN_IRQ(35) /* UART3 RX (DMA20) Interrupt */ 57#define CH_UART3_TX 21 58#define IRQ_UART3_TX BFIN_IRQ(36) /* UART3 TX (DMA21) Interrupt */ 59#endif 60 61#define CH_MEM_STREAM0_DEST 24 62#define CH_MEM_STREAM0_SRC 25 63#define CH_MEM_STREAM1_DEST 26 64#define CH_MEM_STREAM1_SRC 27 65#define CH_MEM_STREAM2_DEST 28 66#define CH_MEM_STREAM2_SRC 29 67#define CH_MEM_STREAM3_DEST 30 68#define CH_MEM_STREAM3_SRC 31 69 70#define MAX_DMA_CHANNELS 32 71 72#endif 73