1/* 2 * Common Blackfin IRQ definitions (i.e. the CEC) 3 * 4 * Copyright 2005-2011 Analog Devices Inc. 5 * 6 * Licensed under the GPL-2 or later 7 */ 8 9#ifndef _MACH_COMMON_IRQ_H_ 10#define _MACH_COMMON_IRQ_H_ 11 12/* 13 * Core events interrupt source definitions 14 * 15 * Event Source Event Name 16 * Emulation EMU 0 (highest priority) 17 * Reset RST 1 18 * NMI NMI 2 19 * Exception EVX 3 20 * Reserved -- 4 21 * Hardware Error IVHW 5 22 * Core Timer IVTMR 6 23 * Peripherals IVG7 7 24 * Peripherals IVG8 8 25 * Peripherals IVG9 9 26 * Peripherals IVG10 10 27 * Peripherals IVG11 11 28 * Peripherals IVG12 12 29 * Peripherals IVG13 13 30 * Softirq IVG14 14 31 * System Call IVG15 15 (lowest priority) 32 */ 33 34/* The ABSTRACT IRQ definitions */ 35#define IRQ_EMU 0 /* Emulation */ 36#define IRQ_RST 1 /* reset */ 37#define IRQ_NMI 2 /* Non Maskable */ 38#define IRQ_EVX 3 /* Exception */ 39#define IRQ_UNUSED 4 /* - unused interrupt */ 40#define IRQ_HWERR 5 /* Hardware Error */ 41#define IRQ_CORETMR 6 /* Core timer */ 42 43#define IVG7 7 44#define IVG8 8 45#define IVG9 9 46#define IVG10 10 47#define IVG11 11 48#define IVG12 12 49#define IVG13 13 50#define IVG14 14 51#define IVG15 15 52 53#define BFIN_IRQ(x) ((x) + IVG7) 54#define BFIN_SYSIRQ(x) ((x) - IVG7) 55 56#define NR_IRQS (NR_MACH_IRQS + NR_SPARE_IRQS) 57 58#endif 59