1/* 2 * bfin_ppi.h - interface to Blackfin PPIs 3 * 4 * Copyright 2005-2010 Analog Devices Inc. 5 * 6 * Licensed under the GPL-2 or later. 7 */ 8 9#ifndef __ASM_BFIN_PPI_H__ 10#define __ASM_BFIN_PPI_H__ 11 12#include <linux/types.h> 13#include <asm/blackfin.h> 14 15/* 16 * All Blackfin system MMRs are padded to 32bits even if the register 17 * itself is only 16bits. So use a helper macro to streamline this. 18 */ 19#define __BFP(m) u16 m; u16 __pad_##m 20 21/* 22 * bfin ppi registers layout 23 */ 24struct bfin_ppi_regs { 25 __BFP(control); 26 __BFP(status); 27 __BFP(count); 28 __BFP(delay); 29 __BFP(frame); 30}; 31 32/* 33 * bfin eppi registers layout 34 */ 35struct bfin_eppi_regs { 36 __BFP(status); 37 __BFP(hcount); 38 __BFP(hdelay); 39 __BFP(vcount); 40 __BFP(vdelay); 41 __BFP(frame); 42 __BFP(line); 43 __BFP(clkdiv); 44 u32 control; 45 u32 fs1w_hbl; 46 u32 fs1p_avpl; 47 u32 fs2w_lvb; 48 u32 fs2p_lavf; 49 u32 clip; 50}; 51 52/* 53 * bfin eppi3 registers layout 54 */ 55struct bfin_eppi3_regs { 56 u32 stat; 57 u32 hcnt; 58 u32 hdly; 59 u32 vcnt; 60 u32 vdly; 61 u32 frame; 62 u32 line; 63 u32 clkdiv; 64 u32 ctl; 65 u32 fs1_wlhb; 66 u32 fs1_paspl; 67 u32 fs2_wlvb; 68 u32 fs2_palpf; 69 u32 imsk; 70 u32 oddclip; 71 u32 evenclip; 72 u32 fs1_dly; 73 u32 fs2_dly; 74 u32 ctl2; 75}; 76 77#undef __BFP 78 79#ifdef EPPI0_CTL2 80#define EPPI_STAT_CFIFOERR 0x00000001 /* Chroma FIFO Error */ 81#define EPPI_STAT_YFIFOERR 0x00000002 /* Luma FIFO Error */ 82#define EPPI_STAT_LTERROVR 0x00000004 /* Line Track Overflow */ 83#define EPPI_STAT_LTERRUNDR 0x00000008 /* Line Track Underflow */ 84#define EPPI_STAT_FTERROVR 0x00000010 /* Frame Track Overflow */ 85#define EPPI_STAT_FTERRUNDR 0x00000020 /* Frame Track Underflow */ 86#define EPPI_STAT_ERRNCOR 0x00000040 /* Preamble Error Not Corrected */ 87#define EPPI_STAT_PXPERR 0x00000080 /* PxP Ready Error */ 88#define EPPI_STAT_ERRDET 0x00004000 /* Preamble Error Detected */ 89#define EPPI_STAT_FLD 0x00008000 /* Current Field Received by EPPI */ 90 91#define EPPI_HCNT_VALUE 0x0000FFFF /* Holds the number of samples to read in or write out per line, after PPIx_HDLY number of cycles have expired since the last assertion of PPIx_FS1 */ 92 93#define EPPI_HDLY_VALUE 0x0000FFFF /* Number of PPIx_CLK cycles to delay after assertion of PPIx_FS1 before starting to read or write data */ 94 95#define EPPI_VCNT_VALUE 0x0000FFFF /* Holds the number of lines to read in or write out, after PPIx_VDLY number of lines from the start of frame */ 96 97#define EPPI_VDLY_VALUE 0x0000FFFF /* Number of lines to wait after the start of a new frame before starting to read/transmit data */ 98 99#define EPPI_FRAME_VALUE 0x0000FFFF /* Holds the number of lines expected per frame of data */ 100 101#define EPPI_LINE_VALUE 0x0000FFFF /* Holds the number of samples expected per line */ 102 103#define EPPI_CLKDIV_VALUE 0x0000FFFF /* Internal clock divider */ 104 105#define EPPI_CTL_EN 0x00000001 /* PPI Enable */ 106#define EPPI_CTL_DIR 0x00000002 /* PPI Direction */ 107#define EPPI_CTL_XFRTYPE 0x0000000C /* PPI Operating Mode */ 108#define EPPI_CTL_ACTIVE656 0x00000000 /* XFRTYPE: ITU656 Active Video Only Mode */ 109#define EPPI_CTL_ENTIRE656 0x00000004 /* XFRTYPE: ITU656 Entire Field Mode */ 110#define EPPI_CTL_VERT656 0x00000008 /* XFRTYPE: ITU656 Vertical Blanking Only Mode */ 111#define EPPI_CTL_NON656 0x0000000C /* XFRTYPE: Non-ITU656 Mode (GP Mode) */ 112#define EPPI_CTL_FSCFG 0x00000030 /* Frame Sync Configuration */ 113#define EPPI_CTL_SYNC0 0x00000000 /* FSCFG: Sync Mode 0 */ 114#define EPPI_CTL_SYNC1 0x00000010 /* FSCFG: Sync Mode 1 */ 115#define EPPI_CTL_SYNC2 0x00000020 /* FSCFG: Sync Mode 2 */ 116#define EPPI_CTL_SYNC3 0x00000030 /* FSCFG: Sync Mode 3 */ 117#define EPPI_CTL_FLDSEL 0x00000040 /* Field Select/Trigger */ 118#define EPPI_CTL_ITUTYPE 0x00000080 /* ITU Interlace or Progressive */ 119#define EPPI_CTL_BLANKGEN 0x00000100 /* ITU Output Mode with Internal Blanking Generation */ 120#define EPPI_CTL_ICLKGEN 0x00000200 /* Internal Clock Generation */ 121#define EPPI_CTL_IFSGEN 0x00000400 /* Internal Frame Sync Generation */ 122#define EPPI_CTL_SIGNEXT 0x00000800 /* Sign Extension */ 123#define EPPI_CTL_POLC 0x00003000 /* Frame Sync and Data Driving and Sampling Edges */ 124#define EPPI_CTL_POLC0 0x00000000 /* POLC: Clock/Sync polarity mode 0 */ 125#define EPPI_CTL_POLC1 0x00001000 /* POLC: Clock/Sync polarity mode 1 */ 126#define EPPI_CTL_POLC2 0x00002000 /* POLC: Clock/Sync polarity mode 2 */ 127#define EPPI_CTL_POLC3 0x00003000 /* POLC: Clock/Sync polarity mode 3 */ 128#define EPPI_CTL_POLS 0x0000C000 /* Frame Sync Polarity */ 129#define EPPI_CTL_FS1HI_FS2HI 0x00000000 /* POLS: FS1 and FS2 are active high */ 130#define EPPI_CTL_FS1LO_FS2HI 0x00004000 /* POLS: FS1 is active low. FS2 is active high */ 131#define EPPI_CTL_FS1HI_FS2LO 0x00008000 /* POLS: FS1 is active high. FS2 is active low */ 132#define EPPI_CTL_FS1LO_FS2LO 0x0000C000 /* POLS: FS1 and FS2 are active low */ 133#define EPPI_CTL_DLEN 0x00070000 /* Data Length */ 134#define EPPI_CTL_DLEN08 0x00000000 /* DLEN: 8 bits */ 135#define EPPI_CTL_DLEN10 0x00010000 /* DLEN: 10 bits */ 136#define EPPI_CTL_DLEN12 0x00020000 /* DLEN: 12 bits */ 137#define EPPI_CTL_DLEN14 0x00030000 /* DLEN: 14 bits */ 138#define EPPI_CTL_DLEN16 0x00040000 /* DLEN: 16 bits */ 139#define EPPI_CTL_DLEN18 0x00050000 /* DLEN: 18 bits */ 140#define EPPI_CTL_DLEN20 0x00060000 /* DLEN: 20 bits */ 141#define EPPI_CTL_DLEN24 0x00070000 /* DLEN: 24 bits */ 142#define EPPI_CTL_DMIRR 0x00080000 /* Data Mirroring */ 143#define EPPI_CTL_SKIPEN 0x00100000 /* Skip Enable */ 144#define EPPI_CTL_SKIPEO 0x00200000 /* Skip Even or Odd */ 145#define EPPI_CTL_PACKEN 0x00400000 /* Pack/Unpack Enable */ 146#define EPPI_CTL_SWAPEN 0x00800000 /* Swap Enable */ 147#define EPPI_CTL_SPLTEO 0x01000000 /* Split Even and Odd Data Samples */ 148#define EPPI_CTL_SUBSPLTODD 0x02000000 /* Sub-Split Odd Samples */ 149#define EPPI_CTL_SPLTWRD 0x04000000 /* Split Word */ 150#define EPPI_CTL_RGBFMTEN 0x08000000 /* RGB Formatting Enable */ 151#define EPPI_CTL_DMACFG 0x10000000 /* One or Two DMA Channels Mode */ 152#define EPPI_CTL_DMAFINEN 0x20000000 /* DMA Finish Enable */ 153#define EPPI_CTL_MUXSEL 0x40000000 /* MUX Select */ 154#define EPPI_CTL_CLKGATEN 0x80000000 /* Clock Gating Enable */ 155 156#define EPPI_FS2_WLVB_F2VBAD 0xFF000000 /* In GP transmit mode with BLANKGEN = 1, contains number of lines of vertical blanking after field 2 */ 157#define EPPI_FS2_WLVB_F2VBBD 0x00FF0000 /* In GP transmit mode with BLANKGEN = 1, contains number of lines of vertical blanking before field 2 */ 158#define EPPI_FS2_WLVB_F1VBAD 0x0000FF00 /* In GP transmit mode with, BLANKGEN = 1, contains number of lines of vertical blanking after field 1 */ 159#define EPPI_FS2_WLVB_F1VBBD 0x000000FF /* In GP 2, or 3 FS modes used to generate PPIx_FS2 width (32-bit). In GP Transmit mode, with BLANKGEN=1, contains the number of lines of Vertical blanking before field 1. */ 160 161#define EPPI_FS2_PALPF_F2ACT 0xFFFF0000 /* Number of lines of Active Data in Field 2 */ 162#define EPPI_FS2_PALPF_F1ACT 0x0000FFFF /* Number of lines of Active Data in Field 1 */ 163 164#define EPPI_IMSK_CFIFOERR 0x00000001 /* Mask CFIFO Underflow or Overflow Error Interrupt */ 165#define EPPI_IMSK_YFIFOERR 0x00000002 /* Mask YFIFO Underflow or Overflow Error Interrupt */ 166#define EPPI_IMSK_LTERROVR 0x00000004 /* Mask Line Track Overflow Error Interrupt */ 167#define EPPI_IMSK_LTERRUNDR 0x00000008 /* Mask Line Track Underflow Error Interrupt */ 168#define EPPI_IMSK_FTERROVR 0x00000010 /* Mask Frame Track Overflow Error Interrupt */ 169#define EPPI_IMSK_FTERRUNDR 0x00000020 /* Mask Frame Track Underflow Error Interrupt */ 170#define EPPI_IMSK_ERRNCOR 0x00000040 /* Mask ITU Preamble Error Not Corrected Interrupt */ 171#define EPPI_IMSK_PXPERR 0x00000080 /* Mask PxP Ready Error Interrupt */ 172 173#define EPPI_ODDCLIP_HIGHODD 0xFFFF0000 174#define EPPI_ODDCLIP_LOWODD 0x0000FFFF 175 176#define EPPI_EVENCLIP_HIGHEVEN 0xFFFF0000 177#define EPPI_EVENCLIP_LOWEVEN 0x0000FFFF 178 179#define EPPI_CTL2_FS1FINEN 0x00000002 /* HSYNC Finish Enable */ 180#endif 181#endif 182