1/*
2 * DTS file for AMD Seattle SoC
3 *
4 * Copyright (C) 2014 Advanced Micro Devices, Inc.
5 */
6
7/ {
8	compatible = "amd,seattle";
9	interrupt-parent = <&gic0>;
10	#address-cells = <2>;
11	#size-cells = <2>;
12
13	gic0: interrupt-controller@e1101000 {
14		compatible = "arm,gic-400", "arm,cortex-a15-gic";
15		interrupt-controller;
16		#interrupt-cells = <3>;
17		#address-cells = <2>;
18		#size-cells = <2>;
19		reg = <0x0 0xe1110000 0 0x1000>,
20		      <0x0 0xe112f000 0 0x2000>,
21		      <0x0 0xe1140000 0 0x10000>,
22		      <0x0 0xe1160000 0 0x10000>;
23		interrupts = <1 9 0xf04>;
24		ranges = <0 0 0 0xe1100000 0 0x100000>;
25		v2m0: v2m@e0080000 {
26			compatible = "arm,gic-v2m-frame";
27			msi-controller;
28			reg = <0x0 0x00080000 0 0x1000>;
29		};
30	};
31
32	timer {
33		compatible = "arm,armv8-timer";
34		interrupts = <1 13 0xff04>,
35			     <1 14 0xff04>,
36			     <1 11 0xff04>,
37			     <1 10 0xff04>;
38	};
39
40	pmu {
41		compatible = "arm,armv8-pmuv3";
42		interrupts = <0 7 4>,
43			     <0 8 4>,
44			     <0 9 4>,
45			     <0 10 4>,
46			     <0 11 4>,
47			     <0 12 4>,
48			     <0 13 4>,
49			     <0 14 4>;
50	};
51
52	smb0: smb {
53		compatible = "simple-bus";
54		#address-cells = <2>;
55		#size-cells = <2>;
56		ranges;
57
58		/* DDR range is 40-bit addressing */
59		dma-ranges = <0x80 0x0 0x80 0x0 0x7f 0xffffffff>;
60
61		/include/ "amd-seattle-clks.dtsi"
62
63		sata0: sata@e0300000 {
64			compatible = "snps,dwc-ahci";
65			reg = <0 0xe0300000 0 0x800>;
66			interrupts = <0 355 4>;
67			clocks = <&sataclk_333mhz>;
68			dma-coherent;
69		};
70
71		i2c0: i2c@e1000000 {
72			status = "disabled";
73			compatible = "snps,designware-i2c";
74			reg = <0 0xe1000000 0 0x1000>;
75			interrupts = <0 357 4>;
76			clocks = <&uartspiclk_100mhz>;
77		};
78
79		serial0: serial@e1010000 {
80			compatible = "arm,pl011", "arm,primecell";
81			reg = <0 0xe1010000 0 0x1000>;
82			interrupts = <0 328 4>;
83			clocks = <&uartspiclk_100mhz>, <&uartspiclk_100mhz>;
84			clock-names = "uartclk", "apb_pclk";
85		};
86
87		spi0: ssp@e1020000 {
88			status = "disabled";
89			compatible = "arm,pl022", "arm,primecell";
90			#gpio-cells = <2>;
91			reg = <0 0xe1020000 0 0x1000>;
92			spi-controller;
93			interrupts = <0 330 4>;
94			clocks = <&uartspiclk_100mhz>;
95			clock-names = "apb_pclk";
96		};
97
98		spi1: ssp@e1030000 {
99			status = "disabled";
100			compatible = "arm,pl022", "arm,primecell";
101			#gpio-cells = <2>;
102			reg = <0 0xe1030000 0 0x1000>;
103			spi-controller;
104			interrupts = <0 329 4>;
105			clocks = <&uartspiclk_100mhz>;
106			clock-names = "apb_pclk";
107			num-cs = <1>;
108			#address-cells = <1>;
109			#size-cells = <0>;
110		};
111
112		gpio0: gpio@e1040000 {
113			status = "disabled";
114			compatible = "arm,pl061", "arm,primecell";
115			#gpio-cells = <2>;
116			reg = <0 0xe1040000 0 0x1000>;
117			gpio-controller;
118			interrupts = <0 359 4>;
119			interrupt-controller;
120			#interrupt-cells = <2>;
121			clocks = <&uartspiclk_100mhz>;
122			clock-names = "apb_pclk";
123		};
124
125		gpio1: gpio@e1050000 {
126			status = "disabled";
127			compatible = "arm,pl061", "arm,primecell";
128			#gpio-cells = <2>;
129			reg = <0 0xe1050000 0 0x1000>;
130			gpio-controller;
131			interrupts = <0 358 4>;
132			clocks = <&uartspiclk_100mhz>;
133			clock-names = "apb_pclk";
134		};
135
136		ccp0: ccp@e0100000 {
137			status = "disabled";
138			compatible = "amd,ccp-seattle-v1a";
139			reg = <0 0xe0100000 0 0x10000>;
140			interrupts = <0 3 4>;
141			dma-coherent;
142		};
143
144		pcie0: pcie@f0000000 {
145			compatible = "pci-host-ecam-generic";
146			#address-cells = <3>;
147			#size-cells = <2>;
148			#interrupt-cells = <1>;
149			device_type = "pci";
150			bus-range = <0 0x7f>;
151			msi-parent = <&v2m0>;
152			reg = <0 0xf0000000 0 0x10000000>;
153
154			interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
155			interrupt-map =
156				<0x1000 0x0 0x0 0x1 &gic0 0x0 0x0 0x0 0x120 0x1>,
157				<0x1000 0x0 0x0 0x2 &gic0 0x0 0x0 0x0 0x121 0x1>,
158				<0x1000 0x0 0x0 0x3 &gic0 0x0 0x0 0x0 0x122 0x1>,
159				<0x1000 0x0 0x0 0x4 &gic0 0x0 0x0 0x0 0x123 0x1>;
160
161			dma-coherent;
162			dma-ranges = <0x43000000 0x80 0x0 0x80 0x0 0x7f 0xffffffff>;
163			ranges =
164				/* I/O Memory (size=64K) */
165				<0x01000000 0x00 0x00000000 0x00 0xefff0000 0x00 0x00010000>,
166				/* 32-bit MMIO (size=2G) */
167				<0x02000000 0x00 0x40000000 0x00 0x40000000 0x00 0x80000000>,
168				/* 64-bit MMIO (size= 124G) */
169				<0x03000000 0x01 0x00000000 0x01 0x00000000 0x7f 0x00000000>;
170		};
171	};
172};
173