1config ARM64 2 def_bool y 3 select ACPI_GENERIC_GSI if ACPI 4 select ACPI_REDUCED_HARDWARE_ONLY if ACPI 5 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE 6 select ARCH_HAS_ELF_RANDOMIZE 7 select ARCH_HAS_GCOV_PROFILE_ALL 8 select ARCH_HAS_SG_CHAIN 9 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 10 select ARCH_USE_CMPXCHG_LOCKREF 11 select ARCH_SUPPORTS_ATOMIC_RMW 12 select ARCH_WANT_OPTIONAL_GPIOLIB 13 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION 14 select ARCH_WANT_FRAME_POINTERS 15 select ARM_AMBA 16 select ARM_ARCH_TIMER 17 select ARM_GIC 18 select AUDIT_ARCH_COMPAT_GENERIC 19 select ARM_GIC_V2M if PCI_MSI 20 select ARM_GIC_V3 21 select ARM_GIC_V3_ITS if PCI_MSI 22 select BUILDTIME_EXTABLE_SORT 23 select CLONE_BACKWARDS 24 select COMMON_CLK 25 select CPU_PM if (SUSPEND || CPU_IDLE) 26 select DCACHE_WORD_ACCESS 27 select GENERIC_ALLOCATOR 28 select GENERIC_CLOCKEVENTS 29 select GENERIC_CLOCKEVENTS_BROADCAST if SMP 30 select GENERIC_CPU_AUTOPROBE 31 select GENERIC_EARLY_IOREMAP 32 select GENERIC_IRQ_PROBE 33 select GENERIC_IRQ_SHOW 34 select GENERIC_IRQ_SHOW_LEVEL 35 select GENERIC_PCI_IOMAP 36 select GENERIC_SCHED_CLOCK 37 select GENERIC_SMP_IDLE_THREAD 38 select GENERIC_STRNCPY_FROM_USER 39 select GENERIC_STRNLEN_USER 40 select GENERIC_TIME_VSYSCALL 41 select HANDLE_DOMAIN_IRQ 42 select HARDIRQS_SW_RESEND 43 select HAVE_ALIGNED_STRUCT_PAGE if SLUB 44 select HAVE_ARCH_AUDITSYSCALL 45 select HAVE_ARCH_BITREVERSE 46 select HAVE_ARCH_JUMP_LABEL 47 select HAVE_ARCH_KGDB 48 select HAVE_ARCH_SECCOMP_FILTER 49 select HAVE_ARCH_TRACEHOOK 50 select HAVE_BPF_JIT 51 select HAVE_C_RECORDMCOUNT 52 select HAVE_CC_STACKPROTECTOR 53 select HAVE_CMPXCHG_DOUBLE 54 select HAVE_DEBUG_BUGVERBOSE 55 select HAVE_DEBUG_KMEMLEAK 56 select HAVE_DMA_API_DEBUG 57 select HAVE_DMA_ATTRS 58 select HAVE_DMA_CONTIGUOUS 59 select HAVE_DYNAMIC_FTRACE 60 select HAVE_EFFICIENT_UNALIGNED_ACCESS 61 select HAVE_FTRACE_MCOUNT_RECORD 62 select HAVE_FUNCTION_TRACER 63 select HAVE_FUNCTION_GRAPH_TRACER 64 select HAVE_GENERIC_DMA_COHERENT 65 select HAVE_HW_BREAKPOINT if PERF_EVENTS 66 select HAVE_MEMBLOCK 67 select HAVE_PATA_PLATFORM 68 select HAVE_PERF_EVENTS 69 select HAVE_PERF_REGS 70 select HAVE_PERF_USER_STACK_DUMP 71 select HAVE_RCU_TABLE_FREE 72 select HAVE_SYSCALL_TRACEPOINTS 73 select IRQ_DOMAIN 74 select MODULES_USE_ELF_RELA 75 select NO_BOOTMEM 76 select OF 77 select OF_EARLY_FLATTREE 78 select OF_RESERVED_MEM 79 select PERF_USE_VMALLOC 80 select POWER_RESET 81 select POWER_SUPPLY 82 select RTC_LIB 83 select SPARSE_IRQ 84 select SYSCTL_EXCEPTION_TRACE 85 select HAVE_CONTEXT_TRACKING 86 help 87 ARM 64-bit (AArch64) Linux support. 88 89config 64BIT 90 def_bool y 91 92config ARCH_PHYS_ADDR_T_64BIT 93 def_bool y 94 95config MMU 96 def_bool y 97 98config NO_IOPORT_MAP 99 def_bool y if !PCI 100 101config STACKTRACE_SUPPORT 102 def_bool y 103 104config ILLEGAL_POINTER_VALUE 105 hex 106 default 0xdead000000000000 107 108config LOCKDEP_SUPPORT 109 def_bool y 110 111config TRACE_IRQFLAGS_SUPPORT 112 def_bool y 113 114config RWSEM_XCHGADD_ALGORITHM 115 def_bool y 116 117config GENERIC_HWEIGHT 118 def_bool y 119 120config GENERIC_CSUM 121 def_bool y 122 123config GENERIC_CALIBRATE_DELAY 124 def_bool y 125 126config ZONE_DMA 127 def_bool y 128 129config HAVE_GENERIC_RCU_GUP 130 def_bool y 131 132config ARCH_DMA_ADDR_T_64BIT 133 def_bool y 134 135config NEED_DMA_MAP_STATE 136 def_bool y 137 138config NEED_SG_DMA_LENGTH 139 def_bool y 140 141config SWIOTLB 142 def_bool y 143 144config IOMMU_HELPER 145 def_bool SWIOTLB 146 147config KERNEL_MODE_NEON 148 def_bool y 149 150config FIX_EARLYCON_MEM 151 def_bool y 152 153config PGTABLE_LEVELS 154 int 155 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42 156 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48 157 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39 158 default 4 if ARM64_4K_PAGES && ARM64_VA_BITS_48 159 160source "init/Kconfig" 161 162source "kernel/Kconfig.freezer" 163 164menu "Platform selection" 165 166config ARCH_EXYNOS 167 bool 168 help 169 This enables support for Samsung Exynos SoC family 170 171config ARCH_EXYNOS7 172 bool "ARMv8 based Samsung Exynos7" 173 select ARCH_EXYNOS 174 select COMMON_CLK_SAMSUNG 175 select HAVE_S3C2410_WATCHDOG if WATCHDOG 176 select HAVE_S3C_RTC if RTC_CLASS 177 select PINCTRL 178 select PINCTRL_EXYNOS 179 180 help 181 This enables support for Samsung Exynos7 SoC family 182 183config ARCH_FSL_LS2085A 184 bool "Freescale LS2085A SOC" 185 help 186 This enables support for Freescale LS2085A SOC. 187 188config ARCH_MEDIATEK 189 bool "Mediatek MT65xx & MT81xx ARMv8 SoC" 190 select ARM_GIC 191 select PINCTRL 192 help 193 Support for Mediatek MT65xx & MT81xx ARMv8 SoCs 194 195config ARCH_QCOM 196 bool "Qualcomm Platforms" 197 select PINCTRL 198 help 199 This enables support for the ARMv8 based Qualcomm chipsets. 200 201config ARCH_SEATTLE 202 bool "AMD Seattle SoC Family" 203 help 204 This enables support for AMD Seattle SOC Family 205 206config ARCH_TEGRA 207 bool "NVIDIA Tegra SoC Family" 208 select ARCH_HAS_RESET_CONTROLLER 209 select ARCH_REQUIRE_GPIOLIB 210 select CLKDEV_LOOKUP 211 select CLKSRC_MMIO 212 select CLKSRC_OF 213 select GENERIC_CLOCKEVENTS 214 select HAVE_CLK 215 select PINCTRL 216 select RESET_CONTROLLER 217 help 218 This enables support for the NVIDIA Tegra SoC family. 219 220config ARCH_TEGRA_132_SOC 221 bool "NVIDIA Tegra132 SoC" 222 depends on ARCH_TEGRA 223 select PINCTRL_TEGRA124 224 select USB_ULPI if USB_PHY 225 select USB_ULPI_VIEWPORT if USB_PHY 226 help 227 Enable support for NVIDIA Tegra132 SoC, based on the Denver 228 ARMv8 CPU. The Tegra132 SoC is similar to the Tegra124 SoC, 229 but contains an NVIDIA Denver CPU complex in place of 230 Tegra124's "4+1" Cortex-A15 CPU complex. 231 232config ARCH_SPRD 233 bool "Spreadtrum SoC platform" 234 help 235 Support for Spreadtrum ARM based SoCs 236 237config ARCH_THUNDER 238 bool "Cavium Inc. Thunder SoC Family" 239 help 240 This enables support for Cavium's Thunder Family of SoCs. 241 242config ARCH_VEXPRESS 243 bool "ARMv8 software model (Versatile Express)" 244 select ARCH_REQUIRE_GPIOLIB 245 select COMMON_CLK_VERSATILE 246 select POWER_RESET_VEXPRESS 247 select VEXPRESS_CONFIG 248 help 249 This enables support for the ARMv8 software model (Versatile 250 Express). 251 252config ARCH_XGENE 253 bool "AppliedMicro X-Gene SOC Family" 254 help 255 This enables support for AppliedMicro X-Gene SOC Family 256 257config ARCH_ZYNQMP 258 bool "Xilinx ZynqMP Family" 259 help 260 This enables support for Xilinx ZynqMP Family 261 262endmenu 263 264menu "Bus support" 265 266config PCI 267 bool "PCI support" 268 help 269 This feature enables support for PCI bus system. If you say Y 270 here, the kernel will include drivers and infrastructure code 271 to support PCI bus devices. 272 273config PCI_DOMAINS 274 def_bool PCI 275 276config PCI_DOMAINS_GENERIC 277 def_bool PCI 278 279config PCI_SYSCALL 280 def_bool PCI 281 282source "drivers/pci/Kconfig" 283source "drivers/pci/pcie/Kconfig" 284source "drivers/pci/hotplug/Kconfig" 285 286endmenu 287 288menu "Kernel Features" 289 290menu "ARM errata workarounds via the alternatives framework" 291 292config ARM64_ERRATUM_826319 293 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted" 294 default y 295 help 296 This option adds an alternative code sequence to work around ARM 297 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or 298 AXI master interface and an L2 cache. 299 300 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors 301 and is unable to accept a certain write via this interface, it will 302 not progress on read data presented on the read data channel and the 303 system can deadlock. 304 305 The workaround promotes data cache clean instructions to 306 data cache clean-and-invalidate. 307 Please note that this does not necessarily enable the workaround, 308 as it depends on the alternative framework, which will only patch 309 the kernel if an affected CPU is detected. 310 311 If unsure, say Y. 312 313config ARM64_ERRATUM_827319 314 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect" 315 default y 316 help 317 This option adds an alternative code sequence to work around ARM 318 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI 319 master interface and an L2 cache. 320 321 Under certain conditions this erratum can cause a clean line eviction 322 to occur at the same time as another transaction to the same address 323 on the AMBA 5 CHI interface, which can cause data corruption if the 324 interconnect reorders the two transactions. 325 326 The workaround promotes data cache clean instructions to 327 data cache clean-and-invalidate. 328 Please note that this does not necessarily enable the workaround, 329 as it depends on the alternative framework, which will only patch 330 the kernel if an affected CPU is detected. 331 332 If unsure, say Y. 333 334config ARM64_ERRATUM_824069 335 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop" 336 default y 337 help 338 This option adds an alternative code sequence to work around ARM 339 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected 340 to a coherent interconnect. 341 342 If a Cortex-A53 processor is executing a store or prefetch for 343 write instruction at the same time as a processor in another 344 cluster is executing a cache maintenance operation to the same 345 address, then this erratum might cause a clean cache line to be 346 incorrectly marked as dirty. 347 348 The workaround promotes data cache clean instructions to 349 data cache clean-and-invalidate. 350 Please note that this option does not necessarily enable the 351 workaround, as it depends on the alternative framework, which will 352 only patch the kernel if an affected CPU is detected. 353 354 If unsure, say Y. 355 356config ARM64_ERRATUM_819472 357 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption" 358 default y 359 help 360 This option adds an alternative code sequence to work around ARM 361 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache 362 present when it is connected to a coherent interconnect. 363 364 If the processor is executing a load and store exclusive sequence at 365 the same time as a processor in another cluster is executing a cache 366 maintenance operation to the same address, then this erratum might 367 cause data corruption. 368 369 The workaround promotes data cache clean instructions to 370 data cache clean-and-invalidate. 371 Please note that this does not necessarily enable the workaround, 372 as it depends on the alternative framework, which will only patch 373 the kernel if an affected CPU is detected. 374 375 If unsure, say Y. 376 377config ARM64_ERRATUM_832075 378 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads" 379 default y 380 help 381 This option adds an alternative code sequence to work around ARM 382 erratum 832075 on Cortex-A57 parts up to r1p2. 383 384 Affected Cortex-A57 parts might deadlock when exclusive load/store 385 instructions to Write-Back memory are mixed with Device loads. 386 387 The workaround is to promote device loads to use Load-Acquire 388 semantics. 389 Please note that this does not necessarily enable the workaround, 390 as it depends on the alternative framework, which will only patch 391 the kernel if an affected CPU is detected. 392 393 If unsure, say Y. 394 395config ARM64_ERRATUM_845719 396 bool "Cortex-A53: 845719: a load might read incorrect data" 397 depends on COMPAT 398 default y 399 help 400 This option adds an alternative code sequence to work around ARM 401 erratum 845719 on Cortex-A53 parts up to r0p4. 402 403 When running a compat (AArch32) userspace on an affected Cortex-A53 404 part, a load at EL0 from a virtual address that matches the bottom 32 405 bits of the virtual address used by a recent load at (AArch64) EL1 406 might return incorrect data. 407 408 The workaround is to write the contextidr_el1 register on exception 409 return to a 32-bit task. 410 Please note that this does not necessarily enable the workaround, 411 as it depends on the alternative framework, which will only patch 412 the kernel if an affected CPU is detected. 413 414 If unsure, say Y. 415 416config ARM64_ERRATUM_843419 417 bool "Cortex-A53: 843419: A load or store might access an incorrect address" 418 depends on MODULES 419 default y 420 help 421 This option builds kernel modules using the large memory model in 422 order to avoid the use of the ADRP instruction, which can cause 423 a subsequent memory access to use an incorrect address on Cortex-A53 424 parts up to r0p4. 425 426 Note that the kernel itself must be linked with a version of ld 427 which fixes potentially affected ADRP instructions through the 428 use of veneers. 429 430 If unsure, say Y. 431 432endmenu 433 434 435choice 436 prompt "Page size" 437 default ARM64_4K_PAGES 438 help 439 Page size (translation granule) configuration. 440 441config ARM64_4K_PAGES 442 bool "4KB" 443 help 444 This feature enables 4KB pages support. 445 446config ARM64_64K_PAGES 447 bool "64KB" 448 help 449 This feature enables 64KB pages support (4KB by default) 450 allowing only two levels of page tables and faster TLB 451 look-up. AArch32 emulation is not available when this feature 452 is enabled. 453 454endchoice 455 456choice 457 prompt "Virtual address space size" 458 default ARM64_VA_BITS_39 if ARM64_4K_PAGES 459 default ARM64_VA_BITS_42 if ARM64_64K_PAGES 460 help 461 Allows choosing one of multiple possible virtual address 462 space sizes. The level of translation table is determined by 463 a combination of page size and virtual address space size. 464 465config ARM64_VA_BITS_39 466 bool "39-bit" 467 depends on ARM64_4K_PAGES 468 469config ARM64_VA_BITS_42 470 bool "42-bit" 471 depends on ARM64_64K_PAGES 472 473config ARM64_VA_BITS_48 474 bool "48-bit" 475 476endchoice 477 478config ARM64_VA_BITS 479 int 480 default 39 if ARM64_VA_BITS_39 481 default 42 if ARM64_VA_BITS_42 482 default 48 if ARM64_VA_BITS_48 483 484config CPU_BIG_ENDIAN 485 bool "Build big-endian kernel" 486 help 487 Say Y if you plan on running a kernel in big-endian mode. 488 489config SMP 490 bool "Symmetric Multi-Processing" 491 help 492 This enables support for systems with more than one CPU. If 493 you say N here, the kernel will run on single and 494 multiprocessor machines, but will use only one CPU of a 495 multiprocessor machine. If you say Y here, the kernel will run 496 on many, but not all, single processor machines. On a single 497 processor machine, the kernel will run faster if you say N 498 here. 499 500 If you don't know what to do here, say N. 501 502config SCHED_MC 503 bool "Multi-core scheduler support" 504 depends on SMP 505 help 506 Multi-core scheduler support improves the CPU scheduler's decision 507 making when dealing with multi-core CPU chips at a cost of slightly 508 increased overhead in some places. If unsure say N here. 509 510config SCHED_SMT 511 bool "SMT scheduler support" 512 depends on SMP 513 help 514 Improves the CPU scheduler's decision making when dealing with 515 MultiThreading at a cost of slightly increased overhead in some 516 places. If unsure say N here. 517 518config NR_CPUS 519 int "Maximum number of CPUs (2-4096)" 520 range 2 4096 521 depends on SMP 522 # These have to remain sorted largest to smallest 523 default "64" 524 525config HOTPLUG_CPU 526 bool "Support for hot-pluggable CPUs" 527 depends on SMP 528 help 529 Say Y here to experiment with turning CPUs off and on. CPUs 530 can be controlled through /sys/devices/system/cpu. 531 532source kernel/Kconfig.preempt 533 534config UP_LATE_INIT 535 def_bool y 536 depends on !SMP 537 538config HZ 539 int 540 default 100 541 542config ARCH_HAS_HOLES_MEMORYMODEL 543 def_bool y if SPARSEMEM 544 545config ARCH_SPARSEMEM_ENABLE 546 def_bool y 547 select SPARSEMEM_VMEMMAP_ENABLE 548 549config ARCH_SPARSEMEM_DEFAULT 550 def_bool ARCH_SPARSEMEM_ENABLE 551 552config ARCH_SELECT_MEMORY_MODEL 553 def_bool ARCH_SPARSEMEM_ENABLE 554 555config HAVE_ARCH_PFN_VALID 556 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM 557 558config HW_PERF_EVENTS 559 bool "Enable hardware performance counter support for perf events" 560 depends on PERF_EVENTS 561 default y 562 help 563 Enable hardware performance counter support for perf events. If 564 disabled, perf events will use software events only. 565 566config SYS_SUPPORTS_HUGETLBFS 567 def_bool y 568 569config ARCH_WANT_GENERAL_HUGETLB 570 def_bool y 571 572config ARCH_WANT_HUGE_PMD_SHARE 573 def_bool y if !ARM64_64K_PAGES 574 575config HAVE_ARCH_TRANSPARENT_HUGEPAGE 576 def_bool y 577 578config ARCH_HAS_CACHE_LINE_SIZE 579 def_bool y 580 581source "mm/Kconfig" 582 583config SECCOMP 584 bool "Enable seccomp to safely compute untrusted bytecode" 585 ---help--- 586 This kernel feature is useful for number crunching applications 587 that may need to compute untrusted bytecode during their 588 execution. By using pipes or other transports made available to 589 the process as file descriptors supporting the read/write 590 syscalls, it's possible to isolate those applications in 591 their own address space using seccomp. Once seccomp is 592 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled 593 and the task is only allowed to execute a few safe syscalls 594 defined by each seccomp mode. 595 596config XEN_DOM0 597 def_bool y 598 depends on XEN 599 600config XEN 601 bool "Xen guest support on ARM64" 602 depends on ARM64 && OF 603 select SWIOTLB_XEN 604 help 605 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64. 606 607config FORCE_MAX_ZONEORDER 608 int 609 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE) 610 default "11" 611 612menuconfig ARMV8_DEPRECATED 613 bool "Emulate deprecated/obsolete ARMv8 instructions" 614 depends on COMPAT 615 help 616 Legacy software support may require certain instructions 617 that have been deprecated or obsoleted in the architecture. 618 619 Enable this config to enable selective emulation of these 620 features. 621 622 If unsure, say Y 623 624if ARMV8_DEPRECATED 625 626config SWP_EMULATION 627 bool "Emulate SWP/SWPB instructions" 628 help 629 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that 630 they are always undefined. Say Y here to enable software 631 emulation of these instructions for userspace using LDXR/STXR. 632 633 In some older versions of glibc [<=2.8] SWP is used during futex 634 trylock() operations with the assumption that the code will not 635 be preempted. This invalid assumption may be more likely to fail 636 with SWP emulation enabled, leading to deadlock of the user 637 application. 638 639 NOTE: when accessing uncached shared regions, LDXR/STXR rely 640 on an external transaction monitoring block called a global 641 monitor to maintain update atomicity. If your system does not 642 implement a global monitor, this option can cause programs that 643 perform SWP operations to uncached memory to deadlock. 644 645 If unsure, say Y 646 647config CP15_BARRIER_EMULATION 648 bool "Emulate CP15 Barrier instructions" 649 help 650 The CP15 barrier instructions - CP15ISB, CP15DSB, and 651 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is 652 strongly recommended to use the ISB, DSB, and DMB 653 instructions instead. 654 655 Say Y here to enable software emulation of these 656 instructions for AArch32 userspace code. When this option is 657 enabled, CP15 barrier usage is traced which can help 658 identify software that needs updating. 659 660 If unsure, say Y 661 662config SETEND_EMULATION 663 bool "Emulate SETEND instruction" 664 help 665 The SETEND instruction alters the data-endianness of the 666 AArch32 EL0, and is deprecated in ARMv8. 667 668 Say Y here to enable software emulation of the instruction 669 for AArch32 userspace code. 670 671 Note: All the cpus on the system must have mixed endian support at EL0 672 for this feature to be enabled. If a new CPU - which doesn't support mixed 673 endian - is hotplugged in after this feature has been enabled, there could 674 be unexpected results in the applications. 675 676 If unsure, say Y 677endif 678 679endmenu 680 681menu "Boot options" 682 683config CMDLINE 684 string "Default kernel command string" 685 default "" 686 help 687 Provide a set of default command-line options at build time by 688 entering them here. As a minimum, you should specify the the 689 root device (e.g. root=/dev/nfs). 690 691config CMDLINE_FORCE 692 bool "Always use the default kernel command string" 693 help 694 Always use the default kernel command string, even if the boot 695 loader passes other arguments to the kernel. 696 This is useful if you cannot or don't want to change the 697 command-line options your boot loader passes to the kernel. 698 699config EFI_STUB 700 bool 701 702config EFI 703 bool "UEFI runtime support" 704 depends on OF && !CPU_BIG_ENDIAN 705 select LIBFDT 706 select UCS2_STRING 707 select EFI_PARAMS_FROM_FDT 708 select EFI_RUNTIME_WRAPPERS 709 select EFI_STUB 710 select EFI_ARMSTUB 711 default y 712 help 713 This option provides support for runtime services provided 714 by UEFI firmware (such as non-volatile variables, realtime 715 clock, and platform reset). A UEFI stub is also provided to 716 allow the kernel to be booted as an EFI application. This 717 is only useful on systems that have UEFI firmware. 718 719config DMI 720 bool "Enable support for SMBIOS (DMI) tables" 721 depends on EFI 722 default y 723 help 724 This enables SMBIOS/DMI feature for systems. 725 726 This option is only useful on systems that have UEFI firmware. 727 However, even with this option, the resultant kernel should 728 continue to boot on existing non-UEFI platforms. 729 730endmenu 731 732menu "Userspace binary formats" 733 734source "fs/Kconfig.binfmt" 735 736config COMPAT 737 bool "Kernel support for 32-bit EL0" 738 depends on !ARM64_64K_PAGES || EXPERT 739 select COMPAT_BINFMT_ELF 740 select HAVE_UID16 741 select OLD_SIGSUSPEND3 742 select COMPAT_OLD_SIGACTION 743 help 744 This option enables support for a 32-bit EL0 running under a 64-bit 745 kernel at EL1. AArch32-specific components such as system calls, 746 the user helper functions, VFP support and the ptrace interface are 747 handled appropriately by the kernel. 748 749 If you also enabled CONFIG_ARM64_64K_PAGES, please be aware that you 750 will only be able to execute AArch32 binaries that were compiled with 751 64k aligned segments. 752 753 If you want to execute 32-bit userspace applications, say Y. 754 755config SYSVIPC_COMPAT 756 def_bool y 757 depends on COMPAT && SYSVIPC 758 759endmenu 760 761menu "Power management options" 762 763source "kernel/power/Kconfig" 764 765config ARCH_SUSPEND_POSSIBLE 766 def_bool y 767 768endmenu 769 770menu "CPU Power Management" 771 772source "drivers/cpuidle/Kconfig" 773 774source "drivers/cpufreq/Kconfig" 775 776endmenu 777 778source "net/Kconfig" 779 780source "drivers/Kconfig" 781 782source "drivers/firmware/Kconfig" 783 784source "drivers/acpi/Kconfig" 785 786source "fs/Kconfig" 787 788source "arch/arm64/kvm/Kconfig" 789 790source "arch/arm64/Kconfig.debug" 791 792source "security/Kconfig" 793 794source "crypto/Kconfig" 795if CRYPTO 796source "arch/arm64/crypto/Kconfig" 797endif 798 799source "lib/Kconfig" 800