1/*
2 * arch/arm/mach-w90x900/include/mach/regs-irq.h
3 *
4 * Copyright (c) 2008 Nuvoton technology corporation
5 * All rights reserved.
6 *
7 * Wan ZongShun <mcuos.com@gmail.com>
8 *
9 * Based on arch/arm/mach-s3c2410/include/mach/regs-irq.h
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 */
17
18#ifndef ___ASM_ARCH_REGS_IRQ_H
19#define ___ASM_ARCH_REGS_IRQ_H
20
21/* Advance Interrupt Controller (AIC) Registers */
22
23#define AIC_BA    		W90X900_VA_IRQ
24
25#define REG_AIC_IRQSC		(AIC_BA+0x80)
26#define REG_AIC_GEN		(AIC_BA+0x84)
27#define REG_AIC_GASR		(AIC_BA+0x88)
28#define REG_AIC_GSCR		(AIC_BA+0x8C)
29#define REG_AIC_IRSR		(AIC_BA+0x100)
30#define REG_AIC_IASR		(AIC_BA+0x104)
31#define REG_AIC_ISR		(AIC_BA+0x108)
32#define REG_AIC_IPER		(AIC_BA+0x10C)
33#define REG_AIC_ISNR		(AIC_BA+0x110)
34#define REG_AIC_IMR		(AIC_BA+0x114)
35#define REG_AIC_OISR		(AIC_BA+0x118)
36#define REG_AIC_MECR		(AIC_BA+0x120)
37#define REG_AIC_MDCR		(AIC_BA+0x124)
38#define REG_AIC_SSCR		(AIC_BA+0x128)
39#define REG_AIC_SCCR		(AIC_BA+0x12C)
40#define REG_AIC_EOSCR		(AIC_BA+0x130)
41#define AIC_IPER		(0x10C)
42#define AIC_ISNR		(0x110)
43
44/*16-18 bits of REG_AIC_GEN define irq(2-4) group*/
45
46#define TIMER2_IRQ		(1 << 16)
47#define TIMER3_IRQ		(1 << 17)
48#define TIMER4_IRQ		(1 << 18)
49#define TIME_GROUP_IRQ		(TIMER2_IRQ|TIMER3_IRQ|TIMER4_IRQ)
50
51#endif /* ___ASM_ARCH_REGS_IRQ_H */
52