1/* 2 * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips 3 * 4 * Copyright (C) 2009-2011 Nokia Corporation 5 * Copyright (C) 2012 Texas Instruments, Inc. 6 * Paul Walmsley 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * The data in this file should be completely autogeneratable from 13 * the TI hardware database or other technical documentation. 14 * 15 * XXX these should be marked initdata for multi-OMAP kernels 16 */ 17 18#include <linux/i2c-omap.h> 19#include <linux/power/smartreflex.h> 20#include <linux/platform_data/gpio-omap.h> 21#include <linux/platform_data/hsmmc-omap.h> 22 23#include <linux/omap-dma.h> 24#include "l3_3xxx.h" 25#include "l4_3xxx.h" 26#include <linux/platform_data/asoc-ti-mcbsp.h> 27#include <linux/platform_data/spi-omap2-mcspi.h> 28#include <linux/platform_data/iommu-omap.h> 29#include <linux/platform_data/mailbox-omap.h> 30#include <plat/dmtimer.h> 31 32#include "soc.h" 33#include "omap_hwmod.h" 34#include "omap_hwmod_common_data.h" 35#include "prm-regbits-34xx.h" 36#include "cm-regbits-34xx.h" 37 38#include "i2c.h" 39#include "wd_timer.h" 40#include "serial.h" 41 42/* 43 * OMAP3xxx hardware module integration data 44 * 45 * All of the data in this section should be autogeneratable from the 46 * TI hardware database or other technical documentation. Data that 47 * is driver-specific or driver-kernel integration-specific belongs 48 * elsewhere. 49 */ 50 51#define AM35XX_IPSS_USBOTGSS_BASE 0x5C040000 52 53/* 54 * IP blocks 55 */ 56 57/* L3 */ 58static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = { 59 { .irq = 9 + OMAP_INTC_START, }, 60 { .irq = 10 + OMAP_INTC_START, }, 61 { .irq = -1 }, 62}; 63 64static struct omap_hwmod omap3xxx_l3_main_hwmod = { 65 .name = "l3_main", 66 .class = &l3_hwmod_class, 67 .mpu_irqs = omap3xxx_l3_main_irqs, 68 .flags = HWMOD_NO_IDLEST, 69}; 70 71/* L4 CORE */ 72static struct omap_hwmod omap3xxx_l4_core_hwmod = { 73 .name = "l4_core", 74 .class = &l4_hwmod_class, 75 .flags = HWMOD_NO_IDLEST, 76}; 77 78/* L4 PER */ 79static struct omap_hwmod omap3xxx_l4_per_hwmod = { 80 .name = "l4_per", 81 .class = &l4_hwmod_class, 82 .flags = HWMOD_NO_IDLEST, 83}; 84 85/* L4 WKUP */ 86static struct omap_hwmod omap3xxx_l4_wkup_hwmod = { 87 .name = "l4_wkup", 88 .class = &l4_hwmod_class, 89 .flags = HWMOD_NO_IDLEST, 90}; 91 92/* L4 SEC */ 93static struct omap_hwmod omap3xxx_l4_sec_hwmod = { 94 .name = "l4_sec", 95 .class = &l4_hwmod_class, 96 .flags = HWMOD_NO_IDLEST, 97}; 98 99/* MPU */ 100static struct omap_hwmod_irq_info omap3xxx_mpu_irqs[] = { 101 { .name = "pmu", .irq = 3 + OMAP_INTC_START }, 102 { .irq = -1 } 103}; 104 105static struct omap_hwmod omap3xxx_mpu_hwmod = { 106 .name = "mpu", 107 .mpu_irqs = omap3xxx_mpu_irqs, 108 .class = &mpu_hwmod_class, 109 .main_clk = "arm_fck", 110}; 111 112/* IVA2 (IVA2) */ 113static struct omap_hwmod_rst_info omap3xxx_iva_resets[] = { 114 { .name = "logic", .rst_shift = 0, .st_shift = 8 }, 115 { .name = "seq0", .rst_shift = 1, .st_shift = 9 }, 116 { .name = "seq1", .rst_shift = 2, .st_shift = 10 }, 117}; 118 119static struct omap_hwmod omap3xxx_iva_hwmod = { 120 .name = "iva", 121 .class = &iva_hwmod_class, 122 .clkdm_name = "iva2_clkdm", 123 .rst_lines = omap3xxx_iva_resets, 124 .rst_lines_cnt = ARRAY_SIZE(omap3xxx_iva_resets), 125 .main_clk = "iva2_ck", 126 .prcm = { 127 .omap2 = { 128 .module_offs = OMAP3430_IVA2_MOD, 129 .prcm_reg_id = 1, 130 .module_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT, 131 .idlest_reg_id = 1, 132 .idlest_idle_bit = OMAP3430_ST_IVA2_SHIFT, 133 } 134 }, 135}; 136 137/* 138 * 'debugss' class 139 * debug and emulation sub system 140 */ 141 142static struct omap_hwmod_class omap3xxx_debugss_hwmod_class = { 143 .name = "debugss", 144}; 145 146/* debugss */ 147static struct omap_hwmod omap3xxx_debugss_hwmod = { 148 .name = "debugss", 149 .class = &omap3xxx_debugss_hwmod_class, 150 .clkdm_name = "emu_clkdm", 151 .main_clk = "emu_src_ck", 152 .flags = HWMOD_NO_IDLEST, 153}; 154 155/* timer class */ 156static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = { 157 .rev_offs = 0x0000, 158 .sysc_offs = 0x0010, 159 .syss_offs = 0x0014, 160 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY | 161 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | 162 SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE | 163 SYSS_HAS_RESET_STATUS), 164 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 165 .clockact = CLOCKACT_TEST_ICLK, 166 .sysc_fields = &omap_hwmod_sysc_type1, 167}; 168 169static struct omap_hwmod_class omap3xxx_timer_hwmod_class = { 170 .name = "timer", 171 .sysc = &omap3xxx_timer_sysc, 172}; 173 174/* secure timers dev attribute */ 175static struct omap_timer_capability_dev_attr capability_secure_dev_attr = { 176 .timer_capability = OMAP_TIMER_ALWON | OMAP_TIMER_SECURE, 177}; 178 179/* always-on timers dev attribute */ 180static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = { 181 .timer_capability = OMAP_TIMER_ALWON, 182}; 183 184/* pwm timers dev attribute */ 185static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = { 186 .timer_capability = OMAP_TIMER_HAS_PWM, 187}; 188 189/* timers with DSP interrupt dev attribute */ 190static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = { 191 .timer_capability = OMAP_TIMER_HAS_DSP_IRQ, 192}; 193 194/* pwm timers with DSP interrupt dev attribute */ 195static struct omap_timer_capability_dev_attr capability_dsp_pwm_dev_attr = { 196 .timer_capability = OMAP_TIMER_HAS_DSP_IRQ | OMAP_TIMER_HAS_PWM, 197}; 198 199/* timer1 */ 200static struct omap_hwmod omap3xxx_timer1_hwmod = { 201 .name = "timer1", 202 .mpu_irqs = omap2_timer1_mpu_irqs, 203 .main_clk = "gpt1_fck", 204 .prcm = { 205 .omap2 = { 206 .prcm_reg_id = 1, 207 .module_bit = OMAP3430_EN_GPT1_SHIFT, 208 .module_offs = WKUP_MOD, 209 .idlest_reg_id = 1, 210 .idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT, 211 }, 212 }, 213 .dev_attr = &capability_alwon_dev_attr, 214 .class = &omap3xxx_timer_hwmod_class, 215 .flags = HWMOD_SET_DEFAULT_CLOCKACT, 216}; 217 218/* timer2 */ 219static struct omap_hwmod omap3xxx_timer2_hwmod = { 220 .name = "timer2", 221 .mpu_irqs = omap2_timer2_mpu_irqs, 222 .main_clk = "gpt2_fck", 223 .prcm = { 224 .omap2 = { 225 .prcm_reg_id = 1, 226 .module_bit = OMAP3430_EN_GPT2_SHIFT, 227 .module_offs = OMAP3430_PER_MOD, 228 .idlest_reg_id = 1, 229 .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT, 230 }, 231 }, 232 .class = &omap3xxx_timer_hwmod_class, 233 .flags = HWMOD_SET_DEFAULT_CLOCKACT, 234}; 235 236/* timer3 */ 237static struct omap_hwmod omap3xxx_timer3_hwmod = { 238 .name = "timer3", 239 .mpu_irqs = omap2_timer3_mpu_irqs, 240 .main_clk = "gpt3_fck", 241 .prcm = { 242 .omap2 = { 243 .prcm_reg_id = 1, 244 .module_bit = OMAP3430_EN_GPT3_SHIFT, 245 .module_offs = OMAP3430_PER_MOD, 246 .idlest_reg_id = 1, 247 .idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT, 248 }, 249 }, 250 .class = &omap3xxx_timer_hwmod_class, 251 .flags = HWMOD_SET_DEFAULT_CLOCKACT, 252}; 253 254/* timer4 */ 255static struct omap_hwmod omap3xxx_timer4_hwmod = { 256 .name = "timer4", 257 .mpu_irqs = omap2_timer4_mpu_irqs, 258 .main_clk = "gpt4_fck", 259 .prcm = { 260 .omap2 = { 261 .prcm_reg_id = 1, 262 .module_bit = OMAP3430_EN_GPT4_SHIFT, 263 .module_offs = OMAP3430_PER_MOD, 264 .idlest_reg_id = 1, 265 .idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT, 266 }, 267 }, 268 .class = &omap3xxx_timer_hwmod_class, 269 .flags = HWMOD_SET_DEFAULT_CLOCKACT, 270}; 271 272/* timer5 */ 273static struct omap_hwmod omap3xxx_timer5_hwmod = { 274 .name = "timer5", 275 .mpu_irqs = omap2_timer5_mpu_irqs, 276 .main_clk = "gpt5_fck", 277 .prcm = { 278 .omap2 = { 279 .prcm_reg_id = 1, 280 .module_bit = OMAP3430_EN_GPT5_SHIFT, 281 .module_offs = OMAP3430_PER_MOD, 282 .idlest_reg_id = 1, 283 .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT, 284 }, 285 }, 286 .dev_attr = &capability_dsp_dev_attr, 287 .class = &omap3xxx_timer_hwmod_class, 288 .flags = HWMOD_SET_DEFAULT_CLOCKACT, 289}; 290 291/* timer6 */ 292static struct omap_hwmod omap3xxx_timer6_hwmod = { 293 .name = "timer6", 294 .mpu_irqs = omap2_timer6_mpu_irqs, 295 .main_clk = "gpt6_fck", 296 .prcm = { 297 .omap2 = { 298 .prcm_reg_id = 1, 299 .module_bit = OMAP3430_EN_GPT6_SHIFT, 300 .module_offs = OMAP3430_PER_MOD, 301 .idlest_reg_id = 1, 302 .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT, 303 }, 304 }, 305 .dev_attr = &capability_dsp_dev_attr, 306 .class = &omap3xxx_timer_hwmod_class, 307 .flags = HWMOD_SET_DEFAULT_CLOCKACT, 308}; 309 310/* timer7 */ 311static struct omap_hwmod omap3xxx_timer7_hwmod = { 312 .name = "timer7", 313 .mpu_irqs = omap2_timer7_mpu_irqs, 314 .main_clk = "gpt7_fck", 315 .prcm = { 316 .omap2 = { 317 .prcm_reg_id = 1, 318 .module_bit = OMAP3430_EN_GPT7_SHIFT, 319 .module_offs = OMAP3430_PER_MOD, 320 .idlest_reg_id = 1, 321 .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT, 322 }, 323 }, 324 .dev_attr = &capability_dsp_dev_attr, 325 .class = &omap3xxx_timer_hwmod_class, 326 .flags = HWMOD_SET_DEFAULT_CLOCKACT, 327}; 328 329/* timer8 */ 330static struct omap_hwmod omap3xxx_timer8_hwmod = { 331 .name = "timer8", 332 .mpu_irqs = omap2_timer8_mpu_irqs, 333 .main_clk = "gpt8_fck", 334 .prcm = { 335 .omap2 = { 336 .prcm_reg_id = 1, 337 .module_bit = OMAP3430_EN_GPT8_SHIFT, 338 .module_offs = OMAP3430_PER_MOD, 339 .idlest_reg_id = 1, 340 .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT, 341 }, 342 }, 343 .dev_attr = &capability_dsp_pwm_dev_attr, 344 .class = &omap3xxx_timer_hwmod_class, 345 .flags = HWMOD_SET_DEFAULT_CLOCKACT, 346}; 347 348/* timer9 */ 349static struct omap_hwmod omap3xxx_timer9_hwmod = { 350 .name = "timer9", 351 .mpu_irqs = omap2_timer9_mpu_irqs, 352 .main_clk = "gpt9_fck", 353 .prcm = { 354 .omap2 = { 355 .prcm_reg_id = 1, 356 .module_bit = OMAP3430_EN_GPT9_SHIFT, 357 .module_offs = OMAP3430_PER_MOD, 358 .idlest_reg_id = 1, 359 .idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT, 360 }, 361 }, 362 .dev_attr = &capability_pwm_dev_attr, 363 .class = &omap3xxx_timer_hwmod_class, 364 .flags = HWMOD_SET_DEFAULT_CLOCKACT, 365}; 366 367/* timer10 */ 368static struct omap_hwmod omap3xxx_timer10_hwmod = { 369 .name = "timer10", 370 .mpu_irqs = omap2_timer10_mpu_irqs, 371 .main_clk = "gpt10_fck", 372 .prcm = { 373 .omap2 = { 374 .prcm_reg_id = 1, 375 .module_bit = OMAP3430_EN_GPT10_SHIFT, 376 .module_offs = CORE_MOD, 377 .idlest_reg_id = 1, 378 .idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT, 379 }, 380 }, 381 .dev_attr = &capability_pwm_dev_attr, 382 .class = &omap3xxx_timer_hwmod_class, 383 .flags = HWMOD_SET_DEFAULT_CLOCKACT, 384}; 385 386/* timer11 */ 387static struct omap_hwmod omap3xxx_timer11_hwmod = { 388 .name = "timer11", 389 .mpu_irqs = omap2_timer11_mpu_irqs, 390 .main_clk = "gpt11_fck", 391 .prcm = { 392 .omap2 = { 393 .prcm_reg_id = 1, 394 .module_bit = OMAP3430_EN_GPT11_SHIFT, 395 .module_offs = CORE_MOD, 396 .idlest_reg_id = 1, 397 .idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT, 398 }, 399 }, 400 .dev_attr = &capability_pwm_dev_attr, 401 .class = &omap3xxx_timer_hwmod_class, 402 .flags = HWMOD_SET_DEFAULT_CLOCKACT, 403}; 404 405/* timer12 */ 406static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = { 407 { .irq = 95 + OMAP_INTC_START, }, 408 { .irq = -1 }, 409}; 410 411static struct omap_hwmod omap3xxx_timer12_hwmod = { 412 .name = "timer12", 413 .mpu_irqs = omap3xxx_timer12_mpu_irqs, 414 .main_clk = "gpt12_fck", 415 .prcm = { 416 .omap2 = { 417 .prcm_reg_id = 1, 418 .module_bit = OMAP3430_EN_GPT12_SHIFT, 419 .module_offs = WKUP_MOD, 420 .idlest_reg_id = 1, 421 .idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT, 422 }, 423 }, 424 .dev_attr = &capability_secure_dev_attr, 425 .class = &omap3xxx_timer_hwmod_class, 426 .flags = HWMOD_SET_DEFAULT_CLOCKACT, 427}; 428 429/* 430 * 'wd_timer' class 431 * 32-bit watchdog upward counter that generates a pulse on the reset pin on 432 * overflow condition 433 */ 434 435static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = { 436 .rev_offs = 0x0000, 437 .sysc_offs = 0x0010, 438 .syss_offs = 0x0014, 439 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE | 440 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | 441 SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | 442 SYSS_HAS_RESET_STATUS), 443 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 444 .sysc_fields = &omap_hwmod_sysc_type1, 445}; 446 447/* I2C common */ 448static struct omap_hwmod_class_sysconfig i2c_sysc = { 449 .rev_offs = 0x00, 450 .sysc_offs = 0x20, 451 .syss_offs = 0x10, 452 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | 453 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | 454 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), 455 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 456 .clockact = CLOCKACT_TEST_ICLK, 457 .sysc_fields = &omap_hwmod_sysc_type1, 458}; 459 460static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = { 461 .name = "wd_timer", 462 .sysc = &omap3xxx_wd_timer_sysc, 463 .pre_shutdown = &omap2_wd_timer_disable, 464 .reset = &omap2_wd_timer_reset, 465}; 466 467static struct omap_hwmod omap3xxx_wd_timer2_hwmod = { 468 .name = "wd_timer2", 469 .class = &omap3xxx_wd_timer_hwmod_class, 470 .main_clk = "wdt2_fck", 471 .prcm = { 472 .omap2 = { 473 .prcm_reg_id = 1, 474 .module_bit = OMAP3430_EN_WDT2_SHIFT, 475 .module_offs = WKUP_MOD, 476 .idlest_reg_id = 1, 477 .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT, 478 }, 479 }, 480 /* 481 * XXX: Use software supervised mode, HW supervised smartidle seems to 482 * block CORE power domain idle transitions. Maybe a HW bug in wdt2? 483 */ 484 .flags = HWMOD_SWSUP_SIDLE, 485}; 486 487/* UART1 */ 488static struct omap_hwmod omap3xxx_uart1_hwmod = { 489 .name = "uart1", 490 .mpu_irqs = omap2_uart1_mpu_irqs, 491 .sdma_reqs = omap2_uart1_sdma_reqs, 492 .main_clk = "uart1_fck", 493 .flags = DEBUG_TI81XXUART1_FLAGS | HWMOD_SWSUP_SIDLE, 494 .prcm = { 495 .omap2 = { 496 .module_offs = CORE_MOD, 497 .prcm_reg_id = 1, 498 .module_bit = OMAP3430_EN_UART1_SHIFT, 499 .idlest_reg_id = 1, 500 .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT, 501 }, 502 }, 503 .class = &omap2_uart_class, 504}; 505 506/* UART2 */ 507static struct omap_hwmod omap3xxx_uart2_hwmod = { 508 .name = "uart2", 509 .mpu_irqs = omap2_uart2_mpu_irqs, 510 .sdma_reqs = omap2_uart2_sdma_reqs, 511 .main_clk = "uart2_fck", 512 .flags = DEBUG_TI81XXUART2_FLAGS | HWMOD_SWSUP_SIDLE, 513 .prcm = { 514 .omap2 = { 515 .module_offs = CORE_MOD, 516 .prcm_reg_id = 1, 517 .module_bit = OMAP3430_EN_UART2_SHIFT, 518 .idlest_reg_id = 1, 519 .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT, 520 }, 521 }, 522 .class = &omap2_uart_class, 523}; 524 525/* UART3 */ 526static struct omap_hwmod omap3xxx_uart3_hwmod = { 527 .name = "uart3", 528 .mpu_irqs = omap2_uart3_mpu_irqs, 529 .sdma_reqs = omap2_uart3_sdma_reqs, 530 .main_clk = "uart3_fck", 531 .flags = DEBUG_OMAP3UART3_FLAGS | DEBUG_TI81XXUART3_FLAGS | 532 HWMOD_SWSUP_SIDLE, 533 .prcm = { 534 .omap2 = { 535 .module_offs = OMAP3430_PER_MOD, 536 .prcm_reg_id = 1, 537 .module_bit = OMAP3430_EN_UART3_SHIFT, 538 .idlest_reg_id = 1, 539 .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT, 540 }, 541 }, 542 .class = &omap2_uart_class, 543}; 544 545/* UART4 */ 546static struct omap_hwmod_irq_info uart4_mpu_irqs[] = { 547 { .irq = 80 + OMAP_INTC_START, }, 548 { .irq = -1 }, 549}; 550 551static struct omap_hwmod_dma_info uart4_sdma_reqs[] = { 552 { .name = "rx", .dma_req = 82, }, 553 { .name = "tx", .dma_req = 81, }, 554 { .dma_req = -1 } 555}; 556 557static struct omap_hwmod omap36xx_uart4_hwmod = { 558 .name = "uart4", 559 .mpu_irqs = uart4_mpu_irqs, 560 .sdma_reqs = uart4_sdma_reqs, 561 .main_clk = "uart4_fck", 562 .flags = DEBUG_OMAP3UART4_FLAGS | HWMOD_SWSUP_SIDLE, 563 .prcm = { 564 .omap2 = { 565 .module_offs = OMAP3430_PER_MOD, 566 .prcm_reg_id = 1, 567 .module_bit = OMAP3630_EN_UART4_SHIFT, 568 .idlest_reg_id = 1, 569 .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT, 570 }, 571 }, 572 .class = &omap2_uart_class, 573}; 574 575static struct omap_hwmod_irq_info am35xx_uart4_mpu_irqs[] = { 576 { .irq = 84 + OMAP_INTC_START, }, 577 { .irq = -1 }, 578}; 579 580static struct omap_hwmod_dma_info am35xx_uart4_sdma_reqs[] = { 581 { .name = "rx", .dma_req = 55, }, 582 { .name = "tx", .dma_req = 54, }, 583 { .dma_req = -1 } 584}; 585 586/* 587 * XXX AM35xx UART4 cannot complete its softreset without uart1_fck or 588 * uart2_fck being enabled. So we add uart1_fck as an optional clock, 589 * below, and set the HWMOD_CONTROL_OPT_CLKS_IN_RESET. This really 590 * should not be needed. The functional clock structure of the AM35xx 591 * UART4 is extremely unclear and opaque; it is unclear what the role 592 * of uart1/2_fck is for the UART4. Any clarification from either 593 * empirical testing or the AM3505/3517 hardware designers would be 594 * most welcome. 595 */ 596static struct omap_hwmod_opt_clk am35xx_uart4_opt_clks[] = { 597 { .role = "softreset_uart1_fck", .clk = "uart1_fck" }, 598}; 599 600static struct omap_hwmod am35xx_uart4_hwmod = { 601 .name = "uart4", 602 .mpu_irqs = am35xx_uart4_mpu_irqs, 603 .sdma_reqs = am35xx_uart4_sdma_reqs, 604 .main_clk = "uart4_fck", 605 .prcm = { 606 .omap2 = { 607 .module_offs = CORE_MOD, 608 .prcm_reg_id = 1, 609 .module_bit = AM35XX_EN_UART4_SHIFT, 610 .idlest_reg_id = 1, 611 .idlest_idle_bit = AM35XX_ST_UART4_SHIFT, 612 }, 613 }, 614 .opt_clks = am35xx_uart4_opt_clks, 615 .opt_clks_cnt = ARRAY_SIZE(am35xx_uart4_opt_clks), 616 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 617 .class = &omap2_uart_class, 618}; 619 620static struct omap_hwmod_class i2c_class = { 621 .name = "i2c", 622 .sysc = &i2c_sysc, 623 .rev = OMAP_I2C_IP_VERSION_1, 624 .reset = &omap_i2c_reset, 625}; 626 627static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = { 628 { .name = "dispc", .dma_req = 5 }, 629 { .name = "dsi1", .dma_req = 74 }, 630 { .dma_req = -1 } 631}; 632 633/* dss */ 634static struct omap_hwmod_opt_clk dss_opt_clks[] = { 635 /* 636 * The DSS HW needs all DSS clocks enabled during reset. The dss_core 637 * driver does not use these clocks. 638 */ 639 { .role = "sys_clk", .clk = "dss2_alwon_fck" }, 640 { .role = "tv_clk", .clk = "dss_tv_fck" }, 641 /* required only on OMAP3430 */ 642 { .role = "tv_dac_clk", .clk = "dss_96m_fck" }, 643}; 644 645static struct omap_hwmod omap3430es1_dss_core_hwmod = { 646 .name = "dss_core", 647 .class = &omap2_dss_hwmod_class, 648 .main_clk = "dss1_alwon_fck", /* instead of dss_fck */ 649 .sdma_reqs = omap3xxx_dss_sdma_chs, 650 .prcm = { 651 .omap2 = { 652 .prcm_reg_id = 1, 653 .module_bit = OMAP3430_EN_DSS1_SHIFT, 654 .module_offs = OMAP3430_DSS_MOD, 655 .idlest_reg_id = 1, 656 .idlest_stdby_bit = OMAP3430ES1_ST_DSS_SHIFT, 657 }, 658 }, 659 .opt_clks = dss_opt_clks, 660 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), 661 .flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET, 662}; 663 664static struct omap_hwmod omap3xxx_dss_core_hwmod = { 665 .name = "dss_core", 666 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 667 .class = &omap2_dss_hwmod_class, 668 .main_clk = "dss1_alwon_fck", /* instead of dss_fck */ 669 .sdma_reqs = omap3xxx_dss_sdma_chs, 670 .prcm = { 671 .omap2 = { 672 .prcm_reg_id = 1, 673 .module_bit = OMAP3430_EN_DSS1_SHIFT, 674 .module_offs = OMAP3430_DSS_MOD, 675 .idlest_reg_id = 1, 676 .idlest_idle_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT, 677 .idlest_stdby_bit = OMAP3430ES2_ST_DSS_STDBY_SHIFT, 678 }, 679 }, 680 .opt_clks = dss_opt_clks, 681 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), 682}; 683 684/* 685 * 'dispc' class 686 * display controller 687 */ 688 689static struct omap_hwmod_class_sysconfig omap3_dispc_sysc = { 690 .rev_offs = 0x0000, 691 .sysc_offs = 0x0010, 692 .syss_offs = 0x0014, 693 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE | 694 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | 695 SYSC_HAS_ENAWAKEUP), 696 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 697 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), 698 .sysc_fields = &omap_hwmod_sysc_type1, 699}; 700 701static struct omap_hwmod_class omap3_dispc_hwmod_class = { 702 .name = "dispc", 703 .sysc = &omap3_dispc_sysc, 704}; 705 706static struct omap_hwmod omap3xxx_dss_dispc_hwmod = { 707 .name = "dss_dispc", 708 .class = &omap3_dispc_hwmod_class, 709 .mpu_irqs = omap2_dispc_irqs, 710 .main_clk = "dss1_alwon_fck", 711 .prcm = { 712 .omap2 = { 713 .prcm_reg_id = 1, 714 .module_bit = OMAP3430_EN_DSS1_SHIFT, 715 .module_offs = OMAP3430_DSS_MOD, 716 }, 717 }, 718 .flags = HWMOD_NO_IDLEST, 719 .dev_attr = &omap2_3_dss_dispc_dev_attr 720}; 721 722/* 723 * 'dsi' class 724 * display serial interface controller 725 */ 726 727static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = { 728 .name = "dsi", 729}; 730 731static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = { 732 { .irq = 25 + OMAP_INTC_START, }, 733 { .irq = -1 }, 734}; 735 736/* dss_dsi1 */ 737static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = { 738 { .role = "sys_clk", .clk = "dss2_alwon_fck" }, 739}; 740 741static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = { 742 .name = "dss_dsi1", 743 .class = &omap3xxx_dsi_hwmod_class, 744 .mpu_irqs = omap3xxx_dsi1_irqs, 745 .main_clk = "dss1_alwon_fck", 746 .prcm = { 747 .omap2 = { 748 .prcm_reg_id = 1, 749 .module_bit = OMAP3430_EN_DSS1_SHIFT, 750 .module_offs = OMAP3430_DSS_MOD, 751 }, 752 }, 753 .opt_clks = dss_dsi1_opt_clks, 754 .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks), 755 .flags = HWMOD_NO_IDLEST, 756}; 757 758static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = { 759 { .role = "ick", .clk = "dss_ick" }, 760}; 761 762static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = { 763 .name = "dss_rfbi", 764 .class = &omap2_rfbi_hwmod_class, 765 .main_clk = "dss1_alwon_fck", 766 .prcm = { 767 .omap2 = { 768 .prcm_reg_id = 1, 769 .module_bit = OMAP3430_EN_DSS1_SHIFT, 770 .module_offs = OMAP3430_DSS_MOD, 771 }, 772 }, 773 .opt_clks = dss_rfbi_opt_clks, 774 .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks), 775 .flags = HWMOD_NO_IDLEST, 776}; 777 778static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = { 779 /* required only on OMAP3430 */ 780 { .role = "tv_dac_clk", .clk = "dss_96m_fck" }, 781}; 782 783static struct omap_hwmod omap3xxx_dss_venc_hwmod = { 784 .name = "dss_venc", 785 .class = &omap2_venc_hwmod_class, 786 .main_clk = "dss_tv_fck", 787 .prcm = { 788 .omap2 = { 789 .prcm_reg_id = 1, 790 .module_bit = OMAP3430_EN_DSS1_SHIFT, 791 .module_offs = OMAP3430_DSS_MOD, 792 }, 793 }, 794 .opt_clks = dss_venc_opt_clks, 795 .opt_clks_cnt = ARRAY_SIZE(dss_venc_opt_clks), 796 .flags = HWMOD_NO_IDLEST, 797}; 798 799/* I2C1 */ 800static struct omap_i2c_dev_attr i2c1_dev_attr = { 801 .fifo_depth = 8, /* bytes */ 802 .flags = OMAP_I2C_FLAG_BUS_SHIFT_2, 803}; 804 805static struct omap_hwmod omap3xxx_i2c1_hwmod = { 806 .name = "i2c1", 807 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, 808 .mpu_irqs = omap2_i2c1_mpu_irqs, 809 .sdma_reqs = omap2_i2c1_sdma_reqs, 810 .main_clk = "i2c1_fck", 811 .prcm = { 812 .omap2 = { 813 .module_offs = CORE_MOD, 814 .prcm_reg_id = 1, 815 .module_bit = OMAP3430_EN_I2C1_SHIFT, 816 .idlest_reg_id = 1, 817 .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT, 818 }, 819 }, 820 .class = &i2c_class, 821 .dev_attr = &i2c1_dev_attr, 822}; 823 824/* I2C2 */ 825static struct omap_i2c_dev_attr i2c2_dev_attr = { 826 .fifo_depth = 8, /* bytes */ 827 .flags = OMAP_I2C_FLAG_BUS_SHIFT_2, 828}; 829 830static struct omap_hwmod omap3xxx_i2c2_hwmod = { 831 .name = "i2c2", 832 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, 833 .mpu_irqs = omap2_i2c2_mpu_irqs, 834 .sdma_reqs = omap2_i2c2_sdma_reqs, 835 .main_clk = "i2c2_fck", 836 .prcm = { 837 .omap2 = { 838 .module_offs = CORE_MOD, 839 .prcm_reg_id = 1, 840 .module_bit = OMAP3430_EN_I2C2_SHIFT, 841 .idlest_reg_id = 1, 842 .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT, 843 }, 844 }, 845 .class = &i2c_class, 846 .dev_attr = &i2c2_dev_attr, 847}; 848 849/* I2C3 */ 850static struct omap_i2c_dev_attr i2c3_dev_attr = { 851 .fifo_depth = 64, /* bytes */ 852 .flags = OMAP_I2C_FLAG_BUS_SHIFT_2, 853}; 854 855static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = { 856 { .irq = 61 + OMAP_INTC_START, }, 857 { .irq = -1 }, 858}; 859 860static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = { 861 { .name = "tx", .dma_req = 25 }, 862 { .name = "rx", .dma_req = 26 }, 863 { .dma_req = -1 } 864}; 865 866static struct omap_hwmod omap3xxx_i2c3_hwmod = { 867 .name = "i2c3", 868 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, 869 .mpu_irqs = i2c3_mpu_irqs, 870 .sdma_reqs = i2c3_sdma_reqs, 871 .main_clk = "i2c3_fck", 872 .prcm = { 873 .omap2 = { 874 .module_offs = CORE_MOD, 875 .prcm_reg_id = 1, 876 .module_bit = OMAP3430_EN_I2C3_SHIFT, 877 .idlest_reg_id = 1, 878 .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT, 879 }, 880 }, 881 .class = &i2c_class, 882 .dev_attr = &i2c3_dev_attr, 883}; 884 885/* 886 * 'gpio' class 887 * general purpose io module 888 */ 889 890static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = { 891 .rev_offs = 0x0000, 892 .sysc_offs = 0x0010, 893 .syss_offs = 0x0014, 894 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | 895 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | 896 SYSS_HAS_RESET_STATUS), 897 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 898 .sysc_fields = &omap_hwmod_sysc_type1, 899}; 900 901static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = { 902 .name = "gpio", 903 .sysc = &omap3xxx_gpio_sysc, 904 .rev = 1, 905}; 906 907/* gpio_dev_attr */ 908static struct omap_gpio_dev_attr gpio_dev_attr = { 909 .bank_width = 32, 910 .dbck_flag = true, 911}; 912 913/* gpio1 */ 914static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { 915 { .role = "dbclk", .clk = "gpio1_dbck", }, 916}; 917 918static struct omap_hwmod omap3xxx_gpio1_hwmod = { 919 .name = "gpio1", 920 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 921 .mpu_irqs = omap2_gpio1_irqs, 922 .main_clk = "gpio1_ick", 923 .opt_clks = gpio1_opt_clks, 924 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks), 925 .prcm = { 926 .omap2 = { 927 .prcm_reg_id = 1, 928 .module_bit = OMAP3430_EN_GPIO1_SHIFT, 929 .module_offs = WKUP_MOD, 930 .idlest_reg_id = 1, 931 .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT, 932 }, 933 }, 934 .class = &omap3xxx_gpio_hwmod_class, 935 .dev_attr = &gpio_dev_attr, 936}; 937 938/* gpio2 */ 939static struct omap_hwmod_opt_clk gpio2_opt_clks[] = { 940 { .role = "dbclk", .clk = "gpio2_dbck", }, 941}; 942 943static struct omap_hwmod omap3xxx_gpio2_hwmod = { 944 .name = "gpio2", 945 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 946 .mpu_irqs = omap2_gpio2_irqs, 947 .main_clk = "gpio2_ick", 948 .opt_clks = gpio2_opt_clks, 949 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks), 950 .prcm = { 951 .omap2 = { 952 .prcm_reg_id = 1, 953 .module_bit = OMAP3430_EN_GPIO2_SHIFT, 954 .module_offs = OMAP3430_PER_MOD, 955 .idlest_reg_id = 1, 956 .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT, 957 }, 958 }, 959 .class = &omap3xxx_gpio_hwmod_class, 960 .dev_attr = &gpio_dev_attr, 961}; 962 963/* gpio3 */ 964static struct omap_hwmod_opt_clk gpio3_opt_clks[] = { 965 { .role = "dbclk", .clk = "gpio3_dbck", }, 966}; 967 968static struct omap_hwmod omap3xxx_gpio3_hwmod = { 969 .name = "gpio3", 970 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 971 .mpu_irqs = omap2_gpio3_irqs, 972 .main_clk = "gpio3_ick", 973 .opt_clks = gpio3_opt_clks, 974 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks), 975 .prcm = { 976 .omap2 = { 977 .prcm_reg_id = 1, 978 .module_bit = OMAP3430_EN_GPIO3_SHIFT, 979 .module_offs = OMAP3430_PER_MOD, 980 .idlest_reg_id = 1, 981 .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT, 982 }, 983 }, 984 .class = &omap3xxx_gpio_hwmod_class, 985 .dev_attr = &gpio_dev_attr, 986}; 987 988/* gpio4 */ 989static struct omap_hwmod_opt_clk gpio4_opt_clks[] = { 990 { .role = "dbclk", .clk = "gpio4_dbck", }, 991}; 992 993static struct omap_hwmod omap3xxx_gpio4_hwmod = { 994 .name = "gpio4", 995 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 996 .mpu_irqs = omap2_gpio4_irqs, 997 .main_clk = "gpio4_ick", 998 .opt_clks = gpio4_opt_clks, 999 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks), 1000 .prcm = { 1001 .omap2 = { 1002 .prcm_reg_id = 1, 1003 .module_bit = OMAP3430_EN_GPIO4_SHIFT, 1004 .module_offs = OMAP3430_PER_MOD, 1005 .idlest_reg_id = 1, 1006 .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT, 1007 }, 1008 }, 1009 .class = &omap3xxx_gpio_hwmod_class, 1010 .dev_attr = &gpio_dev_attr, 1011}; 1012 1013/* gpio5 */ 1014static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = { 1015 { .irq = 33 + OMAP_INTC_START, }, /* INT_34XX_GPIO_BANK5 */ 1016 { .irq = -1 }, 1017}; 1018 1019static struct omap_hwmod_opt_clk gpio5_opt_clks[] = { 1020 { .role = "dbclk", .clk = "gpio5_dbck", }, 1021}; 1022 1023static struct omap_hwmod omap3xxx_gpio5_hwmod = { 1024 .name = "gpio5", 1025 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 1026 .mpu_irqs = omap3xxx_gpio5_irqs, 1027 .main_clk = "gpio5_ick", 1028 .opt_clks = gpio5_opt_clks, 1029 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks), 1030 .prcm = { 1031 .omap2 = { 1032 .prcm_reg_id = 1, 1033 .module_bit = OMAP3430_EN_GPIO5_SHIFT, 1034 .module_offs = OMAP3430_PER_MOD, 1035 .idlest_reg_id = 1, 1036 .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT, 1037 }, 1038 }, 1039 .class = &omap3xxx_gpio_hwmod_class, 1040 .dev_attr = &gpio_dev_attr, 1041}; 1042 1043/* gpio6 */ 1044static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = { 1045 { .irq = 34 + OMAP_INTC_START, }, /* INT_34XX_GPIO_BANK6 */ 1046 { .irq = -1 }, 1047}; 1048 1049static struct omap_hwmod_opt_clk gpio6_opt_clks[] = { 1050 { .role = "dbclk", .clk = "gpio6_dbck", }, 1051}; 1052 1053static struct omap_hwmod omap3xxx_gpio6_hwmod = { 1054 .name = "gpio6", 1055 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 1056 .mpu_irqs = omap3xxx_gpio6_irqs, 1057 .main_clk = "gpio6_ick", 1058 .opt_clks = gpio6_opt_clks, 1059 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks), 1060 .prcm = { 1061 .omap2 = { 1062 .prcm_reg_id = 1, 1063 .module_bit = OMAP3430_EN_GPIO6_SHIFT, 1064 .module_offs = OMAP3430_PER_MOD, 1065 .idlest_reg_id = 1, 1066 .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT, 1067 }, 1068 }, 1069 .class = &omap3xxx_gpio_hwmod_class, 1070 .dev_attr = &gpio_dev_attr, 1071}; 1072 1073/* dma attributes */ 1074static struct omap_dma_dev_attr dma_dev_attr = { 1075 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | 1076 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY, 1077 .lch_count = 32, 1078}; 1079 1080static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = { 1081 .rev_offs = 0x0000, 1082 .sysc_offs = 0x002c, 1083 .syss_offs = 0x0028, 1084 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | 1085 SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY | 1086 SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE | 1087 SYSS_HAS_RESET_STATUS), 1088 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 1089 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), 1090 .sysc_fields = &omap_hwmod_sysc_type1, 1091}; 1092 1093static struct omap_hwmod_class omap3xxx_dma_hwmod_class = { 1094 .name = "dma", 1095 .sysc = &omap3xxx_dma_sysc, 1096}; 1097 1098/* dma_system */ 1099static struct omap_hwmod omap3xxx_dma_system_hwmod = { 1100 .name = "dma", 1101 .class = &omap3xxx_dma_hwmod_class, 1102 .mpu_irqs = omap2_dma_system_irqs, 1103 .main_clk = "core_l3_ick", 1104 .prcm = { 1105 .omap2 = { 1106 .module_offs = CORE_MOD, 1107 .prcm_reg_id = 1, 1108 .module_bit = OMAP3430_ST_SDMA_SHIFT, 1109 .idlest_reg_id = 1, 1110 .idlest_idle_bit = OMAP3430_ST_SDMA_SHIFT, 1111 }, 1112 }, 1113 .dev_attr = &dma_dev_attr, 1114 .flags = HWMOD_NO_IDLEST, 1115}; 1116 1117/* 1118 * 'mcbsp' class 1119 * multi channel buffered serial port controller 1120 */ 1121 1122static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sysc = { 1123 .sysc_offs = 0x008c, 1124 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP | 1125 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), 1126 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 1127 .sysc_fields = &omap_hwmod_sysc_type1, 1128 .clockact = 0x2, 1129}; 1130 1131static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = { 1132 .name = "mcbsp", 1133 .sysc = &omap3xxx_mcbsp_sysc, 1134 .rev = MCBSP_CONFIG_TYPE3, 1135}; 1136 1137/* McBSP functional clock mapping */ 1138static struct omap_hwmod_opt_clk mcbsp15_opt_clks[] = { 1139 { .role = "pad_fck", .clk = "mcbsp_clks" }, 1140 { .role = "prcm_fck", .clk = "core_96m_fck" }, 1141}; 1142 1143static struct omap_hwmod_opt_clk mcbsp234_opt_clks[] = { 1144 { .role = "pad_fck", .clk = "mcbsp_clks" }, 1145 { .role = "prcm_fck", .clk = "per_96m_fck" }, 1146}; 1147 1148/* mcbsp1 */ 1149static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = { 1150 { .name = "common", .irq = 16 + OMAP_INTC_START, }, 1151 { .name = "tx", .irq = 59 + OMAP_INTC_START, }, 1152 { .name = "rx", .irq = 60 + OMAP_INTC_START, }, 1153 { .irq = -1 }, 1154}; 1155 1156static struct omap_hwmod omap3xxx_mcbsp1_hwmod = { 1157 .name = "mcbsp1", 1158 .class = &omap3xxx_mcbsp_hwmod_class, 1159 .mpu_irqs = omap3xxx_mcbsp1_irqs, 1160 .sdma_reqs = omap2_mcbsp1_sdma_reqs, 1161 .main_clk = "mcbsp1_fck", 1162 .prcm = { 1163 .omap2 = { 1164 .prcm_reg_id = 1, 1165 .module_bit = OMAP3430_EN_MCBSP1_SHIFT, 1166 .module_offs = CORE_MOD, 1167 .idlest_reg_id = 1, 1168 .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT, 1169 }, 1170 }, 1171 .opt_clks = mcbsp15_opt_clks, 1172 .opt_clks_cnt = ARRAY_SIZE(mcbsp15_opt_clks), 1173}; 1174 1175/* mcbsp2 */ 1176static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = { 1177 { .name = "common", .irq = 17 + OMAP_INTC_START, }, 1178 { .name = "tx", .irq = 62 + OMAP_INTC_START, }, 1179 { .name = "rx", .irq = 63 + OMAP_INTC_START, }, 1180 { .irq = -1 }, 1181}; 1182 1183static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = { 1184 .sidetone = "mcbsp2_sidetone", 1185}; 1186 1187static struct omap_hwmod omap3xxx_mcbsp2_hwmod = { 1188 .name = "mcbsp2", 1189 .class = &omap3xxx_mcbsp_hwmod_class, 1190 .mpu_irqs = omap3xxx_mcbsp2_irqs, 1191 .sdma_reqs = omap2_mcbsp2_sdma_reqs, 1192 .main_clk = "mcbsp2_fck", 1193 .prcm = { 1194 .omap2 = { 1195 .prcm_reg_id = 1, 1196 .module_bit = OMAP3430_EN_MCBSP2_SHIFT, 1197 .module_offs = OMAP3430_PER_MOD, 1198 .idlest_reg_id = 1, 1199 .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT, 1200 }, 1201 }, 1202 .opt_clks = mcbsp234_opt_clks, 1203 .opt_clks_cnt = ARRAY_SIZE(mcbsp234_opt_clks), 1204 .dev_attr = &omap34xx_mcbsp2_dev_attr, 1205}; 1206 1207/* mcbsp3 */ 1208static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = { 1209 { .name = "common", .irq = 22 + OMAP_INTC_START, }, 1210 { .name = "tx", .irq = 89 + OMAP_INTC_START, }, 1211 { .name = "rx", .irq = 90 + OMAP_INTC_START, }, 1212 { .irq = -1 }, 1213}; 1214 1215static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = { 1216 .sidetone = "mcbsp3_sidetone", 1217}; 1218 1219static struct omap_hwmod omap3xxx_mcbsp3_hwmod = { 1220 .name = "mcbsp3", 1221 .class = &omap3xxx_mcbsp_hwmod_class, 1222 .mpu_irqs = omap3xxx_mcbsp3_irqs, 1223 .sdma_reqs = omap2_mcbsp3_sdma_reqs, 1224 .main_clk = "mcbsp3_fck", 1225 .prcm = { 1226 .omap2 = { 1227 .prcm_reg_id = 1, 1228 .module_bit = OMAP3430_EN_MCBSP3_SHIFT, 1229 .module_offs = OMAP3430_PER_MOD, 1230 .idlest_reg_id = 1, 1231 .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT, 1232 }, 1233 }, 1234 .opt_clks = mcbsp234_opt_clks, 1235 .opt_clks_cnt = ARRAY_SIZE(mcbsp234_opt_clks), 1236 .dev_attr = &omap34xx_mcbsp3_dev_attr, 1237}; 1238 1239/* mcbsp4 */ 1240static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = { 1241 { .name = "common", .irq = 23 + OMAP_INTC_START, }, 1242 { .name = "tx", .irq = 54 + OMAP_INTC_START, }, 1243 { .name = "rx", .irq = 55 + OMAP_INTC_START, }, 1244 { .irq = -1 }, 1245}; 1246 1247static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = { 1248 { .name = "rx", .dma_req = 20 }, 1249 { .name = "tx", .dma_req = 19 }, 1250 { .dma_req = -1 } 1251}; 1252 1253static struct omap_hwmod omap3xxx_mcbsp4_hwmod = { 1254 .name = "mcbsp4", 1255 .class = &omap3xxx_mcbsp_hwmod_class, 1256 .mpu_irqs = omap3xxx_mcbsp4_irqs, 1257 .sdma_reqs = omap3xxx_mcbsp4_sdma_chs, 1258 .main_clk = "mcbsp4_fck", 1259 .prcm = { 1260 .omap2 = { 1261 .prcm_reg_id = 1, 1262 .module_bit = OMAP3430_EN_MCBSP4_SHIFT, 1263 .module_offs = OMAP3430_PER_MOD, 1264 .idlest_reg_id = 1, 1265 .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT, 1266 }, 1267 }, 1268 .opt_clks = mcbsp234_opt_clks, 1269 .opt_clks_cnt = ARRAY_SIZE(mcbsp234_opt_clks), 1270}; 1271 1272/* mcbsp5 */ 1273static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = { 1274 { .name = "common", .irq = 27 + OMAP_INTC_START, }, 1275 { .name = "tx", .irq = 81 + OMAP_INTC_START, }, 1276 { .name = "rx", .irq = 82 + OMAP_INTC_START, }, 1277 { .irq = -1 }, 1278}; 1279 1280static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = { 1281 { .name = "rx", .dma_req = 22 }, 1282 { .name = "tx", .dma_req = 21 }, 1283 { .dma_req = -1 } 1284}; 1285 1286static struct omap_hwmod omap3xxx_mcbsp5_hwmod = { 1287 .name = "mcbsp5", 1288 .class = &omap3xxx_mcbsp_hwmod_class, 1289 .mpu_irqs = omap3xxx_mcbsp5_irqs, 1290 .sdma_reqs = omap3xxx_mcbsp5_sdma_chs, 1291 .main_clk = "mcbsp5_fck", 1292 .prcm = { 1293 .omap2 = { 1294 .prcm_reg_id = 1, 1295 .module_bit = OMAP3430_EN_MCBSP5_SHIFT, 1296 .module_offs = CORE_MOD, 1297 .idlest_reg_id = 1, 1298 .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT, 1299 }, 1300 }, 1301 .opt_clks = mcbsp15_opt_clks, 1302 .opt_clks_cnt = ARRAY_SIZE(mcbsp15_opt_clks), 1303}; 1304 1305/* 'mcbsp sidetone' class */ 1306static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = { 1307 .sysc_offs = 0x0010, 1308 .sysc_flags = SYSC_HAS_AUTOIDLE, 1309 .sysc_fields = &omap_hwmod_sysc_type1, 1310}; 1311 1312static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = { 1313 .name = "mcbsp_sidetone", 1314 .sysc = &omap3xxx_mcbsp_sidetone_sysc, 1315}; 1316 1317/* mcbsp2_sidetone */ 1318static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = { 1319 { .name = "irq", .irq = 4 + OMAP_INTC_START, }, 1320 { .irq = -1 }, 1321}; 1322 1323static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = { 1324 .name = "mcbsp2_sidetone", 1325 .class = &omap3xxx_mcbsp_sidetone_hwmod_class, 1326 .mpu_irqs = omap3xxx_mcbsp2_sidetone_irqs, 1327 .main_clk = "mcbsp2_fck", 1328 .prcm = { 1329 .omap2 = { 1330 .prcm_reg_id = 1, 1331 .module_bit = OMAP3430_EN_MCBSP2_SHIFT, 1332 .module_offs = OMAP3430_PER_MOD, 1333 .idlest_reg_id = 1, 1334 .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT, 1335 }, 1336 }, 1337}; 1338 1339/* mcbsp3_sidetone */ 1340static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = { 1341 { .name = "irq", .irq = 5 + OMAP_INTC_START, }, 1342 { .irq = -1 }, 1343}; 1344 1345static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = { 1346 .name = "mcbsp3_sidetone", 1347 .class = &omap3xxx_mcbsp_sidetone_hwmod_class, 1348 .mpu_irqs = omap3xxx_mcbsp3_sidetone_irqs, 1349 .main_clk = "mcbsp3_fck", 1350 .prcm = { 1351 .omap2 = { 1352 .prcm_reg_id = 1, 1353 .module_bit = OMAP3430_EN_MCBSP3_SHIFT, 1354 .module_offs = OMAP3430_PER_MOD, 1355 .idlest_reg_id = 1, 1356 .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT, 1357 }, 1358 }, 1359}; 1360 1361/* SR common */ 1362static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = { 1363 .clkact_shift = 20, 1364}; 1365 1366static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = { 1367 .sysc_offs = 0x24, 1368 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE), 1369 .clockact = CLOCKACT_TEST_ICLK, 1370 .sysc_fields = &omap34xx_sr_sysc_fields, 1371}; 1372 1373static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = { 1374 .name = "smartreflex", 1375 .sysc = &omap34xx_sr_sysc, 1376 .rev = 1, 1377}; 1378 1379static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = { 1380 .sidle_shift = 24, 1381 .enwkup_shift = 26, 1382}; 1383 1384static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = { 1385 .sysc_offs = 0x38, 1386 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 1387 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP | 1388 SYSC_NO_CACHE), 1389 .sysc_fields = &omap36xx_sr_sysc_fields, 1390}; 1391 1392static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = { 1393 .name = "smartreflex", 1394 .sysc = &omap36xx_sr_sysc, 1395 .rev = 2, 1396}; 1397 1398/* SR1 */ 1399static struct omap_smartreflex_dev_attr sr1_dev_attr = { 1400 .sensor_voltdm_name = "mpu_iva", 1401}; 1402 1403static struct omap_hwmod_irq_info omap3_smartreflex_mpu_irqs[] = { 1404 { .irq = 18 + OMAP_INTC_START, }, 1405 { .irq = -1 }, 1406}; 1407 1408static struct omap_hwmod omap34xx_sr1_hwmod = { 1409 .name = "smartreflex_mpu_iva", 1410 .class = &omap34xx_smartreflex_hwmod_class, 1411 .main_clk = "sr1_fck", 1412 .prcm = { 1413 .omap2 = { 1414 .prcm_reg_id = 1, 1415 .module_bit = OMAP3430_EN_SR1_SHIFT, 1416 .module_offs = WKUP_MOD, 1417 .idlest_reg_id = 1, 1418 .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT, 1419 }, 1420 }, 1421 .dev_attr = &sr1_dev_attr, 1422 .mpu_irqs = omap3_smartreflex_mpu_irqs, 1423 .flags = HWMOD_SET_DEFAULT_CLOCKACT, 1424}; 1425 1426static struct omap_hwmod omap36xx_sr1_hwmod = { 1427 .name = "smartreflex_mpu_iva", 1428 .class = &omap36xx_smartreflex_hwmod_class, 1429 .main_clk = "sr1_fck", 1430 .prcm = { 1431 .omap2 = { 1432 .prcm_reg_id = 1, 1433 .module_bit = OMAP3430_EN_SR1_SHIFT, 1434 .module_offs = WKUP_MOD, 1435 .idlest_reg_id = 1, 1436 .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT, 1437 }, 1438 }, 1439 .dev_attr = &sr1_dev_attr, 1440 .mpu_irqs = omap3_smartreflex_mpu_irqs, 1441}; 1442 1443/* SR2 */ 1444static struct omap_smartreflex_dev_attr sr2_dev_attr = { 1445 .sensor_voltdm_name = "core", 1446}; 1447 1448static struct omap_hwmod_irq_info omap3_smartreflex_core_irqs[] = { 1449 { .irq = 19 + OMAP_INTC_START, }, 1450 { .irq = -1 }, 1451}; 1452 1453static struct omap_hwmod omap34xx_sr2_hwmod = { 1454 .name = "smartreflex_core", 1455 .class = &omap34xx_smartreflex_hwmod_class, 1456 .main_clk = "sr2_fck", 1457 .prcm = { 1458 .omap2 = { 1459 .prcm_reg_id = 1, 1460 .module_bit = OMAP3430_EN_SR2_SHIFT, 1461 .module_offs = WKUP_MOD, 1462 .idlest_reg_id = 1, 1463 .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT, 1464 }, 1465 }, 1466 .dev_attr = &sr2_dev_attr, 1467 .mpu_irqs = omap3_smartreflex_core_irqs, 1468 .flags = HWMOD_SET_DEFAULT_CLOCKACT, 1469}; 1470 1471static struct omap_hwmod omap36xx_sr2_hwmod = { 1472 .name = "smartreflex_core", 1473 .class = &omap36xx_smartreflex_hwmod_class, 1474 .main_clk = "sr2_fck", 1475 .prcm = { 1476 .omap2 = { 1477 .prcm_reg_id = 1, 1478 .module_bit = OMAP3430_EN_SR2_SHIFT, 1479 .module_offs = WKUP_MOD, 1480 .idlest_reg_id = 1, 1481 .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT, 1482 }, 1483 }, 1484 .dev_attr = &sr2_dev_attr, 1485 .mpu_irqs = omap3_smartreflex_core_irqs, 1486}; 1487 1488/* 1489 * 'mailbox' class 1490 * mailbox module allowing communication between the on-chip processors 1491 * using a queued mailbox-interrupt mechanism. 1492 */ 1493 1494static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc = { 1495 .rev_offs = 0x000, 1496 .sysc_offs = 0x010, 1497 .syss_offs = 0x014, 1498 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | 1499 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), 1500 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 1501 .sysc_fields = &omap_hwmod_sysc_type1, 1502}; 1503 1504static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = { 1505 .name = "mailbox", 1506 .sysc = &omap3xxx_mailbox_sysc, 1507}; 1508 1509static struct omap_mbox_dev_info omap3xxx_mailbox_info[] = { 1510 { .name = "dsp", .tx_id = 0, .rx_id = 1 }, 1511}; 1512 1513static struct omap_mbox_pdata omap3xxx_mailbox_attrs = { 1514 .num_users = 2, 1515 .num_fifos = 2, 1516 .info_cnt = ARRAY_SIZE(omap3xxx_mailbox_info), 1517 .info = omap3xxx_mailbox_info, 1518}; 1519 1520static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = { 1521 { .irq = 26 + OMAP_INTC_START, }, 1522 { .irq = -1 }, 1523}; 1524 1525static struct omap_hwmod omap3xxx_mailbox_hwmod = { 1526 .name = "mailbox", 1527 .class = &omap3xxx_mailbox_hwmod_class, 1528 .mpu_irqs = omap3xxx_mailbox_irqs, 1529 .main_clk = "mailboxes_ick", 1530 .prcm = { 1531 .omap2 = { 1532 .prcm_reg_id = 1, 1533 .module_bit = OMAP3430_EN_MAILBOXES_SHIFT, 1534 .module_offs = CORE_MOD, 1535 .idlest_reg_id = 1, 1536 .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT, 1537 }, 1538 }, 1539 .dev_attr = &omap3xxx_mailbox_attrs, 1540}; 1541 1542/* 1543 * 'mcspi' class 1544 * multichannel serial port interface (mcspi) / master/slave synchronous serial 1545 * bus 1546 */ 1547 1548static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = { 1549 .rev_offs = 0x0000, 1550 .sysc_offs = 0x0010, 1551 .syss_offs = 0x0014, 1552 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | 1553 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | 1554 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), 1555 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 1556 .sysc_fields = &omap_hwmod_sysc_type1, 1557}; 1558 1559static struct omap_hwmod_class omap34xx_mcspi_class = { 1560 .name = "mcspi", 1561 .sysc = &omap34xx_mcspi_sysc, 1562 .rev = OMAP3_MCSPI_REV, 1563}; 1564 1565/* mcspi1 */ 1566static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = { 1567 .num_chipselect = 4, 1568}; 1569 1570static struct omap_hwmod omap34xx_mcspi1 = { 1571 .name = "mcspi1", 1572 .mpu_irqs = omap2_mcspi1_mpu_irqs, 1573 .sdma_reqs = omap2_mcspi1_sdma_reqs, 1574 .main_clk = "mcspi1_fck", 1575 .prcm = { 1576 .omap2 = { 1577 .module_offs = CORE_MOD, 1578 .prcm_reg_id = 1, 1579 .module_bit = OMAP3430_EN_MCSPI1_SHIFT, 1580 .idlest_reg_id = 1, 1581 .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT, 1582 }, 1583 }, 1584 .class = &omap34xx_mcspi_class, 1585 .dev_attr = &omap_mcspi1_dev_attr, 1586}; 1587 1588/* mcspi2 */ 1589static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = { 1590 .num_chipselect = 2, 1591}; 1592 1593static struct omap_hwmod omap34xx_mcspi2 = { 1594 .name = "mcspi2", 1595 .mpu_irqs = omap2_mcspi2_mpu_irqs, 1596 .sdma_reqs = omap2_mcspi2_sdma_reqs, 1597 .main_clk = "mcspi2_fck", 1598 .prcm = { 1599 .omap2 = { 1600 .module_offs = CORE_MOD, 1601 .prcm_reg_id = 1, 1602 .module_bit = OMAP3430_EN_MCSPI2_SHIFT, 1603 .idlest_reg_id = 1, 1604 .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT, 1605 }, 1606 }, 1607 .class = &omap34xx_mcspi_class, 1608 .dev_attr = &omap_mcspi2_dev_attr, 1609}; 1610 1611/* mcspi3 */ 1612static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = { 1613 { .name = "irq", .irq = 91 + OMAP_INTC_START, }, /* 91 */ 1614 { .irq = -1 }, 1615}; 1616 1617static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = { 1618 { .name = "tx0", .dma_req = 15 }, 1619 { .name = "rx0", .dma_req = 16 }, 1620 { .name = "tx1", .dma_req = 23 }, 1621 { .name = "rx1", .dma_req = 24 }, 1622 { .dma_req = -1 } 1623}; 1624 1625static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = { 1626 .num_chipselect = 2, 1627}; 1628 1629static struct omap_hwmod omap34xx_mcspi3 = { 1630 .name = "mcspi3", 1631 .mpu_irqs = omap34xx_mcspi3_mpu_irqs, 1632 .sdma_reqs = omap34xx_mcspi3_sdma_reqs, 1633 .main_clk = "mcspi3_fck", 1634 .prcm = { 1635 .omap2 = { 1636 .module_offs = CORE_MOD, 1637 .prcm_reg_id = 1, 1638 .module_bit = OMAP3430_EN_MCSPI3_SHIFT, 1639 .idlest_reg_id = 1, 1640 .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT, 1641 }, 1642 }, 1643 .class = &omap34xx_mcspi_class, 1644 .dev_attr = &omap_mcspi3_dev_attr, 1645}; 1646 1647/* mcspi4 */ 1648static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = { 1649 { .name = "irq", .irq = 48 + OMAP_INTC_START, }, 1650 { .irq = -1 }, 1651}; 1652 1653static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = { 1654 { .name = "tx0", .dma_req = 70 }, /* DMA_SPI4_TX0 */ 1655 { .name = "rx0", .dma_req = 71 }, /* DMA_SPI4_RX0 */ 1656 { .dma_req = -1 } 1657}; 1658 1659static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = { 1660 .num_chipselect = 1, 1661}; 1662 1663static struct omap_hwmod omap34xx_mcspi4 = { 1664 .name = "mcspi4", 1665 .mpu_irqs = omap34xx_mcspi4_mpu_irqs, 1666 .sdma_reqs = omap34xx_mcspi4_sdma_reqs, 1667 .main_clk = "mcspi4_fck", 1668 .prcm = { 1669 .omap2 = { 1670 .module_offs = CORE_MOD, 1671 .prcm_reg_id = 1, 1672 .module_bit = OMAP3430_EN_MCSPI4_SHIFT, 1673 .idlest_reg_id = 1, 1674 .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT, 1675 }, 1676 }, 1677 .class = &omap34xx_mcspi_class, 1678 .dev_attr = &omap_mcspi4_dev_attr, 1679}; 1680 1681/* usbhsotg */ 1682static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = { 1683 .rev_offs = 0x0400, 1684 .sysc_offs = 0x0404, 1685 .syss_offs = 0x0408, 1686 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE| 1687 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | 1688 SYSC_HAS_AUTOIDLE), 1689 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 1690 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), 1691 .sysc_fields = &omap_hwmod_sysc_type1, 1692}; 1693 1694static struct omap_hwmod_class usbotg_class = { 1695 .name = "usbotg", 1696 .sysc = &omap3xxx_usbhsotg_sysc, 1697}; 1698 1699/* usb_otg_hs */ 1700static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = { 1701 1702 { .name = "mc", .irq = 92 + OMAP_INTC_START, }, 1703 { .name = "dma", .irq = 93 + OMAP_INTC_START, }, 1704 { .irq = -1 }, 1705}; 1706 1707static struct omap_hwmod omap3xxx_usbhsotg_hwmod = { 1708 .name = "usb_otg_hs", 1709 .mpu_irqs = omap3xxx_usbhsotg_mpu_irqs, 1710 .main_clk = "hsotgusb_ick", 1711 .prcm = { 1712 .omap2 = { 1713 .prcm_reg_id = 1, 1714 .module_bit = OMAP3430_EN_HSOTGUSB_SHIFT, 1715 .module_offs = CORE_MOD, 1716 .idlest_reg_id = 1, 1717 .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT, 1718 .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT 1719 }, 1720 }, 1721 .class = &usbotg_class, 1722 1723 /* 1724 * Erratum ID: i479 idle_req / idle_ack mechanism potentially 1725 * broken when autoidle is enabled 1726 * workaround is to disable the autoidle bit at module level. 1727 * 1728 * Enabling the device in any other MIDLEMODE setting but force-idle 1729 * causes core_pwrdm not enter idle states at least on OMAP3630. 1730 * Note that musb has OTG_FORCESTDBY register that controls MSTANDBY 1731 * signal when MIDLEMODE is set to force-idle. 1732 */ 1733 .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE | 1734 HWMOD_FORCE_MSTANDBY | HWMOD_RECONFIG_IO_CHAIN, 1735}; 1736 1737/* usb_otg_hs */ 1738static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = { 1739 { .name = "mc", .irq = 71 + OMAP_INTC_START, }, 1740 { .irq = -1 }, 1741}; 1742 1743static struct omap_hwmod_class am35xx_usbotg_class = { 1744 .name = "am35xx_usbotg", 1745}; 1746 1747static struct omap_hwmod am35xx_usbhsotg_hwmod = { 1748 .name = "am35x_otg_hs", 1749 .mpu_irqs = am35xx_usbhsotg_mpu_irqs, 1750 .main_clk = "hsotgusb_fck", 1751 .class = &am35xx_usbotg_class, 1752 .flags = HWMOD_NO_IDLEST, 1753}; 1754 1755/* MMC/SD/SDIO common */ 1756static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = { 1757 .rev_offs = 0x1fc, 1758 .sysc_offs = 0x10, 1759 .syss_offs = 0x14, 1760 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | 1761 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | 1762 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), 1763 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 1764 .sysc_fields = &omap_hwmod_sysc_type1, 1765}; 1766 1767static struct omap_hwmod_class omap34xx_mmc_class = { 1768 .name = "mmc", 1769 .sysc = &omap34xx_mmc_sysc, 1770}; 1771 1772/* MMC/SD/SDIO1 */ 1773 1774static struct omap_hwmod_irq_info omap34xx_mmc1_mpu_irqs[] = { 1775 { .irq = 83 + OMAP_INTC_START, }, 1776 { .irq = -1 }, 1777}; 1778 1779static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs[] = { 1780 { .name = "tx", .dma_req = 61, }, 1781 { .name = "rx", .dma_req = 62, }, 1782 { .dma_req = -1 } 1783}; 1784 1785static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = { 1786 { .role = "dbck", .clk = "omap_32k_fck", }, 1787}; 1788 1789static struct omap_hsmmc_dev_attr mmc1_dev_attr = { 1790 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, 1791}; 1792 1793/* See 35xx errata 2.1.1.128 in SPRZ278F */ 1794static struct omap_hsmmc_dev_attr mmc1_pre_es3_dev_attr = { 1795 .flags = (OMAP_HSMMC_SUPPORTS_DUAL_VOLT | 1796 OMAP_HSMMC_BROKEN_MULTIBLOCK_READ), 1797}; 1798 1799static struct omap_hwmod omap3xxx_pre_es3_mmc1_hwmod = { 1800 .name = "mmc1", 1801 .mpu_irqs = omap34xx_mmc1_mpu_irqs, 1802 .sdma_reqs = omap34xx_mmc1_sdma_reqs, 1803 .opt_clks = omap34xx_mmc1_opt_clks, 1804 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks), 1805 .main_clk = "mmchs1_fck", 1806 .prcm = { 1807 .omap2 = { 1808 .module_offs = CORE_MOD, 1809 .prcm_reg_id = 1, 1810 .module_bit = OMAP3430_EN_MMC1_SHIFT, 1811 .idlest_reg_id = 1, 1812 .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT, 1813 }, 1814 }, 1815 .dev_attr = &mmc1_pre_es3_dev_attr, 1816 .class = &omap34xx_mmc_class, 1817}; 1818 1819static struct omap_hwmod omap3xxx_es3plus_mmc1_hwmod = { 1820 .name = "mmc1", 1821 .mpu_irqs = omap34xx_mmc1_mpu_irqs, 1822 .sdma_reqs = omap34xx_mmc1_sdma_reqs, 1823 .opt_clks = omap34xx_mmc1_opt_clks, 1824 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks), 1825 .main_clk = "mmchs1_fck", 1826 .prcm = { 1827 .omap2 = { 1828 .module_offs = CORE_MOD, 1829 .prcm_reg_id = 1, 1830 .module_bit = OMAP3430_EN_MMC1_SHIFT, 1831 .idlest_reg_id = 1, 1832 .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT, 1833 }, 1834 }, 1835 .dev_attr = &mmc1_dev_attr, 1836 .class = &omap34xx_mmc_class, 1837}; 1838 1839/* MMC/SD/SDIO2 */ 1840 1841static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs[] = { 1842 { .irq = 86 + OMAP_INTC_START, }, 1843 { .irq = -1 }, 1844}; 1845 1846static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs[] = { 1847 { .name = "tx", .dma_req = 47, }, 1848 { .name = "rx", .dma_req = 48, }, 1849 { .dma_req = -1 } 1850}; 1851 1852static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = { 1853 { .role = "dbck", .clk = "omap_32k_fck", }, 1854}; 1855 1856/* See 35xx errata 2.1.1.128 in SPRZ278F */ 1857static struct omap_hsmmc_dev_attr mmc2_pre_es3_dev_attr = { 1858 .flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ, 1859}; 1860 1861static struct omap_hwmod omap3xxx_pre_es3_mmc2_hwmod = { 1862 .name = "mmc2", 1863 .mpu_irqs = omap34xx_mmc2_mpu_irqs, 1864 .sdma_reqs = omap34xx_mmc2_sdma_reqs, 1865 .opt_clks = omap34xx_mmc2_opt_clks, 1866 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks), 1867 .main_clk = "mmchs2_fck", 1868 .prcm = { 1869 .omap2 = { 1870 .module_offs = CORE_MOD, 1871 .prcm_reg_id = 1, 1872 .module_bit = OMAP3430_EN_MMC2_SHIFT, 1873 .idlest_reg_id = 1, 1874 .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT, 1875 }, 1876 }, 1877 .dev_attr = &mmc2_pre_es3_dev_attr, 1878 .class = &omap34xx_mmc_class, 1879}; 1880 1881static struct omap_hwmod omap3xxx_es3plus_mmc2_hwmod = { 1882 .name = "mmc2", 1883 .mpu_irqs = omap34xx_mmc2_mpu_irqs, 1884 .sdma_reqs = omap34xx_mmc2_sdma_reqs, 1885 .opt_clks = omap34xx_mmc2_opt_clks, 1886 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks), 1887 .main_clk = "mmchs2_fck", 1888 .prcm = { 1889 .omap2 = { 1890 .module_offs = CORE_MOD, 1891 .prcm_reg_id = 1, 1892 .module_bit = OMAP3430_EN_MMC2_SHIFT, 1893 .idlest_reg_id = 1, 1894 .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT, 1895 }, 1896 }, 1897 .class = &omap34xx_mmc_class, 1898}; 1899 1900/* MMC/SD/SDIO3 */ 1901 1902static struct omap_hwmod_irq_info omap34xx_mmc3_mpu_irqs[] = { 1903 { .irq = 94 + OMAP_INTC_START, }, 1904 { .irq = -1 }, 1905}; 1906 1907static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs[] = { 1908 { .name = "tx", .dma_req = 77, }, 1909 { .name = "rx", .dma_req = 78, }, 1910 { .dma_req = -1 } 1911}; 1912 1913static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = { 1914 { .role = "dbck", .clk = "omap_32k_fck", }, 1915}; 1916 1917static struct omap_hwmod omap3xxx_mmc3_hwmod = { 1918 .name = "mmc3", 1919 .mpu_irqs = omap34xx_mmc3_mpu_irqs, 1920 .sdma_reqs = omap34xx_mmc3_sdma_reqs, 1921 .opt_clks = omap34xx_mmc3_opt_clks, 1922 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc3_opt_clks), 1923 .main_clk = "mmchs3_fck", 1924 .prcm = { 1925 .omap2 = { 1926 .prcm_reg_id = 1, 1927 .module_bit = OMAP3430_EN_MMC3_SHIFT, 1928 .idlest_reg_id = 1, 1929 .idlest_idle_bit = OMAP3430_ST_MMC3_SHIFT, 1930 }, 1931 }, 1932 .class = &omap34xx_mmc_class, 1933}; 1934 1935/* 1936 * 'usb_host_hs' class 1937 * high-speed multi-port usb host controller 1938 */ 1939 1940static struct omap_hwmod_class_sysconfig omap3xxx_usb_host_hs_sysc = { 1941 .rev_offs = 0x0000, 1942 .sysc_offs = 0x0010, 1943 .syss_offs = 0x0014, 1944 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY | 1945 SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP | 1946 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | 1947 SYSS_HAS_RESET_STATUS), 1948 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 1949 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), 1950 .sysc_fields = &omap_hwmod_sysc_type1, 1951}; 1952 1953static struct omap_hwmod_class omap3xxx_usb_host_hs_hwmod_class = { 1954 .name = "usb_host_hs", 1955 .sysc = &omap3xxx_usb_host_hs_sysc, 1956}; 1957 1958static struct omap_hwmod_irq_info omap3xxx_usb_host_hs_irqs[] = { 1959 { .name = "ohci-irq", .irq = 76 + OMAP_INTC_START, }, 1960 { .name = "ehci-irq", .irq = 77 + OMAP_INTC_START, }, 1961 { .irq = -1 }, 1962}; 1963 1964static struct omap_hwmod omap3xxx_usb_host_hs_hwmod = { 1965 .name = "usb_host_hs", 1966 .class = &omap3xxx_usb_host_hs_hwmod_class, 1967 .clkdm_name = "usbhost_clkdm", 1968 .mpu_irqs = omap3xxx_usb_host_hs_irqs, 1969 .main_clk = "usbhost_48m_fck", 1970 .prcm = { 1971 .omap2 = { 1972 .module_offs = OMAP3430ES2_USBHOST_MOD, 1973 .prcm_reg_id = 1, 1974 .module_bit = OMAP3430ES2_EN_USBHOST1_SHIFT, 1975 .idlest_reg_id = 1, 1976 .idlest_idle_bit = OMAP3430ES2_ST_USBHOST_IDLE_SHIFT, 1977 .idlest_stdby_bit = OMAP3430ES2_ST_USBHOST_STDBY_SHIFT, 1978 }, 1979 }, 1980 1981 /* 1982 * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock 1983 * id: i660 1984 * 1985 * Description: 1986 * In the following configuration : 1987 * - USBHOST module is set to smart-idle mode 1988 * - PRCM asserts idle_req to the USBHOST module ( This typically 1989 * happens when the system is going to a low power mode : all ports 1990 * have been suspended, the master part of the USBHOST module has 1991 * entered the standby state, and SW has cut the functional clocks) 1992 * - an USBHOST interrupt occurs before the module is able to answer 1993 * idle_ack, typically a remote wakeup IRQ. 1994 * Then the USB HOST module will enter a deadlock situation where it 1995 * is no more accessible nor functional. 1996 * 1997 * Workaround: 1998 * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE 1999 */ 2000 2001 /* 2002 * Errata: USB host EHCI may stall when entering smart-standby mode 2003 * Id: i571 2004 * 2005 * Description: 2006 * When the USBHOST module is set to smart-standby mode, and when it is 2007 * ready to enter the standby state (i.e. all ports are suspended and 2008 * all attached devices are in suspend mode), then it can wrongly assert 2009 * the Mstandby signal too early while there are still some residual OCP 2010 * transactions ongoing. If this condition occurs, the internal state 2011 * machine may go to an undefined state and the USB link may be stuck 2012 * upon the next resume. 2013 * 2014 * Workaround: 2015 * Don't use smart standby; use only force standby, 2016 * hence HWMOD_SWSUP_MSTANDBY 2017 */ 2018 2019 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY, 2020}; 2021 2022/* 2023 * 'usb_tll_hs' class 2024 * usb_tll_hs module is the adapter on the usb_host_hs ports 2025 */ 2026static struct omap_hwmod_class_sysconfig omap3xxx_usb_tll_hs_sysc = { 2027 .rev_offs = 0x0000, 2028 .sysc_offs = 0x0010, 2029 .syss_offs = 0x0014, 2030 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | 2031 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | 2032 SYSC_HAS_AUTOIDLE), 2033 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 2034 .sysc_fields = &omap_hwmod_sysc_type1, 2035}; 2036 2037static struct omap_hwmod_class omap3xxx_usb_tll_hs_hwmod_class = { 2038 .name = "usb_tll_hs", 2039 .sysc = &omap3xxx_usb_tll_hs_sysc, 2040}; 2041 2042static struct omap_hwmod_irq_info omap3xxx_usb_tll_hs_irqs[] = { 2043 { .name = "tll-irq", .irq = 78 + OMAP_INTC_START, }, 2044 { .irq = -1 }, 2045}; 2046 2047static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = { 2048 .name = "usb_tll_hs", 2049 .class = &omap3xxx_usb_tll_hs_hwmod_class, 2050 .clkdm_name = "core_l4_clkdm", 2051 .mpu_irqs = omap3xxx_usb_tll_hs_irqs, 2052 .main_clk = "usbtll_fck", 2053 .prcm = { 2054 .omap2 = { 2055 .module_offs = CORE_MOD, 2056 .prcm_reg_id = 3, 2057 .module_bit = OMAP3430ES2_EN_USBTLL_SHIFT, 2058 .idlest_reg_id = 3, 2059 .idlest_idle_bit = OMAP3430ES2_ST_USBTLL_SHIFT, 2060 }, 2061 }, 2062}; 2063 2064static struct omap_hwmod omap3xxx_hdq1w_hwmod = { 2065 .name = "hdq1w", 2066 .mpu_irqs = omap2_hdq1w_mpu_irqs, 2067 .main_clk = "hdq_fck", 2068 .prcm = { 2069 .omap2 = { 2070 .module_offs = CORE_MOD, 2071 .prcm_reg_id = 1, 2072 .module_bit = OMAP3430_EN_HDQ_SHIFT, 2073 .idlest_reg_id = 1, 2074 .idlest_idle_bit = OMAP3430_ST_HDQ_SHIFT, 2075 }, 2076 }, 2077 .class = &omap2_hdq1w_class, 2078}; 2079 2080/* SAD2D */ 2081static struct omap_hwmod_rst_info omap3xxx_sad2d_resets[] = { 2082 { .name = "rst_modem_pwron_sw", .rst_shift = 0 }, 2083 { .name = "rst_modem_sw", .rst_shift = 1 }, 2084}; 2085 2086static struct omap_hwmod_class omap3xxx_sad2d_class = { 2087 .name = "sad2d", 2088}; 2089 2090static struct omap_hwmod omap3xxx_sad2d_hwmod = { 2091 .name = "sad2d", 2092 .rst_lines = omap3xxx_sad2d_resets, 2093 .rst_lines_cnt = ARRAY_SIZE(omap3xxx_sad2d_resets), 2094 .main_clk = "sad2d_ick", 2095 .prcm = { 2096 .omap2 = { 2097 .module_offs = CORE_MOD, 2098 .prcm_reg_id = 1, 2099 .module_bit = OMAP3430_EN_SAD2D_SHIFT, 2100 .idlest_reg_id = 1, 2101 .idlest_idle_bit = OMAP3430_ST_SAD2D_SHIFT, 2102 }, 2103 }, 2104 .class = &omap3xxx_sad2d_class, 2105}; 2106 2107/* 2108 * '32K sync counter' class 2109 * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock 2110 */ 2111static struct omap_hwmod_class_sysconfig omap3xxx_counter_sysc = { 2112 .rev_offs = 0x0000, 2113 .sysc_offs = 0x0004, 2114 .sysc_flags = SYSC_HAS_SIDLEMODE, 2115 .idlemodes = (SIDLE_FORCE | SIDLE_NO), 2116 .sysc_fields = &omap_hwmod_sysc_type1, 2117}; 2118 2119static struct omap_hwmod_class omap3xxx_counter_hwmod_class = { 2120 .name = "counter", 2121 .sysc = &omap3xxx_counter_sysc, 2122}; 2123 2124static struct omap_hwmod omap3xxx_counter_32k_hwmod = { 2125 .name = "counter_32k", 2126 .class = &omap3xxx_counter_hwmod_class, 2127 .clkdm_name = "wkup_clkdm", 2128 .flags = HWMOD_SWSUP_SIDLE, 2129 .main_clk = "wkup_32k_fck", 2130 .prcm = { 2131 .omap2 = { 2132 .module_offs = WKUP_MOD, 2133 .prcm_reg_id = 1, 2134 .module_bit = OMAP3430_ST_32KSYNC_SHIFT, 2135 .idlest_reg_id = 1, 2136 .idlest_idle_bit = OMAP3430_ST_32KSYNC_SHIFT, 2137 }, 2138 }, 2139}; 2140 2141/* 2142 * 'gpmc' class 2143 * general purpose memory controller 2144 */ 2145 2146static struct omap_hwmod_class_sysconfig omap3xxx_gpmc_sysc = { 2147 .rev_offs = 0x0000, 2148 .sysc_offs = 0x0010, 2149 .syss_offs = 0x0014, 2150 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE | 2151 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), 2152 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 2153 .sysc_fields = &omap_hwmod_sysc_type1, 2154}; 2155 2156static struct omap_hwmod_class omap3xxx_gpmc_hwmod_class = { 2157 .name = "gpmc", 2158 .sysc = &omap3xxx_gpmc_sysc, 2159}; 2160 2161static struct omap_hwmod_irq_info omap3xxx_gpmc_irqs[] = { 2162 { .irq = 20 + OMAP_INTC_START, }, 2163 { .irq = -1 } 2164}; 2165 2166static struct omap_hwmod omap3xxx_gpmc_hwmod = { 2167 .name = "gpmc", 2168 .class = &omap3xxx_gpmc_hwmod_class, 2169 .clkdm_name = "core_l3_clkdm", 2170 .mpu_irqs = omap3xxx_gpmc_irqs, 2171 .main_clk = "gpmc_fck", 2172 /* 2173 * XXX HWMOD_INIT_NO_RESET should not be needed for this IP 2174 * block. It is not being added due to any known bugs with 2175 * resetting the GPMC IP block, but rather because any timings 2176 * set by the bootloader are not being correctly programmed by 2177 * the kernel from the board file or DT data. 2178 * HWMOD_INIT_NO_RESET should be removed ASAP. 2179 */ 2180 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET | 2181 HWMOD_NO_IDLEST), 2182}; 2183 2184/* 2185 * interfaces 2186 */ 2187 2188/* L3 -> L4_CORE interface */ 2189static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = { 2190 .master = &omap3xxx_l3_main_hwmod, 2191 .slave = &omap3xxx_l4_core_hwmod, 2192 .user = OCP_USER_MPU | OCP_USER_SDMA, 2193}; 2194 2195/* L3 -> L4_PER interface */ 2196static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = { 2197 .master = &omap3xxx_l3_main_hwmod, 2198 .slave = &omap3xxx_l4_per_hwmod, 2199 .user = OCP_USER_MPU | OCP_USER_SDMA, 2200}; 2201 2202static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = { 2203 { 2204 .pa_start = 0x68000000, 2205 .pa_end = 0x6800ffff, 2206 .flags = ADDR_TYPE_RT, 2207 }, 2208 { } 2209}; 2210 2211/* MPU -> L3 interface */ 2212static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = { 2213 .master = &omap3xxx_mpu_hwmod, 2214 .slave = &omap3xxx_l3_main_hwmod, 2215 .addr = omap3xxx_l3_main_addrs, 2216 .user = OCP_USER_MPU, 2217}; 2218 2219static struct omap_hwmod_addr_space omap3xxx_l4_emu_addrs[] = { 2220 { 2221 .pa_start = 0x54000000, 2222 .pa_end = 0x547fffff, 2223 .flags = ADDR_TYPE_RT, 2224 }, 2225 { } 2226}; 2227 2228/* l3 -> debugss */ 2229static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_debugss = { 2230 .master = &omap3xxx_l3_main_hwmod, 2231 .slave = &omap3xxx_debugss_hwmod, 2232 .addr = omap3xxx_l4_emu_addrs, 2233 .user = OCP_USER_MPU, 2234}; 2235 2236/* DSS -> l3 */ 2237static struct omap_hwmod_ocp_if omap3430es1_dss__l3 = { 2238 .master = &omap3430es1_dss_core_hwmod, 2239 .slave = &omap3xxx_l3_main_hwmod, 2240 .user = OCP_USER_MPU | OCP_USER_SDMA, 2241}; 2242 2243static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = { 2244 .master = &omap3xxx_dss_core_hwmod, 2245 .slave = &omap3xxx_l3_main_hwmod, 2246 .fw = { 2247 .omap2 = { 2248 .l3_perm_bit = OMAP3_L3_CORE_FW_INIT_ID_DSS, 2249 .flags = OMAP_FIREWALL_L3, 2250 } 2251 }, 2252 .user = OCP_USER_MPU | OCP_USER_SDMA, 2253}; 2254 2255/* l3_core -> usbhsotg interface */ 2256static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = { 2257 .master = &omap3xxx_usbhsotg_hwmod, 2258 .slave = &omap3xxx_l3_main_hwmod, 2259 .clk = "core_l3_ick", 2260 .user = OCP_USER_MPU, 2261}; 2262 2263/* l3_core -> am35xx_usbhsotg interface */ 2264static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = { 2265 .master = &am35xx_usbhsotg_hwmod, 2266 .slave = &omap3xxx_l3_main_hwmod, 2267 .clk = "hsotgusb_ick", 2268 .user = OCP_USER_MPU, 2269}; 2270 2271/* l3_core -> sad2d interface */ 2272static struct omap_hwmod_ocp_if omap3xxx_sad2d__l3 = { 2273 .master = &omap3xxx_sad2d_hwmod, 2274 .slave = &omap3xxx_l3_main_hwmod, 2275 .clk = "core_l3_ick", 2276 .user = OCP_USER_MPU, 2277}; 2278 2279/* L4_CORE -> L4_WKUP interface */ 2280static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = { 2281 .master = &omap3xxx_l4_core_hwmod, 2282 .slave = &omap3xxx_l4_wkup_hwmod, 2283 .user = OCP_USER_MPU | OCP_USER_SDMA, 2284}; 2285 2286/* L4 CORE -> MMC1 interface */ 2287static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc1 = { 2288 .master = &omap3xxx_l4_core_hwmod, 2289 .slave = &omap3xxx_pre_es3_mmc1_hwmod, 2290 .clk = "mmchs1_ick", 2291 .addr = omap2430_mmc1_addr_space, 2292 .user = OCP_USER_MPU | OCP_USER_SDMA, 2293 .flags = OMAP_FIREWALL_L4 2294}; 2295 2296static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc1 = { 2297 .master = &omap3xxx_l4_core_hwmod, 2298 .slave = &omap3xxx_es3plus_mmc1_hwmod, 2299 .clk = "mmchs1_ick", 2300 .addr = omap2430_mmc1_addr_space, 2301 .user = OCP_USER_MPU | OCP_USER_SDMA, 2302 .flags = OMAP_FIREWALL_L4 2303}; 2304 2305/* L4 CORE -> MMC2 interface */ 2306static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc2 = { 2307 .master = &omap3xxx_l4_core_hwmod, 2308 .slave = &omap3xxx_pre_es3_mmc2_hwmod, 2309 .clk = "mmchs2_ick", 2310 .addr = omap2430_mmc2_addr_space, 2311 .user = OCP_USER_MPU | OCP_USER_SDMA, 2312 .flags = OMAP_FIREWALL_L4 2313}; 2314 2315static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc2 = { 2316 .master = &omap3xxx_l4_core_hwmod, 2317 .slave = &omap3xxx_es3plus_mmc2_hwmod, 2318 .clk = "mmchs2_ick", 2319 .addr = omap2430_mmc2_addr_space, 2320 .user = OCP_USER_MPU | OCP_USER_SDMA, 2321 .flags = OMAP_FIREWALL_L4 2322}; 2323 2324/* L4 CORE -> MMC3 interface */ 2325static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = { 2326 { 2327 .pa_start = 0x480ad000, 2328 .pa_end = 0x480ad1ff, 2329 .flags = ADDR_TYPE_RT, 2330 }, 2331 { } 2332}; 2333 2334static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = { 2335 .master = &omap3xxx_l4_core_hwmod, 2336 .slave = &omap3xxx_mmc3_hwmod, 2337 .clk = "mmchs3_ick", 2338 .addr = omap3xxx_mmc3_addr_space, 2339 .user = OCP_USER_MPU | OCP_USER_SDMA, 2340 .flags = OMAP_FIREWALL_L4 2341}; 2342 2343/* L4 CORE -> UART1 interface */ 2344static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = { 2345 { 2346 .pa_start = OMAP3_UART1_BASE, 2347 .pa_end = OMAP3_UART1_BASE + SZ_8K - 1, 2348 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, 2349 }, 2350 { } 2351}; 2352 2353static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = { 2354 .master = &omap3xxx_l4_core_hwmod, 2355 .slave = &omap3xxx_uart1_hwmod, 2356 .clk = "uart1_ick", 2357 .addr = omap3xxx_uart1_addr_space, 2358 .user = OCP_USER_MPU | OCP_USER_SDMA, 2359}; 2360 2361/* L4 CORE -> UART2 interface */ 2362static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = { 2363 { 2364 .pa_start = OMAP3_UART2_BASE, 2365 .pa_end = OMAP3_UART2_BASE + SZ_1K - 1, 2366 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, 2367 }, 2368 { } 2369}; 2370 2371static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = { 2372 .master = &omap3xxx_l4_core_hwmod, 2373 .slave = &omap3xxx_uart2_hwmod, 2374 .clk = "uart2_ick", 2375 .addr = omap3xxx_uart2_addr_space, 2376 .user = OCP_USER_MPU | OCP_USER_SDMA, 2377}; 2378 2379/* L4 PER -> UART3 interface */ 2380static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = { 2381 { 2382 .pa_start = OMAP3_UART3_BASE, 2383 .pa_end = OMAP3_UART3_BASE + SZ_1K - 1, 2384 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, 2385 }, 2386 { } 2387}; 2388 2389static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = { 2390 .master = &omap3xxx_l4_per_hwmod, 2391 .slave = &omap3xxx_uart3_hwmod, 2392 .clk = "uart3_ick", 2393 .addr = omap3xxx_uart3_addr_space, 2394 .user = OCP_USER_MPU | OCP_USER_SDMA, 2395}; 2396 2397/* L4 PER -> UART4 interface */ 2398static struct omap_hwmod_addr_space omap36xx_uart4_addr_space[] = { 2399 { 2400 .pa_start = OMAP3_UART4_BASE, 2401 .pa_end = OMAP3_UART4_BASE + SZ_1K - 1, 2402 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, 2403 }, 2404 { } 2405}; 2406 2407static struct omap_hwmod_ocp_if omap36xx_l4_per__uart4 = { 2408 .master = &omap3xxx_l4_per_hwmod, 2409 .slave = &omap36xx_uart4_hwmod, 2410 .clk = "uart4_ick", 2411 .addr = omap36xx_uart4_addr_space, 2412 .user = OCP_USER_MPU | OCP_USER_SDMA, 2413}; 2414 2415/* AM35xx: L4 CORE -> UART4 interface */ 2416static struct omap_hwmod_addr_space am35xx_uart4_addr_space[] = { 2417 { 2418 .pa_start = OMAP3_UART4_AM35XX_BASE, 2419 .pa_end = OMAP3_UART4_AM35XX_BASE + SZ_1K - 1, 2420 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, 2421 }, 2422 { } 2423}; 2424 2425static struct omap_hwmod_ocp_if am35xx_l4_core__uart4 = { 2426 .master = &omap3xxx_l4_core_hwmod, 2427 .slave = &am35xx_uart4_hwmod, 2428 .clk = "uart4_ick", 2429 .addr = am35xx_uart4_addr_space, 2430 .user = OCP_USER_MPU | OCP_USER_SDMA, 2431}; 2432 2433/* L4 CORE -> I2C1 interface */ 2434static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = { 2435 .master = &omap3xxx_l4_core_hwmod, 2436 .slave = &omap3xxx_i2c1_hwmod, 2437 .clk = "i2c1_ick", 2438 .addr = omap2_i2c1_addr_space, 2439 .fw = { 2440 .omap2 = { 2441 .l4_fw_region = OMAP3_L4_CORE_FW_I2C1_REGION, 2442 .l4_prot_group = 7, 2443 .flags = OMAP_FIREWALL_L4, 2444 } 2445 }, 2446 .user = OCP_USER_MPU | OCP_USER_SDMA, 2447}; 2448 2449/* L4 CORE -> I2C2 interface */ 2450static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = { 2451 .master = &omap3xxx_l4_core_hwmod, 2452 .slave = &omap3xxx_i2c2_hwmod, 2453 .clk = "i2c2_ick", 2454 .addr = omap2_i2c2_addr_space, 2455 .fw = { 2456 .omap2 = { 2457 .l4_fw_region = OMAP3_L4_CORE_FW_I2C2_REGION, 2458 .l4_prot_group = 7, 2459 .flags = OMAP_FIREWALL_L4, 2460 } 2461 }, 2462 .user = OCP_USER_MPU | OCP_USER_SDMA, 2463}; 2464 2465/* L4 CORE -> I2C3 interface */ 2466static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = { 2467 { 2468 .pa_start = 0x48060000, 2469 .pa_end = 0x48060000 + SZ_128 - 1, 2470 .flags = ADDR_TYPE_RT, 2471 }, 2472 { } 2473}; 2474 2475static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = { 2476 .master = &omap3xxx_l4_core_hwmod, 2477 .slave = &omap3xxx_i2c3_hwmod, 2478 .clk = "i2c3_ick", 2479 .addr = omap3xxx_i2c3_addr_space, 2480 .fw = { 2481 .omap2 = { 2482 .l4_fw_region = OMAP3_L4_CORE_FW_I2C3_REGION, 2483 .l4_prot_group = 7, 2484 .flags = OMAP_FIREWALL_L4, 2485 } 2486 }, 2487 .user = OCP_USER_MPU | OCP_USER_SDMA, 2488}; 2489 2490/* L4 CORE -> SR1 interface */ 2491static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = { 2492 { 2493 .pa_start = OMAP34XX_SR1_BASE, 2494 .pa_end = OMAP34XX_SR1_BASE + SZ_1K - 1, 2495 .flags = ADDR_TYPE_RT, 2496 }, 2497 { } 2498}; 2499 2500static struct omap_hwmod_ocp_if omap34xx_l4_core__sr1 = { 2501 .master = &omap3xxx_l4_core_hwmod, 2502 .slave = &omap34xx_sr1_hwmod, 2503 .clk = "sr_l4_ick", 2504 .addr = omap3_sr1_addr_space, 2505 .user = OCP_USER_MPU, 2506}; 2507 2508static struct omap_hwmod_ocp_if omap36xx_l4_core__sr1 = { 2509 .master = &omap3xxx_l4_core_hwmod, 2510 .slave = &omap36xx_sr1_hwmod, 2511 .clk = "sr_l4_ick", 2512 .addr = omap3_sr1_addr_space, 2513 .user = OCP_USER_MPU, 2514}; 2515 2516/* L4 CORE -> SR1 interface */ 2517static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = { 2518 { 2519 .pa_start = OMAP34XX_SR2_BASE, 2520 .pa_end = OMAP34XX_SR2_BASE + SZ_1K - 1, 2521 .flags = ADDR_TYPE_RT, 2522 }, 2523 { } 2524}; 2525 2526static struct omap_hwmod_ocp_if omap34xx_l4_core__sr2 = { 2527 .master = &omap3xxx_l4_core_hwmod, 2528 .slave = &omap34xx_sr2_hwmod, 2529 .clk = "sr_l4_ick", 2530 .addr = omap3_sr2_addr_space, 2531 .user = OCP_USER_MPU, 2532}; 2533 2534static struct omap_hwmod_ocp_if omap36xx_l4_core__sr2 = { 2535 .master = &omap3xxx_l4_core_hwmod, 2536 .slave = &omap36xx_sr2_hwmod, 2537 .clk = "sr_l4_ick", 2538 .addr = omap3_sr2_addr_space, 2539 .user = OCP_USER_MPU, 2540}; 2541 2542static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = { 2543 { 2544 .pa_start = OMAP34XX_HSUSB_OTG_BASE, 2545 .pa_end = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1, 2546 .flags = ADDR_TYPE_RT 2547 }, 2548 { } 2549}; 2550 2551/* l4_core -> usbhsotg */ 2552static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = { 2553 .master = &omap3xxx_l4_core_hwmod, 2554 .slave = &omap3xxx_usbhsotg_hwmod, 2555 .clk = "l4_ick", 2556 .addr = omap3xxx_usbhsotg_addrs, 2557 .user = OCP_USER_MPU, 2558}; 2559 2560static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = { 2561 { 2562 .pa_start = AM35XX_IPSS_USBOTGSS_BASE, 2563 .pa_end = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1, 2564 .flags = ADDR_TYPE_RT 2565 }, 2566 { } 2567}; 2568 2569/* l4_core -> usbhsotg */ 2570static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = { 2571 .master = &omap3xxx_l4_core_hwmod, 2572 .slave = &am35xx_usbhsotg_hwmod, 2573 .clk = "hsotgusb_ick", 2574 .addr = am35xx_usbhsotg_addrs, 2575 .user = OCP_USER_MPU, 2576}; 2577 2578/* L4_WKUP -> L4_SEC interface */ 2579static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__l4_sec = { 2580 .master = &omap3xxx_l4_wkup_hwmod, 2581 .slave = &omap3xxx_l4_sec_hwmod, 2582 .user = OCP_USER_MPU | OCP_USER_SDMA, 2583}; 2584 2585/* IVA2 <- L3 interface */ 2586static struct omap_hwmod_ocp_if omap3xxx_l3__iva = { 2587 .master = &omap3xxx_l3_main_hwmod, 2588 .slave = &omap3xxx_iva_hwmod, 2589 .clk = "core_l3_ick", 2590 .user = OCP_USER_MPU | OCP_USER_SDMA, 2591}; 2592 2593static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = { 2594 { 2595 .pa_start = 0x48318000, 2596 .pa_end = 0x48318000 + SZ_1K - 1, 2597 .flags = ADDR_TYPE_RT 2598 }, 2599 { } 2600}; 2601 2602/* l4_wkup -> timer1 */ 2603static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = { 2604 .master = &omap3xxx_l4_wkup_hwmod, 2605 .slave = &omap3xxx_timer1_hwmod, 2606 .clk = "gpt1_ick", 2607 .addr = omap3xxx_timer1_addrs, 2608 .user = OCP_USER_MPU | OCP_USER_SDMA, 2609}; 2610 2611static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = { 2612 { 2613 .pa_start = 0x49032000, 2614 .pa_end = 0x49032000 + SZ_1K - 1, 2615 .flags = ADDR_TYPE_RT 2616 }, 2617 { } 2618}; 2619 2620/* l4_per -> timer2 */ 2621static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = { 2622 .master = &omap3xxx_l4_per_hwmod, 2623 .slave = &omap3xxx_timer2_hwmod, 2624 .clk = "gpt2_ick", 2625 .addr = omap3xxx_timer2_addrs, 2626 .user = OCP_USER_MPU | OCP_USER_SDMA, 2627}; 2628 2629static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = { 2630 { 2631 .pa_start = 0x49034000, 2632 .pa_end = 0x49034000 + SZ_1K - 1, 2633 .flags = ADDR_TYPE_RT 2634 }, 2635 { } 2636}; 2637 2638/* l4_per -> timer3 */ 2639static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = { 2640 .master = &omap3xxx_l4_per_hwmod, 2641 .slave = &omap3xxx_timer3_hwmod, 2642 .clk = "gpt3_ick", 2643 .addr = omap3xxx_timer3_addrs, 2644 .user = OCP_USER_MPU | OCP_USER_SDMA, 2645}; 2646 2647static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = { 2648 { 2649 .pa_start = 0x49036000, 2650 .pa_end = 0x49036000 + SZ_1K - 1, 2651 .flags = ADDR_TYPE_RT 2652 }, 2653 { } 2654}; 2655 2656/* l4_per -> timer4 */ 2657static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = { 2658 .master = &omap3xxx_l4_per_hwmod, 2659 .slave = &omap3xxx_timer4_hwmod, 2660 .clk = "gpt4_ick", 2661 .addr = omap3xxx_timer4_addrs, 2662 .user = OCP_USER_MPU | OCP_USER_SDMA, 2663}; 2664 2665static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = { 2666 { 2667 .pa_start = 0x49038000, 2668 .pa_end = 0x49038000 + SZ_1K - 1, 2669 .flags = ADDR_TYPE_RT 2670 }, 2671 { } 2672}; 2673 2674/* l4_per -> timer5 */ 2675static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = { 2676 .master = &omap3xxx_l4_per_hwmod, 2677 .slave = &omap3xxx_timer5_hwmod, 2678 .clk = "gpt5_ick", 2679 .addr = omap3xxx_timer5_addrs, 2680 .user = OCP_USER_MPU | OCP_USER_SDMA, 2681}; 2682 2683static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = { 2684 { 2685 .pa_start = 0x4903A000, 2686 .pa_end = 0x4903A000 + SZ_1K - 1, 2687 .flags = ADDR_TYPE_RT 2688 }, 2689 { } 2690}; 2691 2692/* l4_per -> timer6 */ 2693static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = { 2694 .master = &omap3xxx_l4_per_hwmod, 2695 .slave = &omap3xxx_timer6_hwmod, 2696 .clk = "gpt6_ick", 2697 .addr = omap3xxx_timer6_addrs, 2698 .user = OCP_USER_MPU | OCP_USER_SDMA, 2699}; 2700 2701static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = { 2702 { 2703 .pa_start = 0x4903C000, 2704 .pa_end = 0x4903C000 + SZ_1K - 1, 2705 .flags = ADDR_TYPE_RT 2706 }, 2707 { } 2708}; 2709 2710/* l4_per -> timer7 */ 2711static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = { 2712 .master = &omap3xxx_l4_per_hwmod, 2713 .slave = &omap3xxx_timer7_hwmod, 2714 .clk = "gpt7_ick", 2715 .addr = omap3xxx_timer7_addrs, 2716 .user = OCP_USER_MPU | OCP_USER_SDMA, 2717}; 2718 2719static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = { 2720 { 2721 .pa_start = 0x4903E000, 2722 .pa_end = 0x4903E000 + SZ_1K - 1, 2723 .flags = ADDR_TYPE_RT 2724 }, 2725 { } 2726}; 2727 2728/* l4_per -> timer8 */ 2729static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = { 2730 .master = &omap3xxx_l4_per_hwmod, 2731 .slave = &omap3xxx_timer8_hwmod, 2732 .clk = "gpt8_ick", 2733 .addr = omap3xxx_timer8_addrs, 2734 .user = OCP_USER_MPU | OCP_USER_SDMA, 2735}; 2736 2737static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = { 2738 { 2739 .pa_start = 0x49040000, 2740 .pa_end = 0x49040000 + SZ_1K - 1, 2741 .flags = ADDR_TYPE_RT 2742 }, 2743 { } 2744}; 2745 2746/* l4_per -> timer9 */ 2747static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = { 2748 .master = &omap3xxx_l4_per_hwmod, 2749 .slave = &omap3xxx_timer9_hwmod, 2750 .clk = "gpt9_ick", 2751 .addr = omap3xxx_timer9_addrs, 2752 .user = OCP_USER_MPU | OCP_USER_SDMA, 2753}; 2754 2755/* l4_core -> timer10 */ 2756static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = { 2757 .master = &omap3xxx_l4_core_hwmod, 2758 .slave = &omap3xxx_timer10_hwmod, 2759 .clk = "gpt10_ick", 2760 .addr = omap2_timer10_addrs, 2761 .user = OCP_USER_MPU | OCP_USER_SDMA, 2762}; 2763 2764/* l4_core -> timer11 */ 2765static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = { 2766 .master = &omap3xxx_l4_core_hwmod, 2767 .slave = &omap3xxx_timer11_hwmod, 2768 .clk = "gpt11_ick", 2769 .addr = omap2_timer11_addrs, 2770 .user = OCP_USER_MPU | OCP_USER_SDMA, 2771}; 2772 2773static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = { 2774 { 2775 .pa_start = 0x48304000, 2776 .pa_end = 0x48304000 + SZ_1K - 1, 2777 .flags = ADDR_TYPE_RT 2778 }, 2779 { } 2780}; 2781 2782/* l4_core -> timer12 */ 2783static struct omap_hwmod_ocp_if omap3xxx_l4_sec__timer12 = { 2784 .master = &omap3xxx_l4_sec_hwmod, 2785 .slave = &omap3xxx_timer12_hwmod, 2786 .clk = "gpt12_ick", 2787 .addr = omap3xxx_timer12_addrs, 2788 .user = OCP_USER_MPU | OCP_USER_SDMA, 2789}; 2790 2791/* l4_wkup -> wd_timer2 */ 2792static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = { 2793 { 2794 .pa_start = 0x48314000, 2795 .pa_end = 0x4831407f, 2796 .flags = ADDR_TYPE_RT 2797 }, 2798 { } 2799}; 2800 2801static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = { 2802 .master = &omap3xxx_l4_wkup_hwmod, 2803 .slave = &omap3xxx_wd_timer2_hwmod, 2804 .clk = "wdt2_ick", 2805 .addr = omap3xxx_wd_timer2_addrs, 2806 .user = OCP_USER_MPU | OCP_USER_SDMA, 2807}; 2808 2809/* l4_core -> dss */ 2810static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = { 2811 .master = &omap3xxx_l4_core_hwmod, 2812 .slave = &omap3430es1_dss_core_hwmod, 2813 .clk = "dss_ick", 2814 .addr = omap2_dss_addrs, 2815 .fw = { 2816 .omap2 = { 2817 .l4_fw_region = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION, 2818 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, 2819 .flags = OMAP_FIREWALL_L4, 2820 } 2821 }, 2822 .user = OCP_USER_MPU | OCP_USER_SDMA, 2823}; 2824 2825static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = { 2826 .master = &omap3xxx_l4_core_hwmod, 2827 .slave = &omap3xxx_dss_core_hwmod, 2828 .clk = "dss_ick", 2829 .addr = omap2_dss_addrs, 2830 .fw = { 2831 .omap2 = { 2832 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_CORE_REGION, 2833 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, 2834 .flags = OMAP_FIREWALL_L4, 2835 } 2836 }, 2837 .user = OCP_USER_MPU | OCP_USER_SDMA, 2838}; 2839 2840/* l4_core -> dss_dispc */ 2841static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = { 2842 .master = &omap3xxx_l4_core_hwmod, 2843 .slave = &omap3xxx_dss_dispc_hwmod, 2844 .clk = "dss_ick", 2845 .addr = omap2_dss_dispc_addrs, 2846 .fw = { 2847 .omap2 = { 2848 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DISPC_REGION, 2849 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, 2850 .flags = OMAP_FIREWALL_L4, 2851 } 2852 }, 2853 .user = OCP_USER_MPU | OCP_USER_SDMA, 2854}; 2855 2856static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = { 2857 { 2858 .pa_start = 0x4804FC00, 2859 .pa_end = 0x4804FFFF, 2860 .flags = ADDR_TYPE_RT 2861 }, 2862 { } 2863}; 2864 2865/* l4_core -> dss_dsi1 */ 2866static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = { 2867 .master = &omap3xxx_l4_core_hwmod, 2868 .slave = &omap3xxx_dss_dsi1_hwmod, 2869 .clk = "dss_ick", 2870 .addr = omap3xxx_dss_dsi1_addrs, 2871 .fw = { 2872 .omap2 = { 2873 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DSI_REGION, 2874 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, 2875 .flags = OMAP_FIREWALL_L4, 2876 } 2877 }, 2878 .user = OCP_USER_MPU | OCP_USER_SDMA, 2879}; 2880 2881/* l4_core -> dss_rfbi */ 2882static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = { 2883 .master = &omap3xxx_l4_core_hwmod, 2884 .slave = &omap3xxx_dss_rfbi_hwmod, 2885 .clk = "dss_ick", 2886 .addr = omap2_dss_rfbi_addrs, 2887 .fw = { 2888 .omap2 = { 2889 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_RFBI_REGION, 2890 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP , 2891 .flags = OMAP_FIREWALL_L4, 2892 } 2893 }, 2894 .user = OCP_USER_MPU | OCP_USER_SDMA, 2895}; 2896 2897/* l4_core -> dss_venc */ 2898static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = { 2899 .master = &omap3xxx_l4_core_hwmod, 2900 .slave = &omap3xxx_dss_venc_hwmod, 2901 .clk = "dss_ick", 2902 .addr = omap2_dss_venc_addrs, 2903 .fw = { 2904 .omap2 = { 2905 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_VENC_REGION, 2906 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, 2907 .flags = OMAP_FIREWALL_L4, 2908 } 2909 }, 2910 .flags = OCPIF_SWSUP_IDLE, 2911 .user = OCP_USER_MPU | OCP_USER_SDMA, 2912}; 2913 2914/* l4_wkup -> gpio1 */ 2915static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = { 2916 { 2917 .pa_start = 0x48310000, 2918 .pa_end = 0x483101ff, 2919 .flags = ADDR_TYPE_RT 2920 }, 2921 { } 2922}; 2923 2924static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = { 2925 .master = &omap3xxx_l4_wkup_hwmod, 2926 .slave = &omap3xxx_gpio1_hwmod, 2927 .addr = omap3xxx_gpio1_addrs, 2928 .user = OCP_USER_MPU | OCP_USER_SDMA, 2929}; 2930 2931/* l4_per -> gpio2 */ 2932static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = { 2933 { 2934 .pa_start = 0x49050000, 2935 .pa_end = 0x490501ff, 2936 .flags = ADDR_TYPE_RT 2937 }, 2938 { } 2939}; 2940 2941static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = { 2942 .master = &omap3xxx_l4_per_hwmod, 2943 .slave = &omap3xxx_gpio2_hwmod, 2944 .addr = omap3xxx_gpio2_addrs, 2945 .user = OCP_USER_MPU | OCP_USER_SDMA, 2946}; 2947 2948/* l4_per -> gpio3 */ 2949static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = { 2950 { 2951 .pa_start = 0x49052000, 2952 .pa_end = 0x490521ff, 2953 .flags = ADDR_TYPE_RT 2954 }, 2955 { } 2956}; 2957 2958static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = { 2959 .master = &omap3xxx_l4_per_hwmod, 2960 .slave = &omap3xxx_gpio3_hwmod, 2961 .addr = omap3xxx_gpio3_addrs, 2962 .user = OCP_USER_MPU | OCP_USER_SDMA, 2963}; 2964 2965/* 2966 * 'mmu' class 2967 * The memory management unit performs virtual to physical address translation 2968 * for its requestors. 2969 */ 2970 2971static struct omap_hwmod_class_sysconfig mmu_sysc = { 2972 .rev_offs = 0x000, 2973 .sysc_offs = 0x010, 2974 .syss_offs = 0x014, 2975 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | 2976 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), 2977 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 2978 .sysc_fields = &omap_hwmod_sysc_type1, 2979}; 2980 2981static struct omap_hwmod_class omap3xxx_mmu_hwmod_class = { 2982 .name = "mmu", 2983 .sysc = &mmu_sysc, 2984}; 2985 2986/* mmu isp */ 2987 2988static struct omap_mmu_dev_attr mmu_isp_dev_attr = { 2989 .nr_tlb_entries = 8, 2990}; 2991 2992static struct omap_hwmod omap3xxx_mmu_isp_hwmod; 2993static struct omap_hwmod_irq_info omap3xxx_mmu_isp_irqs[] = { 2994 { .irq = 24 + OMAP_INTC_START, }, 2995 { .irq = -1 } 2996}; 2997 2998static struct omap_hwmod_addr_space omap3xxx_mmu_isp_addrs[] = { 2999 { 3000 .pa_start = 0x480bd400, 3001 .pa_end = 0x480bd47f, 3002 .flags = ADDR_TYPE_RT, 3003 }, 3004 { } 3005}; 3006 3007/* l4_core -> mmu isp */ 3008static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmu_isp = { 3009 .master = &omap3xxx_l4_core_hwmod, 3010 .slave = &omap3xxx_mmu_isp_hwmod, 3011 .addr = omap3xxx_mmu_isp_addrs, 3012 .user = OCP_USER_MPU | OCP_USER_SDMA, 3013}; 3014 3015static struct omap_hwmod omap3xxx_mmu_isp_hwmod = { 3016 .name = "mmu_isp", 3017 .class = &omap3xxx_mmu_hwmod_class, 3018 .mpu_irqs = omap3xxx_mmu_isp_irqs, 3019 .main_clk = "cam_ick", 3020 .dev_attr = &mmu_isp_dev_attr, 3021 .flags = HWMOD_NO_IDLEST, 3022}; 3023 3024/* mmu iva */ 3025 3026static struct omap_mmu_dev_attr mmu_iva_dev_attr = { 3027 .nr_tlb_entries = 32, 3028}; 3029 3030static struct omap_hwmod omap3xxx_mmu_iva_hwmod; 3031static struct omap_hwmod_irq_info omap3xxx_mmu_iva_irqs[] = { 3032 { .irq = 28 + OMAP_INTC_START, }, 3033 { .irq = -1 } 3034}; 3035 3036static struct omap_hwmod_rst_info omap3xxx_mmu_iva_resets[] = { 3037 { .name = "mmu", .rst_shift = 1, .st_shift = 9 }, 3038}; 3039 3040static struct omap_hwmod_addr_space omap3xxx_mmu_iva_addrs[] = { 3041 { 3042 .pa_start = 0x5d000000, 3043 .pa_end = 0x5d00007f, 3044 .flags = ADDR_TYPE_RT, 3045 }, 3046 { } 3047}; 3048 3049/* l3_main -> iva mmu */ 3050static struct omap_hwmod_ocp_if omap3xxx_l3_main__mmu_iva = { 3051 .master = &omap3xxx_l3_main_hwmod, 3052 .slave = &omap3xxx_mmu_iva_hwmod, 3053 .addr = omap3xxx_mmu_iva_addrs, 3054 .user = OCP_USER_MPU | OCP_USER_SDMA, 3055}; 3056 3057static struct omap_hwmod omap3xxx_mmu_iva_hwmod = { 3058 .name = "mmu_iva", 3059 .class = &omap3xxx_mmu_hwmod_class, 3060 .mpu_irqs = omap3xxx_mmu_iva_irqs, 3061 .clkdm_name = "iva2_clkdm", 3062 .rst_lines = omap3xxx_mmu_iva_resets, 3063 .rst_lines_cnt = ARRAY_SIZE(omap3xxx_mmu_iva_resets), 3064 .main_clk = "iva2_ck", 3065 .prcm = { 3066 .omap2 = { 3067 .module_offs = OMAP3430_IVA2_MOD, 3068 .module_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT, 3069 .idlest_reg_id = 1, 3070 .idlest_idle_bit = OMAP3430_ST_IVA2_SHIFT, 3071 }, 3072 }, 3073 .dev_attr = &mmu_iva_dev_attr, 3074 .flags = HWMOD_NO_IDLEST, 3075}; 3076 3077/* l4_per -> gpio4 */ 3078static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = { 3079 { 3080 .pa_start = 0x49054000, 3081 .pa_end = 0x490541ff, 3082 .flags = ADDR_TYPE_RT 3083 }, 3084 { } 3085}; 3086 3087static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = { 3088 .master = &omap3xxx_l4_per_hwmod, 3089 .slave = &omap3xxx_gpio4_hwmod, 3090 .addr = omap3xxx_gpio4_addrs, 3091 .user = OCP_USER_MPU | OCP_USER_SDMA, 3092}; 3093 3094/* l4_per -> gpio5 */ 3095static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = { 3096 { 3097 .pa_start = 0x49056000, 3098 .pa_end = 0x490561ff, 3099 .flags = ADDR_TYPE_RT 3100 }, 3101 { } 3102}; 3103 3104static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = { 3105 .master = &omap3xxx_l4_per_hwmod, 3106 .slave = &omap3xxx_gpio5_hwmod, 3107 .addr = omap3xxx_gpio5_addrs, 3108 .user = OCP_USER_MPU | OCP_USER_SDMA, 3109}; 3110 3111/* l4_per -> gpio6 */ 3112static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = { 3113 { 3114 .pa_start = 0x49058000, 3115 .pa_end = 0x490581ff, 3116 .flags = ADDR_TYPE_RT 3117 }, 3118 { } 3119}; 3120 3121static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = { 3122 .master = &omap3xxx_l4_per_hwmod, 3123 .slave = &omap3xxx_gpio6_hwmod, 3124 .addr = omap3xxx_gpio6_addrs, 3125 .user = OCP_USER_MPU | OCP_USER_SDMA, 3126}; 3127 3128/* dma_system -> L3 */ 3129static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = { 3130 .master = &omap3xxx_dma_system_hwmod, 3131 .slave = &omap3xxx_l3_main_hwmod, 3132 .clk = "core_l3_ick", 3133 .user = OCP_USER_MPU | OCP_USER_SDMA, 3134}; 3135 3136static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = { 3137 { 3138 .pa_start = 0x48056000, 3139 .pa_end = 0x48056fff, 3140 .flags = ADDR_TYPE_RT 3141 }, 3142 { } 3143}; 3144 3145/* l4_cfg -> dma_system */ 3146static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = { 3147 .master = &omap3xxx_l4_core_hwmod, 3148 .slave = &omap3xxx_dma_system_hwmod, 3149 .clk = "core_l4_ick", 3150 .addr = omap3xxx_dma_system_addrs, 3151 .user = OCP_USER_MPU | OCP_USER_SDMA, 3152}; 3153 3154static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = { 3155 { 3156 .name = "mpu", 3157 .pa_start = 0x48074000, 3158 .pa_end = 0x480740ff, 3159 .flags = ADDR_TYPE_RT 3160 }, 3161 { } 3162}; 3163 3164/* l4_core -> mcbsp1 */ 3165static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = { 3166 .master = &omap3xxx_l4_core_hwmod, 3167 .slave = &omap3xxx_mcbsp1_hwmod, 3168 .clk = "mcbsp1_ick", 3169 .addr = omap3xxx_mcbsp1_addrs, 3170 .user = OCP_USER_MPU | OCP_USER_SDMA, 3171}; 3172 3173static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = { 3174 { 3175 .name = "mpu", 3176 .pa_start = 0x49022000, 3177 .pa_end = 0x490220ff, 3178 .flags = ADDR_TYPE_RT 3179 }, 3180 { } 3181}; 3182 3183/* l4_per -> mcbsp2 */ 3184static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = { 3185 .master = &omap3xxx_l4_per_hwmod, 3186 .slave = &omap3xxx_mcbsp2_hwmod, 3187 .clk = "mcbsp2_ick", 3188 .addr = omap3xxx_mcbsp2_addrs, 3189 .user = OCP_USER_MPU | OCP_USER_SDMA, 3190}; 3191 3192static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = { 3193 { 3194 .name = "mpu", 3195 .pa_start = 0x49024000, 3196 .pa_end = 0x490240ff, 3197 .flags = ADDR_TYPE_RT 3198 }, 3199 { } 3200}; 3201 3202/* l4_per -> mcbsp3 */ 3203static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = { 3204 .master = &omap3xxx_l4_per_hwmod, 3205 .slave = &omap3xxx_mcbsp3_hwmod, 3206 .clk = "mcbsp3_ick", 3207 .addr = omap3xxx_mcbsp3_addrs, 3208 .user = OCP_USER_MPU | OCP_USER_SDMA, 3209}; 3210 3211static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = { 3212 { 3213 .name = "mpu", 3214 .pa_start = 0x49026000, 3215 .pa_end = 0x490260ff, 3216 .flags = ADDR_TYPE_RT 3217 }, 3218 { } 3219}; 3220 3221/* l4_per -> mcbsp4 */ 3222static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = { 3223 .master = &omap3xxx_l4_per_hwmod, 3224 .slave = &omap3xxx_mcbsp4_hwmod, 3225 .clk = "mcbsp4_ick", 3226 .addr = omap3xxx_mcbsp4_addrs, 3227 .user = OCP_USER_MPU | OCP_USER_SDMA, 3228}; 3229 3230static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = { 3231 { 3232 .name = "mpu", 3233 .pa_start = 0x48096000, 3234 .pa_end = 0x480960ff, 3235 .flags = ADDR_TYPE_RT 3236 }, 3237 { } 3238}; 3239 3240/* l4_core -> mcbsp5 */ 3241static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = { 3242 .master = &omap3xxx_l4_core_hwmod, 3243 .slave = &omap3xxx_mcbsp5_hwmod, 3244 .clk = "mcbsp5_ick", 3245 .addr = omap3xxx_mcbsp5_addrs, 3246 .user = OCP_USER_MPU | OCP_USER_SDMA, 3247}; 3248 3249static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = { 3250 { 3251 .name = "sidetone", 3252 .pa_start = 0x49028000, 3253 .pa_end = 0x490280ff, 3254 .flags = ADDR_TYPE_RT 3255 }, 3256 { } 3257}; 3258 3259/* l4_per -> mcbsp2_sidetone */ 3260static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = { 3261 .master = &omap3xxx_l4_per_hwmod, 3262 .slave = &omap3xxx_mcbsp2_sidetone_hwmod, 3263 .clk = "mcbsp2_ick", 3264 .addr = omap3xxx_mcbsp2_sidetone_addrs, 3265 .user = OCP_USER_MPU, 3266}; 3267 3268static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = { 3269 { 3270 .name = "sidetone", 3271 .pa_start = 0x4902A000, 3272 .pa_end = 0x4902A0ff, 3273 .flags = ADDR_TYPE_RT 3274 }, 3275 { } 3276}; 3277 3278/* l4_per -> mcbsp3_sidetone */ 3279static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = { 3280 .master = &omap3xxx_l4_per_hwmod, 3281 .slave = &omap3xxx_mcbsp3_sidetone_hwmod, 3282 .clk = "mcbsp3_ick", 3283 .addr = omap3xxx_mcbsp3_sidetone_addrs, 3284 .user = OCP_USER_MPU, 3285}; 3286 3287static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = { 3288 { 3289 .pa_start = 0x48094000, 3290 .pa_end = 0x480941ff, 3291 .flags = ADDR_TYPE_RT, 3292 }, 3293 { } 3294}; 3295 3296/* l4_core -> mailbox */ 3297static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = { 3298 .master = &omap3xxx_l4_core_hwmod, 3299 .slave = &omap3xxx_mailbox_hwmod, 3300 .addr = omap3xxx_mailbox_addrs, 3301 .user = OCP_USER_MPU | OCP_USER_SDMA, 3302}; 3303 3304/* l4 core -> mcspi1 interface */ 3305static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = { 3306 .master = &omap3xxx_l4_core_hwmod, 3307 .slave = &omap34xx_mcspi1, 3308 .clk = "mcspi1_ick", 3309 .addr = omap2_mcspi1_addr_space, 3310 .user = OCP_USER_MPU | OCP_USER_SDMA, 3311}; 3312 3313/* l4 core -> mcspi2 interface */ 3314static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = { 3315 .master = &omap3xxx_l4_core_hwmod, 3316 .slave = &omap34xx_mcspi2, 3317 .clk = "mcspi2_ick", 3318 .addr = omap2_mcspi2_addr_space, 3319 .user = OCP_USER_MPU | OCP_USER_SDMA, 3320}; 3321 3322/* l4 core -> mcspi3 interface */ 3323static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = { 3324 .master = &omap3xxx_l4_core_hwmod, 3325 .slave = &omap34xx_mcspi3, 3326 .clk = "mcspi3_ick", 3327 .addr = omap2430_mcspi3_addr_space, 3328 .user = OCP_USER_MPU | OCP_USER_SDMA, 3329}; 3330 3331/* l4 core -> mcspi4 interface */ 3332static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = { 3333 { 3334 .pa_start = 0x480ba000, 3335 .pa_end = 0x480ba0ff, 3336 .flags = ADDR_TYPE_RT, 3337 }, 3338 { } 3339}; 3340 3341static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = { 3342 .master = &omap3xxx_l4_core_hwmod, 3343 .slave = &omap34xx_mcspi4, 3344 .clk = "mcspi4_ick", 3345 .addr = omap34xx_mcspi4_addr_space, 3346 .user = OCP_USER_MPU | OCP_USER_SDMA, 3347}; 3348 3349static struct omap_hwmod_ocp_if omap3xxx_usb_host_hs__l3_main_2 = { 3350 .master = &omap3xxx_usb_host_hs_hwmod, 3351 .slave = &omap3xxx_l3_main_hwmod, 3352 .clk = "core_l3_ick", 3353 .user = OCP_USER_MPU, 3354}; 3355 3356static struct omap_hwmod_addr_space omap3xxx_usb_host_hs_addrs[] = { 3357 { 3358 .name = "uhh", 3359 .pa_start = 0x48064000, 3360 .pa_end = 0x480643ff, 3361 .flags = ADDR_TYPE_RT 3362 }, 3363 { 3364 .name = "ohci", 3365 .pa_start = 0x48064400, 3366 .pa_end = 0x480647ff, 3367 }, 3368 { 3369 .name = "ehci", 3370 .pa_start = 0x48064800, 3371 .pa_end = 0x48064cff, 3372 }, 3373 {} 3374}; 3375 3376static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_host_hs = { 3377 .master = &omap3xxx_l4_core_hwmod, 3378 .slave = &omap3xxx_usb_host_hs_hwmod, 3379 .clk = "usbhost_ick", 3380 .addr = omap3xxx_usb_host_hs_addrs, 3381 .user = OCP_USER_MPU | OCP_USER_SDMA, 3382}; 3383 3384static struct omap_hwmod_addr_space omap3xxx_usb_tll_hs_addrs[] = { 3385 { 3386 .name = "tll", 3387 .pa_start = 0x48062000, 3388 .pa_end = 0x48062fff, 3389 .flags = ADDR_TYPE_RT 3390 }, 3391 {} 3392}; 3393 3394static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_tll_hs = { 3395 .master = &omap3xxx_l4_core_hwmod, 3396 .slave = &omap3xxx_usb_tll_hs_hwmod, 3397 .clk = "usbtll_ick", 3398 .addr = omap3xxx_usb_tll_hs_addrs, 3399 .user = OCP_USER_MPU | OCP_USER_SDMA, 3400}; 3401 3402/* l4_core -> hdq1w interface */ 3403static struct omap_hwmod_ocp_if omap3xxx_l4_core__hdq1w = { 3404 .master = &omap3xxx_l4_core_hwmod, 3405 .slave = &omap3xxx_hdq1w_hwmod, 3406 .clk = "hdq_ick", 3407 .addr = omap2_hdq1w_addr_space, 3408 .user = OCP_USER_MPU | OCP_USER_SDMA, 3409 .flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE, 3410}; 3411 3412/* l4_wkup -> 32ksync_counter */ 3413static struct omap_hwmod_addr_space omap3xxx_counter_32k_addrs[] = { 3414 { 3415 .pa_start = 0x48320000, 3416 .pa_end = 0x4832001f, 3417 .flags = ADDR_TYPE_RT 3418 }, 3419 { } 3420}; 3421 3422static struct omap_hwmod_addr_space omap3xxx_gpmc_addrs[] = { 3423 { 3424 .pa_start = 0x6e000000, 3425 .pa_end = 0x6e000fff, 3426 .flags = ADDR_TYPE_RT 3427 }, 3428 { } 3429}; 3430 3431static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__counter_32k = { 3432 .master = &omap3xxx_l4_wkup_hwmod, 3433 .slave = &omap3xxx_counter_32k_hwmod, 3434 .clk = "omap_32ksync_ick", 3435 .addr = omap3xxx_counter_32k_addrs, 3436 .user = OCP_USER_MPU | OCP_USER_SDMA, 3437}; 3438 3439/* am35xx has Davinci MDIO & EMAC */ 3440static struct omap_hwmod_class am35xx_mdio_class = { 3441 .name = "davinci_mdio", 3442}; 3443 3444static struct omap_hwmod am35xx_mdio_hwmod = { 3445 .name = "davinci_mdio", 3446 .class = &am35xx_mdio_class, 3447 .flags = HWMOD_NO_IDLEST, 3448}; 3449 3450/* 3451 * XXX Should be connected to an IPSS hwmod, not the L3 directly; 3452 * but this will probably require some additional hwmod core support, 3453 * so is left as a future to-do item. 3454 */ 3455static struct omap_hwmod_ocp_if am35xx_mdio__l3 = { 3456 .master = &am35xx_mdio_hwmod, 3457 .slave = &omap3xxx_l3_main_hwmod, 3458 .clk = "emac_fck", 3459 .user = OCP_USER_MPU, 3460}; 3461 3462/* l4_core -> davinci mdio */ 3463/* 3464 * XXX Should be connected to an IPSS hwmod, not the L4_CORE directly; 3465 * but this will probably require some additional hwmod core support, 3466 * so is left as a future to-do item. 3467 */ 3468static struct omap_hwmod_ocp_if am35xx_l4_core__mdio = { 3469 .master = &omap3xxx_l4_core_hwmod, 3470 .slave = &am35xx_mdio_hwmod, 3471 .clk = "emac_fck", 3472 .user = OCP_USER_MPU, 3473}; 3474 3475static struct omap_hwmod_class am35xx_emac_class = { 3476 .name = "davinci_emac", 3477}; 3478 3479static struct omap_hwmod am35xx_emac_hwmod = { 3480 .name = "davinci_emac", 3481 .class = &am35xx_emac_class, 3482 /* 3483 * According to Mark Greer, the MPU will not return from WFI 3484 * when the EMAC signals an interrupt. 3485 * http://www.spinics.net/lists/arm-kernel/msg174734.html 3486 */ 3487 .flags = (HWMOD_NO_IDLEST | HWMOD_BLOCK_WFI), 3488}; 3489 3490/* l3_core -> davinci emac interface */ 3491/* 3492 * XXX Should be connected to an IPSS hwmod, not the L3 directly; 3493 * but this will probably require some additional hwmod core support, 3494 * so is left as a future to-do item. 3495 */ 3496static struct omap_hwmod_ocp_if am35xx_emac__l3 = { 3497 .master = &am35xx_emac_hwmod, 3498 .slave = &omap3xxx_l3_main_hwmod, 3499 .clk = "emac_ick", 3500 .user = OCP_USER_MPU, 3501}; 3502 3503/* l4_core -> davinci emac */ 3504/* 3505 * XXX Should be connected to an IPSS hwmod, not the L4_CORE directly; 3506 * but this will probably require some additional hwmod core support, 3507 * so is left as a future to-do item. 3508 */ 3509static struct omap_hwmod_ocp_if am35xx_l4_core__emac = { 3510 .master = &omap3xxx_l4_core_hwmod, 3511 .slave = &am35xx_emac_hwmod, 3512 .clk = "emac_ick", 3513 .user = OCP_USER_MPU, 3514}; 3515 3516static struct omap_hwmod_ocp_if omap3xxx_l3_main__gpmc = { 3517 .master = &omap3xxx_l3_main_hwmod, 3518 .slave = &omap3xxx_gpmc_hwmod, 3519 .clk = "core_l3_ick", 3520 .addr = omap3xxx_gpmc_addrs, 3521 .user = OCP_USER_MPU | OCP_USER_SDMA, 3522}; 3523 3524/* l4_core -> SHAM2 (SHA1/MD5) (similar to omap24xx) */ 3525static struct omap_hwmod_sysc_fields omap3_sham_sysc_fields = { 3526 .sidle_shift = 4, 3527 .srst_shift = 1, 3528 .autoidle_shift = 0, 3529}; 3530 3531static struct omap_hwmod_class_sysconfig omap3_sham_sysc = { 3532 .rev_offs = 0x5c, 3533 .sysc_offs = 0x60, 3534 .syss_offs = 0x64, 3535 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | 3536 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), 3537 .sysc_fields = &omap3_sham_sysc_fields, 3538}; 3539 3540static struct omap_hwmod_class omap3xxx_sham_class = { 3541 .name = "sham", 3542 .sysc = &omap3_sham_sysc, 3543}; 3544 3545static struct omap_hwmod_irq_info omap3_sham_mpu_irqs[] = { 3546 { .irq = 49 + OMAP_INTC_START, }, 3547 { .irq = -1 } 3548}; 3549 3550static struct omap_hwmod_dma_info omap3_sham_sdma_reqs[] = { 3551 { .name = "rx", .dma_req = 69, }, 3552 { .dma_req = -1 } 3553}; 3554 3555static struct omap_hwmod omap3xxx_sham_hwmod = { 3556 .name = "sham", 3557 .mpu_irqs = omap3_sham_mpu_irqs, 3558 .sdma_reqs = omap3_sham_sdma_reqs, 3559 .main_clk = "sha12_ick", 3560 .prcm = { 3561 .omap2 = { 3562 .module_offs = CORE_MOD, 3563 .prcm_reg_id = 1, 3564 .module_bit = OMAP3430_EN_SHA12_SHIFT, 3565 .idlest_reg_id = 1, 3566 .idlest_idle_bit = OMAP3430_ST_SHA12_SHIFT, 3567 }, 3568 }, 3569 .class = &omap3xxx_sham_class, 3570}; 3571 3572static struct omap_hwmod_addr_space omap3xxx_sham_addrs[] = { 3573 { 3574 .pa_start = 0x480c3000, 3575 .pa_end = 0x480c3000 + 0x64 - 1, 3576 .flags = ADDR_TYPE_RT 3577 }, 3578 { } 3579}; 3580 3581static struct omap_hwmod_ocp_if omap3xxx_l4_core__sham = { 3582 .master = &omap3xxx_l4_core_hwmod, 3583 .slave = &omap3xxx_sham_hwmod, 3584 .clk = "sha12_ick", 3585 .addr = omap3xxx_sham_addrs, 3586 .user = OCP_USER_MPU | OCP_USER_SDMA, 3587}; 3588 3589/* l4_core -> AES */ 3590static struct omap_hwmod_sysc_fields omap3xxx_aes_sysc_fields = { 3591 .sidle_shift = 6, 3592 .srst_shift = 1, 3593 .autoidle_shift = 0, 3594}; 3595 3596static struct omap_hwmod_class_sysconfig omap3_aes_sysc = { 3597 .rev_offs = 0x44, 3598 .sysc_offs = 0x48, 3599 .syss_offs = 0x4c, 3600 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | 3601 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), 3602 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 3603 .sysc_fields = &omap3xxx_aes_sysc_fields, 3604}; 3605 3606static struct omap_hwmod_class omap3xxx_aes_class = { 3607 .name = "aes", 3608 .sysc = &omap3_aes_sysc, 3609}; 3610 3611static struct omap_hwmod_dma_info omap3_aes_sdma_reqs[] = { 3612 { .name = "tx", .dma_req = 65, }, 3613 { .name = "rx", .dma_req = 66, }, 3614 { .dma_req = -1 } 3615}; 3616 3617static struct omap_hwmod omap3xxx_aes_hwmod = { 3618 .name = "aes", 3619 .sdma_reqs = omap3_aes_sdma_reqs, 3620 .main_clk = "aes2_ick", 3621 .prcm = { 3622 .omap2 = { 3623 .module_offs = CORE_MOD, 3624 .prcm_reg_id = 1, 3625 .module_bit = OMAP3430_EN_AES2_SHIFT, 3626 .idlest_reg_id = 1, 3627 .idlest_idle_bit = OMAP3430_ST_AES2_SHIFT, 3628 }, 3629 }, 3630 .class = &omap3xxx_aes_class, 3631}; 3632 3633static struct omap_hwmod_addr_space omap3xxx_aes_addrs[] = { 3634 { 3635 .pa_start = 0x480c5000, 3636 .pa_end = 0x480c5000 + 0x50 - 1, 3637 .flags = ADDR_TYPE_RT 3638 }, 3639 { } 3640}; 3641 3642static struct omap_hwmod_ocp_if omap3xxx_l4_core__aes = { 3643 .master = &omap3xxx_l4_core_hwmod, 3644 .slave = &omap3xxx_aes_hwmod, 3645 .clk = "aes2_ick", 3646 .addr = omap3xxx_aes_addrs, 3647 .user = OCP_USER_MPU | OCP_USER_SDMA, 3648}; 3649 3650/* 3651 * 'ssi' class 3652 * synchronous serial interface (multichannel and full-duplex serial if) 3653 */ 3654 3655static struct omap_hwmod_class_sysconfig omap34xx_ssi_sysc = { 3656 .rev_offs = 0x0000, 3657 .sysc_offs = 0x0010, 3658 .syss_offs = 0x0014, 3659 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_MIDLEMODE | 3660 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), 3661 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 3662 .sysc_fields = &omap_hwmod_sysc_type1, 3663}; 3664 3665static struct omap_hwmod_class omap34xx_ssi_hwmod_class = { 3666 .name = "ssi", 3667 .sysc = &omap34xx_ssi_sysc, 3668}; 3669 3670static struct omap_hwmod omap34xx_ssi_hwmod = { 3671 .name = "ssi", 3672 .class = &omap34xx_ssi_hwmod_class, 3673 .clkdm_name = "core_l4_clkdm", 3674 .main_clk = "ssi_ssr_fck", 3675 .prcm = { 3676 .omap2 = { 3677 .prcm_reg_id = 1, 3678 .module_bit = OMAP3430_EN_SSI_SHIFT, 3679 .module_offs = CORE_MOD, 3680 .idlest_reg_id = 1, 3681 .idlest_idle_bit = OMAP3430ES2_ST_SSI_IDLE_SHIFT, 3682 }, 3683 }, 3684}; 3685 3686/* L4 CORE -> SSI */ 3687static struct omap_hwmod_ocp_if omap34xx_l4_core__ssi = { 3688 .master = &omap3xxx_l4_core_hwmod, 3689 .slave = &omap34xx_ssi_hwmod, 3690 .clk = "ssi_ick", 3691 .user = OCP_USER_MPU | OCP_USER_SDMA, 3692}; 3693 3694static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = { 3695 &omap3xxx_l3_main__l4_core, 3696 &omap3xxx_l3_main__l4_per, 3697 &omap3xxx_mpu__l3_main, 3698 &omap3xxx_l3_main__l4_debugss, 3699 &omap3xxx_l4_core__l4_wkup, 3700 &omap3xxx_l4_core__mmc3, 3701 &omap3_l4_core__uart1, 3702 &omap3_l4_core__uart2, 3703 &omap3_l4_per__uart3, 3704 &omap3_l4_core__i2c1, 3705 &omap3_l4_core__i2c2, 3706 &omap3_l4_core__i2c3, 3707 &omap3xxx_l4_wkup__l4_sec, 3708 &omap3xxx_l4_wkup__timer1, 3709 &omap3xxx_l4_per__timer2, 3710 &omap3xxx_l4_per__timer3, 3711 &omap3xxx_l4_per__timer4, 3712 &omap3xxx_l4_per__timer5, 3713 &omap3xxx_l4_per__timer6, 3714 &omap3xxx_l4_per__timer7, 3715 &omap3xxx_l4_per__timer8, 3716 &omap3xxx_l4_per__timer9, 3717 &omap3xxx_l4_core__timer10, 3718 &omap3xxx_l4_core__timer11, 3719 &omap3xxx_l4_wkup__wd_timer2, 3720 &omap3xxx_l4_wkup__gpio1, 3721 &omap3xxx_l4_per__gpio2, 3722 &omap3xxx_l4_per__gpio3, 3723 &omap3xxx_l4_per__gpio4, 3724 &omap3xxx_l4_per__gpio5, 3725 &omap3xxx_l4_per__gpio6, 3726 &omap3xxx_dma_system__l3, 3727 &omap3xxx_l4_core__dma_system, 3728 &omap3xxx_l4_core__mcbsp1, 3729 &omap3xxx_l4_per__mcbsp2, 3730 &omap3xxx_l4_per__mcbsp3, 3731 &omap3xxx_l4_per__mcbsp4, 3732 &omap3xxx_l4_core__mcbsp5, 3733 &omap3xxx_l4_per__mcbsp2_sidetone, 3734 &omap3xxx_l4_per__mcbsp3_sidetone, 3735 &omap34xx_l4_core__mcspi1, 3736 &omap34xx_l4_core__mcspi2, 3737 &omap34xx_l4_core__mcspi3, 3738 &omap34xx_l4_core__mcspi4, 3739 &omap3xxx_l4_wkup__counter_32k, 3740 &omap3xxx_l3_main__gpmc, 3741 NULL, 3742}; 3743 3744/* GP-only hwmod links */ 3745static struct omap_hwmod_ocp_if *omap34xx_gp_hwmod_ocp_ifs[] __initdata = { 3746 &omap3xxx_l4_sec__timer12, 3747 &omap3xxx_l4_core__sham, 3748 &omap3xxx_l4_core__aes, 3749 NULL 3750}; 3751 3752static struct omap_hwmod_ocp_if *omap36xx_gp_hwmod_ocp_ifs[] __initdata = { 3753 &omap3xxx_l4_sec__timer12, 3754 &omap3xxx_l4_core__sham, 3755 &omap3xxx_l4_core__aes, 3756 NULL 3757}; 3758 3759static struct omap_hwmod_ocp_if *am35xx_gp_hwmod_ocp_ifs[] __initdata = { 3760 &omap3xxx_l4_sec__timer12, 3761 /* 3762 * Apparently the SHA/MD5 and AES accelerator IP blocks are 3763 * only present on some AM35xx chips, and no one knows which 3764 * ones. See 3765 * http://www.spinics.net/lists/arm-kernel/msg215466.html So 3766 * if you need these IP blocks on an AM35xx, try uncommenting 3767 * the following lines. 3768 */ 3769 /* &omap3xxx_l4_core__sham, */ 3770 /* &omap3xxx_l4_core__aes, */ 3771 NULL 3772}; 3773 3774/* 3430ES1-only hwmod links */ 3775static struct omap_hwmod_ocp_if *omap3430es1_hwmod_ocp_ifs[] __initdata = { 3776 &omap3430es1_dss__l3, 3777 &omap3430es1_l4_core__dss, 3778 NULL 3779}; 3780 3781/* 3430ES2+-only hwmod links */ 3782static struct omap_hwmod_ocp_if *omap3430es2plus_hwmod_ocp_ifs[] __initdata = { 3783 &omap3xxx_dss__l3, 3784 &omap3xxx_l4_core__dss, 3785 &omap3xxx_usbhsotg__l3, 3786 &omap3xxx_l4_core__usbhsotg, 3787 &omap3xxx_usb_host_hs__l3_main_2, 3788 &omap3xxx_l4_core__usb_host_hs, 3789 &omap3xxx_l4_core__usb_tll_hs, 3790 NULL 3791}; 3792 3793/* <= 3430ES3-only hwmod links */ 3794static struct omap_hwmod_ocp_if *omap3430_pre_es3_hwmod_ocp_ifs[] __initdata = { 3795 &omap3xxx_l4_core__pre_es3_mmc1, 3796 &omap3xxx_l4_core__pre_es3_mmc2, 3797 NULL 3798}; 3799 3800/* 3430ES3+-only hwmod links */ 3801static struct omap_hwmod_ocp_if *omap3430_es3plus_hwmod_ocp_ifs[] __initdata = { 3802 &omap3xxx_l4_core__es3plus_mmc1, 3803 &omap3xxx_l4_core__es3plus_mmc2, 3804 NULL 3805}; 3806 3807/* 34xx-only hwmod links (all ES revisions) */ 3808static struct omap_hwmod_ocp_if *omap34xx_hwmod_ocp_ifs[] __initdata = { 3809 &omap3xxx_l3__iva, 3810 &omap34xx_l4_core__sr1, 3811 &omap34xx_l4_core__sr2, 3812 &omap3xxx_l4_core__mailbox, 3813 &omap3xxx_l4_core__hdq1w, 3814 &omap3xxx_sad2d__l3, 3815 &omap3xxx_l4_core__mmu_isp, 3816 &omap3xxx_l3_main__mmu_iva, 3817 &omap34xx_l4_core__ssi, 3818 NULL 3819}; 3820 3821/* 36xx-only hwmod links (all ES revisions) */ 3822static struct omap_hwmod_ocp_if *omap36xx_hwmod_ocp_ifs[] __initdata = { 3823 &omap3xxx_l3__iva, 3824 &omap36xx_l4_per__uart4, 3825 &omap3xxx_dss__l3, 3826 &omap3xxx_l4_core__dss, 3827 &omap36xx_l4_core__sr1, 3828 &omap36xx_l4_core__sr2, 3829 &omap3xxx_usbhsotg__l3, 3830 &omap3xxx_l4_core__usbhsotg, 3831 &omap3xxx_l4_core__mailbox, 3832 &omap3xxx_usb_host_hs__l3_main_2, 3833 &omap3xxx_l4_core__usb_host_hs, 3834 &omap3xxx_l4_core__usb_tll_hs, 3835 &omap3xxx_l4_core__es3plus_mmc1, 3836 &omap3xxx_l4_core__es3plus_mmc2, 3837 &omap3xxx_l4_core__hdq1w, 3838 &omap3xxx_sad2d__l3, 3839 &omap3xxx_l4_core__mmu_isp, 3840 &omap3xxx_l3_main__mmu_iva, 3841 NULL 3842}; 3843 3844static struct omap_hwmod_ocp_if *am35xx_hwmod_ocp_ifs[] __initdata = { 3845 &omap3xxx_dss__l3, 3846 &omap3xxx_l4_core__dss, 3847 &am35xx_usbhsotg__l3, 3848 &am35xx_l4_core__usbhsotg, 3849 &am35xx_l4_core__uart4, 3850 &omap3xxx_usb_host_hs__l3_main_2, 3851 &omap3xxx_l4_core__usb_host_hs, 3852 &omap3xxx_l4_core__usb_tll_hs, 3853 &omap3xxx_l4_core__es3plus_mmc1, 3854 &omap3xxx_l4_core__es3plus_mmc2, 3855 &omap3xxx_l4_core__hdq1w, 3856 &am35xx_mdio__l3, 3857 &am35xx_l4_core__mdio, 3858 &am35xx_emac__l3, 3859 &am35xx_l4_core__emac, 3860 NULL 3861}; 3862 3863static struct omap_hwmod_ocp_if *omap3xxx_dss_hwmod_ocp_ifs[] __initdata = { 3864 &omap3xxx_l4_core__dss_dispc, 3865 &omap3xxx_l4_core__dss_dsi1, 3866 &omap3xxx_l4_core__dss_rfbi, 3867 &omap3xxx_l4_core__dss_venc, 3868 NULL 3869}; 3870 3871int __init omap3xxx_hwmod_init(void) 3872{ 3873 int r; 3874 struct omap_hwmod_ocp_if **h = NULL, **h_gp = NULL; 3875 unsigned int rev; 3876 3877 omap_hwmod_init(); 3878 3879 /* Register hwmod links common to all OMAP3 */ 3880 r = omap_hwmod_register_links(omap3xxx_hwmod_ocp_ifs); 3881 if (r < 0) 3882 return r; 3883 3884 rev = omap_rev(); 3885 3886 /* 3887 * Register hwmod links common to individual OMAP3 families, all 3888 * silicon revisions (e.g., 34xx, or AM3505/3517, or 36xx) 3889 * All possible revisions should be included in this conditional. 3890 */ 3891 if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 || 3892 rev == OMAP3430_REV_ES2_1 || rev == OMAP3430_REV_ES3_0 || 3893 rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) { 3894 h = omap34xx_hwmod_ocp_ifs; 3895 h_gp = omap34xx_gp_hwmod_ocp_ifs; 3896 } else if (rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1) { 3897 h = am35xx_hwmod_ocp_ifs; 3898 h_gp = am35xx_gp_hwmod_ocp_ifs; 3899 } else if (rev == OMAP3630_REV_ES1_0 || rev == OMAP3630_REV_ES1_1 || 3900 rev == OMAP3630_REV_ES1_2) { 3901 h = omap36xx_hwmod_ocp_ifs; 3902 h_gp = omap36xx_gp_hwmod_ocp_ifs; 3903 } else { 3904 WARN(1, "OMAP3 hwmod family init: unknown chip type\n"); 3905 return -EINVAL; 3906 } 3907 3908 r = omap_hwmod_register_links(h); 3909 if (r < 0) 3910 return r; 3911 3912 /* Register GP-only hwmod links. */ 3913 if (h_gp && omap_type() == OMAP2_DEVICE_TYPE_GP) { 3914 r = omap_hwmod_register_links(h_gp); 3915 if (r < 0) 3916 return r; 3917 } 3918 3919 3920 /* 3921 * Register hwmod links specific to certain ES levels of a 3922 * particular family of silicon (e.g., 34xx ES1.0) 3923 */ 3924 h = NULL; 3925 if (rev == OMAP3430_REV_ES1_0) { 3926 h = omap3430es1_hwmod_ocp_ifs; 3927 } else if (rev == OMAP3430_REV_ES2_0 || rev == OMAP3430_REV_ES2_1 || 3928 rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 || 3929 rev == OMAP3430_REV_ES3_1_2) { 3930 h = omap3430es2plus_hwmod_ocp_ifs; 3931 } 3932 3933 if (h) { 3934 r = omap_hwmod_register_links(h); 3935 if (r < 0) 3936 return r; 3937 } 3938 3939 h = NULL; 3940 if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 || 3941 rev == OMAP3430_REV_ES2_1) { 3942 h = omap3430_pre_es3_hwmod_ocp_ifs; 3943 } else if (rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 || 3944 rev == OMAP3430_REV_ES3_1_2) { 3945 h = omap3430_es3plus_hwmod_ocp_ifs; 3946 } 3947 3948 if (h) 3949 r = omap_hwmod_register_links(h); 3950 if (r < 0) 3951 return r; 3952 3953 /* 3954 * DSS code presumes that dss_core hwmod is handled first, 3955 * _before_ any other DSS related hwmods so register common 3956 * DSS hwmod links last to ensure that dss_core is already 3957 * registered. Otherwise some change things may happen, for 3958 * ex. if dispc is handled before dss_core and DSS is enabled 3959 * in bootloader DISPC will be reset with outputs enabled 3960 * which sometimes leads to unrecoverable L3 error. XXX The 3961 * long-term fix to this is to ensure hwmods are set up in 3962 * dependency order in the hwmod core code. 3963 */ 3964 r = omap_hwmod_register_links(omap3xxx_dss_hwmod_ocp_ifs); 3965 3966 return r; 3967} 3968