1/*
2 * AM43xx Clock domains framework
3 *
4 * Copyright (C) 2013 Texas Instruments, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/kernel.h>
12#include <linux/io.h>
13
14#include "clockdomain.h"
15#include "prcm44xx.h"
16#include "prcm43xx.h"
17
18static struct clockdomain l4_cefuse_43xx_clkdm = {
19	.name		  = "l4_cefuse_clkdm",
20	.pwrdm		  = { .name = "cefuse_pwrdm" },
21	.prcm_partition	  = AM43XX_CM_PARTITION,
22	.cm_inst	  = AM43XX_CM_CEFUSE_INST,
23	.clkdm_offs	  = AM43XX_CM_CEFUSE_CEFUSE_CDOFFS,
24	.flags		  = CLKDM_CAN_SWSUP,
25};
26
27static struct clockdomain mpu_43xx_clkdm = {
28	.name		  = "mpu_clkdm",
29	.pwrdm		  = { .name = "mpu_pwrdm" },
30	.prcm_partition	  = AM43XX_CM_PARTITION,
31	.cm_inst	  = AM43XX_CM_MPU_INST,
32	.clkdm_offs	  = AM43XX_CM_MPU_MPU_CDOFFS,
33	.flags		  = CLKDM_CAN_HWSUP_SWSUP,
34};
35
36static struct clockdomain l4ls_43xx_clkdm = {
37	.name		  = "l4ls_clkdm",
38	.pwrdm		  = { .name = "per_pwrdm" },
39	.prcm_partition	  = AM43XX_CM_PARTITION,
40	.cm_inst	  = AM43XX_CM_PER_INST,
41	.clkdm_offs	  = AM43XX_CM_PER_L4LS_CDOFFS,
42	.flags		  = CLKDM_CAN_SWSUP,
43};
44
45static struct clockdomain tamper_43xx_clkdm = {
46	.name		  = "tamper_clkdm",
47	.pwrdm		  = { .name = "tamper_pwrdm" },
48	.prcm_partition	  = AM43XX_CM_PARTITION,
49	.cm_inst	  = AM43XX_CM_TAMPER_INST,
50	.clkdm_offs	  = AM43XX_CM_TAMPER_TAMPER_CDOFFS,
51	.flags		  = CLKDM_CAN_SWSUP,
52};
53
54static struct clockdomain l4_rtc_43xx_clkdm = {
55	.name		  = "l4_rtc_clkdm",
56	.pwrdm		  = { .name = "rtc_pwrdm" },
57	.prcm_partition	  = AM43XX_CM_PARTITION,
58	.cm_inst	  = AM43XX_CM_RTC_INST,
59	.clkdm_offs	  = AM43XX_CM_RTC_RTC_CDOFFS,
60	.flags		  = CLKDM_CAN_SWSUP,
61};
62
63static struct clockdomain pruss_ocp_43xx_clkdm = {
64	.name		  = "pruss_ocp_clkdm",
65	.pwrdm		  = { .name = "per_pwrdm" },
66	.prcm_partition	  = AM43XX_CM_PARTITION,
67	.cm_inst	  = AM43XX_CM_PER_INST,
68	.clkdm_offs	  = AM43XX_CM_PER_ICSS_CDOFFS,
69	.flags		  = CLKDM_CAN_SWSUP,
70};
71
72static struct clockdomain ocpwp_l3_43xx_clkdm = {
73	.name		  = "ocpwp_l3_clkdm",
74	.pwrdm		  = { .name = "per_pwrdm" },
75	.prcm_partition	  = AM43XX_CM_PARTITION,
76	.cm_inst	  = AM43XX_CM_PER_INST,
77	.clkdm_offs	  = AM43XX_CM_PER_OCPWP_L3_CDOFFS,
78	.flags		  = CLKDM_CAN_SWSUP,
79};
80
81static struct clockdomain l3s_tsc_43xx_clkdm = {
82	.name		  = "l3s_tsc_clkdm",
83	.pwrdm		  = { .name = "wkup_pwrdm" },
84	.prcm_partition	  = AM43XX_CM_PARTITION,
85	.cm_inst	  = AM43XX_CM_WKUP_INST,
86	.clkdm_offs	  = AM43XX_CM_WKUP_L3S_TSC_CDOFFS,
87	.flags		  = CLKDM_CAN_SWSUP,
88};
89
90static struct clockdomain dss_43xx_clkdm = {
91	.name		  = "dss_clkdm",
92	.pwrdm		  = { .name = "per_pwrdm" },
93	.prcm_partition	  = AM43XX_CM_PARTITION,
94	.cm_inst	  = AM43XX_CM_PER_INST,
95	.clkdm_offs	  = AM43XX_CM_PER_DSS_CDOFFS,
96	.flags		  = CLKDM_CAN_SWSUP,
97};
98
99static struct clockdomain l3_aon_43xx_clkdm = {
100	.name		  = "l3_aon_clkdm",
101	.pwrdm		  = { .name = "wkup_pwrdm" },
102	.prcm_partition	  = AM43XX_CM_PARTITION,
103	.cm_inst	  = AM43XX_CM_WKUP_INST,
104	.clkdm_offs	  = AM43XX_CM_WKUP_L3_AON_CDOFFS,
105	.flags		  = CLKDM_CAN_SWSUP,
106};
107
108static struct clockdomain emif_43xx_clkdm = {
109	.name		  = "emif_clkdm",
110	.pwrdm		  = { .name = "per_pwrdm" },
111	.prcm_partition	  = AM43XX_CM_PARTITION,
112	.cm_inst	  = AM43XX_CM_PER_INST,
113	.clkdm_offs	  = AM43XX_CM_PER_EMIF_CDOFFS,
114	.flags		  = CLKDM_CAN_SWSUP,
115};
116
117static struct clockdomain l4_wkup_aon_43xx_clkdm = {
118	.name		  = "l4_wkup_aon_clkdm",
119	.pwrdm		  = { .name = "wkup_pwrdm" },
120	.prcm_partition	  = AM43XX_CM_PARTITION,
121	.cm_inst	  = AM43XX_CM_WKUP_INST,
122	.clkdm_offs	  = AM43XX_CM_WKUP_L4_WKUP_AON_CDOFFS,
123};
124
125static struct clockdomain l3_43xx_clkdm = {
126	.name		  = "l3_clkdm",
127	.pwrdm		  = { .name = "per_pwrdm" },
128	.prcm_partition	  = AM43XX_CM_PARTITION,
129	.cm_inst	  = AM43XX_CM_PER_INST,
130	.clkdm_offs	  = AM43XX_CM_PER_L3_CDOFFS,
131	.flags		  = CLKDM_CAN_SWSUP,
132};
133
134static struct clockdomain l4_wkup_43xx_clkdm = {
135	.name		  = "l4_wkup_clkdm",
136	.pwrdm		  = { .name = "wkup_pwrdm" },
137	.prcm_partition	  = AM43XX_CM_PARTITION,
138	.cm_inst	  = AM43XX_CM_WKUP_INST,
139	.clkdm_offs	  = AM43XX_CM_WKUP_WKUP_CDOFFS,
140	.flags		  = CLKDM_CAN_SWSUP,
141};
142
143static struct clockdomain cpsw_125mhz_43xx_clkdm = {
144	.name		  = "cpsw_125mhz_clkdm",
145	.pwrdm		  = { .name = "per_pwrdm" },
146	.prcm_partition	  = AM43XX_CM_PARTITION,
147	.cm_inst	  = AM43XX_CM_PER_INST,
148	.clkdm_offs	  = AM43XX_CM_PER_CPSW_CDOFFS,
149	.flags		  = CLKDM_CAN_SWSUP,
150};
151
152static struct clockdomain gfx_l3_43xx_clkdm = {
153	.name		  = "gfx_l3_clkdm",
154	.pwrdm		  = { .name = "gfx_pwrdm" },
155	.prcm_partition	  = AM43XX_CM_PARTITION,
156	.cm_inst	  = AM43XX_CM_GFX_INST,
157	.clkdm_offs	  = AM43XX_CM_GFX_GFX_L3_CDOFFS,
158	.flags		  = CLKDM_CAN_SWSUP,
159};
160
161static struct clockdomain l3s_43xx_clkdm = {
162	.name		  = "l3s_clkdm",
163	.pwrdm		  = { .name = "per_pwrdm" },
164	.prcm_partition	  = AM43XX_CM_PARTITION,
165	.cm_inst	  = AM43XX_CM_PER_INST,
166	.clkdm_offs	  = AM43XX_CM_PER_L3S_CDOFFS,
167	.flags		  = CLKDM_CAN_SWSUP,
168};
169
170static struct clockdomain *clockdomains_am43xx[] __initdata = {
171	&l4_cefuse_43xx_clkdm,
172	&mpu_43xx_clkdm,
173	&l4ls_43xx_clkdm,
174	&tamper_43xx_clkdm,
175	&l4_rtc_43xx_clkdm,
176	&pruss_ocp_43xx_clkdm,
177	&ocpwp_l3_43xx_clkdm,
178	&l3s_tsc_43xx_clkdm,
179	&dss_43xx_clkdm,
180	&l3_aon_43xx_clkdm,
181	&emif_43xx_clkdm,
182	&l4_wkup_aon_43xx_clkdm,
183	&l3_43xx_clkdm,
184	&l4_wkup_43xx_clkdm,
185	&cpsw_125mhz_43xx_clkdm,
186	&gfx_l3_43xx_clkdm,
187	&l3s_43xx_clkdm,
188	NULL
189};
190
191void __init am43xx_clockdomains_init(void)
192{
193	clkdm_register_platform_funcs(&am43xx_clkdm_operations);
194	clkdm_register_clkdms(clockdomains_am43xx);
195	clkdm_complete_init();
196}
197