1 /*
2 * OMAP3-specific clock framework functions
3 *
4 * Copyright (C) 2007-2008 Texas Instruments, Inc.
5 * Copyright (C) 2007-2010 Nokia Corporation
6 *
7 * Paul Walmsley
8 * Jouni Högander
9 *
10 * Parts of this code are based on code written by
11 * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 */
17 #undef DEBUG
18
19 #include <linux/kernel.h>
20 #include <linux/errno.h>
21 #include <linux/clk.h>
22 #include <linux/io.h>
23
24 #include "soc.h"
25 #include "clock.h"
26 #include "clock3xxx.h"
27 #include "prm2xxx_3xxx.h"
28 #include "prm-regbits-34xx.h"
29 #include "cm2xxx_3xxx.h"
30 #include "cm-regbits-34xx.h"
31
32 /*
33 * DPLL5_FREQ_FOR_USBHOST: USBHOST and USBTLL are the only clocks
34 * that are sourced by DPLL5, and both of these require this clock
35 * to be at 120 MHz for proper operation.
36 */
37 #define DPLL5_FREQ_FOR_USBHOST 120000000
38
39 /* needed by omap3_core_dpll_m2_set_rate() */
40 struct clk *sdrc_ick_p, *arm_fck_p;
41
42 /**
43 * omap3_dpll4_set_rate - set rate for omap3 per-dpll
44 * @hw: clock to change
45 * @rate: target rate for clock
46 * @parent_rate: rate of the parent clock
47 *
48 * Check if the current SoC supports the per-dpll reprogram operation
49 * or not, and then do the rate change if supported. Returns -EINVAL
50 * if not supported, 0 for success, and potential error codes from the
51 * clock rate change.
52 */
omap3_dpll4_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)53 int omap3_dpll4_set_rate(struct clk_hw *hw, unsigned long rate,
54 unsigned long parent_rate)
55 {
56 /*
57 * According to the 12-5 CDP code from TI, "Limitation 2.5"
58 * on 3430ES1 prevents us from changing DPLL multipliers or dividers
59 * on DPLL4.
60 */
61 if (ti_clk_features.flags & TI_CLK_DPLL4_DENY_REPROGRAM) {
62 pr_err("clock: DPLL4 cannot change rate due to silicon 'Limitation 2.5' on 3430ES1.\n");
63 return -EINVAL;
64 }
65
66 return omap3_noncore_dpll_set_rate(hw, rate, parent_rate);
67 }
68
69 /**
70 * omap3_dpll4_set_rate_and_parent - set rate and parent for omap3 per-dpll
71 * @hw: clock to change
72 * @rate: target rate for clock
73 * @parent_rate: rate of the parent clock
74 * @index: parent index, 0 - reference clock, 1 - bypass clock
75 *
76 * Check if the current SoC support the per-dpll reprogram operation
77 * or not, and then do the rate + parent change if supported. Returns
78 * -EINVAL if not supported, 0 for success, and potential error codes
79 * from the clock rate change.
80 */
omap3_dpll4_set_rate_and_parent(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate,u8 index)81 int omap3_dpll4_set_rate_and_parent(struct clk_hw *hw, unsigned long rate,
82 unsigned long parent_rate, u8 index)
83 {
84 if (ti_clk_features.flags & TI_CLK_DPLL4_DENY_REPROGRAM) {
85 pr_err("clock: DPLL4 cannot change rate due to silicon 'Limitation 2.5' on 3430ES1.\n");
86 return -EINVAL;
87 }
88
89 return omap3_noncore_dpll_set_rate_and_parent(hw, rate, parent_rate,
90 index);
91 }
92
omap3_clk_lock_dpll5(void)93 void __init omap3_clk_lock_dpll5(void)
94 {
95 struct clk *dpll5_clk;
96 struct clk *dpll5_m2_clk;
97
98 dpll5_clk = clk_get(NULL, "dpll5_ck");
99 clk_set_rate(dpll5_clk, DPLL5_FREQ_FOR_USBHOST);
100 clk_prepare_enable(dpll5_clk);
101
102 /* Program dpll5_m2_clk divider for no division */
103 dpll5_m2_clk = clk_get(NULL, "dpll5_m2_ck");
104 clk_prepare_enable(dpll5_m2_clk);
105 clk_set_rate(dpll5_m2_clk, DPLL5_FREQ_FOR_USBHOST);
106
107 clk_disable_unprepare(dpll5_m2_clk);
108 clk_disable_unprepare(dpll5_clk);
109 return;
110 }
111
112 /* Common clock code */
113
114 /*
115 * Switch the MPU rate if specified on cmdline. We cannot do this
116 * early until cmdline is parsed. XXX This should be removed from the
117 * clock code and handled by the OPP layer code in the near future.
118 */
omap3xxx_clk_arch_init(void)119 static int __init omap3xxx_clk_arch_init(void)
120 {
121 int ret;
122
123 if (!cpu_is_omap34xx())
124 return 0;
125
126 ret = omap2_clk_switch_mpurate_at_boot("dpll1_ck");
127 if (!ret)
128 omap2_clk_print_new_rates("osc_sys_ck", "core_ck", "arm_fck");
129
130 return ret;
131 }
132
133 omap_arch_initcall(omap3xxx_clk_arch_init);
134
135
136