1/*
2 * arch/arm/mach-lpc32xx/timer.c
3 *
4 * Author: Kevin Wells <kevin.wells@nxp.com>
5 *
6 * Copyright (C) 2009 - 2010 NXP Semiconductors
7 * Copyright (C) 2009 Fontys University of Applied Sciences, Eindhoven
8 *                    Ed Schouten <e.schouten@fontys.nl>
9 *                    Laurens Timmermans <l.timmermans@fontys.nl>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
19 * GNU General Public License for more details.
20 */
21
22#include <linux/interrupt.h>
23#include <linux/irq.h>
24#include <linux/time.h>
25#include <linux/err.h>
26#include <linux/clockchips.h>
27
28#include <asm/mach/time.h>
29
30#include <mach/hardware.h>
31#include <mach/platform.h>
32#include "common.h"
33
34static int lpc32xx_clkevt_next_event(unsigned long delta,
35    struct clock_event_device *dev)
36{
37	__raw_writel(LPC32XX_TIMER_CNTR_TCR_RESET,
38		LPC32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
39	__raw_writel(delta, LPC32XX_TIMER_PR(LPC32XX_TIMER0_BASE));
40	__raw_writel(LPC32XX_TIMER_CNTR_TCR_EN,
41		LPC32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
42
43	return 0;
44}
45
46static void lpc32xx_clkevt_mode(enum clock_event_mode mode,
47    struct clock_event_device *dev)
48{
49	switch (mode) {
50	case CLOCK_EVT_MODE_PERIODIC:
51		WARN_ON(1);
52		break;
53
54	case CLOCK_EVT_MODE_ONESHOT:
55	case CLOCK_EVT_MODE_SHUTDOWN:
56		/*
57		 * Disable the timer. When using oneshot, we must also
58		 * disable the timer to wait for the first call to
59		 * set_next_event().
60		 */
61		__raw_writel(0, LPC32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
62		break;
63
64	case CLOCK_EVT_MODE_UNUSED:
65	case CLOCK_EVT_MODE_RESUME:
66		break;
67	}
68}
69
70static struct clock_event_device lpc32xx_clkevt = {
71	.name		= "lpc32xx_clkevt",
72	.features	= CLOCK_EVT_FEAT_ONESHOT,
73	.rating		= 300,
74	.set_next_event	= lpc32xx_clkevt_next_event,
75	.set_mode	= lpc32xx_clkevt_mode,
76};
77
78static irqreturn_t lpc32xx_timer_interrupt(int irq, void *dev_id)
79{
80	struct clock_event_device *evt = &lpc32xx_clkevt;
81
82	/* Clear match */
83	__raw_writel(LPC32XX_TIMER_CNTR_MTCH_BIT(0),
84		LPC32XX_TIMER_IR(LPC32XX_TIMER0_BASE));
85
86	evt->event_handler(evt);
87
88	return IRQ_HANDLED;
89}
90
91static struct irqaction lpc32xx_timer_irq = {
92	.name		= "LPC32XX Timer Tick",
93	.flags		= IRQF_TIMER | IRQF_IRQPOLL,
94	.handler	= lpc32xx_timer_interrupt,
95};
96
97/*
98 * The clock management driver isn't initialized at this point, so the
99 * clocks need to be enabled here manually and then tagged as used in
100 * the clock driver initialization
101 */
102void __init lpc32xx_timer_init(void)
103{
104	u32 clkrate, pllreg;
105
106	/* Enable timer clock */
107	__raw_writel(LPC32XX_CLKPWR_TMRPWMCLK_TIMER0_EN |
108		LPC32XX_CLKPWR_TMRPWMCLK_TIMER1_EN,
109		LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1);
110
111	/*
112	 * The clock driver isn't initialized at this point. So determine if
113	 * the SYSCLK is driven from the PLL397 or main oscillator and then use
114	 * it to compute the PLL frequency and the PCLK divider to get the base
115	 * timer rates. This rate is needed to compute the tick rate.
116	 */
117	if (clk_is_sysclk_mainosc() != 0)
118		clkrate = LPC32XX_MAIN_OSC_FREQ;
119	else
120		clkrate = 397 * LPC32XX_CLOCK_OSC_FREQ;
121
122	/* Get ARM HCLKPLL register and convert it into a frequency */
123	pllreg = __raw_readl(LPC32XX_CLKPWR_HCLKPLL_CTRL) & 0x1FFFF;
124	clkrate = clk_get_pllrate_from_reg(clkrate, pllreg);
125
126	/* Get PCLK divider and divide ARM PLL clock by it to get timer rate */
127	clkrate = clkrate / clk_get_pclk_div();
128
129	/* Initial timer setup */
130	__raw_writel(0, LPC32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
131	__raw_writel(LPC32XX_TIMER_CNTR_MTCH_BIT(0),
132		LPC32XX_TIMER_IR(LPC32XX_TIMER0_BASE));
133	__raw_writel(1, LPC32XX_TIMER_MR0(LPC32XX_TIMER0_BASE));
134	__raw_writel(LPC32XX_TIMER_CNTR_MCR_MTCH(0) |
135		LPC32XX_TIMER_CNTR_MCR_STOP(0) |
136		LPC32XX_TIMER_CNTR_MCR_RESET(0),
137		LPC32XX_TIMER_MCR(LPC32XX_TIMER0_BASE));
138
139	/* Setup tick interrupt */
140	setup_irq(IRQ_LPC32XX_TIMER0, &lpc32xx_timer_irq);
141
142	/* Setup the clockevent structure. */
143	lpc32xx_clkevt.cpumask = cpumask_of(0);
144	clockevents_config_and_register(&lpc32xx_clkevt, clkrate, 1, -1);
145
146	/* Use timer1 as clock source. */
147	__raw_writel(LPC32XX_TIMER_CNTR_TCR_RESET,
148		LPC32XX_TIMER_TCR(LPC32XX_TIMER1_BASE));
149	__raw_writel(0, LPC32XX_TIMER_PR(LPC32XX_TIMER1_BASE));
150	__raw_writel(0, LPC32XX_TIMER_MCR(LPC32XX_TIMER1_BASE));
151	__raw_writel(LPC32XX_TIMER_CNTR_TCR_EN,
152		LPC32XX_TIMER_TCR(LPC32XX_TIMER1_BASE));
153
154	clocksource_mmio_init(LPC32XX_TIMER_TC(LPC32XX_TIMER1_BASE),
155		"lpc32xx_clksrc", clkrate, 300, 32, clocksource_mmio_readl_up);
156}
157