1 /*
2 * TI DaVinci DM644x chip specific setup
3 *
4 * Author: Kevin Hilman, Deep Root Systems, LLC
5 *
6 * 2007 (c) Deep Root Systems, LLC. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 */
11 #include <linux/init.h>
12 #include <linux/clk.h>
13 #include <linux/serial_8250.h>
14 #include <linux/platform_device.h>
15 #include <linux/platform_data/edma.h>
16 #include <linux/platform_data/gpio-davinci.h>
17
18 #include <asm/mach/map.h>
19
20 #include <mach/cputype.h>
21 #include <mach/irqs.h>
22 #include <mach/psc.h>
23 #include <mach/mux.h>
24 #include <mach/time.h>
25 #include <mach/serial.h>
26 #include <mach/common.h>
27
28 #include "davinci.h"
29 #include "clock.h"
30 #include "mux.h"
31 #include "asp.h"
32
33 /*
34 * Device specific clocks
35 */
36 #define DM644X_REF_FREQ 27000000
37
38 #define DM644X_EMAC_BASE 0x01c80000
39 #define DM644X_EMAC_MDIO_BASE (DM644X_EMAC_BASE + 0x4000)
40 #define DM644X_EMAC_CNTRL_OFFSET 0x0000
41 #define DM644X_EMAC_CNTRL_MOD_OFFSET 0x1000
42 #define DM644X_EMAC_CNTRL_RAM_OFFSET 0x2000
43 #define DM644X_EMAC_CNTRL_RAM_SIZE 0x2000
44
45 static struct pll_data pll1_data = {
46 .num = 1,
47 .phys_base = DAVINCI_PLL1_BASE,
48 };
49
50 static struct pll_data pll2_data = {
51 .num = 2,
52 .phys_base = DAVINCI_PLL2_BASE,
53 };
54
55 static struct clk ref_clk = {
56 .name = "ref_clk",
57 .rate = DM644X_REF_FREQ,
58 };
59
60 static struct clk pll1_clk = {
61 .name = "pll1",
62 .parent = &ref_clk,
63 .pll_data = &pll1_data,
64 .flags = CLK_PLL,
65 };
66
67 static struct clk pll1_sysclk1 = {
68 .name = "pll1_sysclk1",
69 .parent = &pll1_clk,
70 .flags = CLK_PLL,
71 .div_reg = PLLDIV1,
72 };
73
74 static struct clk pll1_sysclk2 = {
75 .name = "pll1_sysclk2",
76 .parent = &pll1_clk,
77 .flags = CLK_PLL,
78 .div_reg = PLLDIV2,
79 };
80
81 static struct clk pll1_sysclk3 = {
82 .name = "pll1_sysclk3",
83 .parent = &pll1_clk,
84 .flags = CLK_PLL,
85 .div_reg = PLLDIV3,
86 };
87
88 static struct clk pll1_sysclk5 = {
89 .name = "pll1_sysclk5",
90 .parent = &pll1_clk,
91 .flags = CLK_PLL,
92 .div_reg = PLLDIV5,
93 };
94
95 static struct clk pll1_aux_clk = {
96 .name = "pll1_aux_clk",
97 .parent = &pll1_clk,
98 .flags = CLK_PLL | PRE_PLL,
99 };
100
101 static struct clk pll1_sysclkbp = {
102 .name = "pll1_sysclkbp",
103 .parent = &pll1_clk,
104 .flags = CLK_PLL | PRE_PLL,
105 .div_reg = BPDIV
106 };
107
108 static struct clk pll2_clk = {
109 .name = "pll2",
110 .parent = &ref_clk,
111 .pll_data = &pll2_data,
112 .flags = CLK_PLL,
113 };
114
115 static struct clk pll2_sysclk1 = {
116 .name = "pll2_sysclk1",
117 .parent = &pll2_clk,
118 .flags = CLK_PLL,
119 .div_reg = PLLDIV1,
120 };
121
122 static struct clk pll2_sysclk2 = {
123 .name = "pll2_sysclk2",
124 .parent = &pll2_clk,
125 .flags = CLK_PLL,
126 .div_reg = PLLDIV2,
127 };
128
129 static struct clk pll2_sysclkbp = {
130 .name = "pll2_sysclkbp",
131 .parent = &pll2_clk,
132 .flags = CLK_PLL | PRE_PLL,
133 .div_reg = BPDIV
134 };
135
136 static struct clk dsp_clk = {
137 .name = "dsp",
138 .parent = &pll1_sysclk1,
139 .lpsc = DAVINCI_LPSC_GEM,
140 .domain = DAVINCI_GPSC_DSPDOMAIN,
141 .usecount = 1, /* REVISIT how to disable? */
142 };
143
144 static struct clk arm_clk = {
145 .name = "arm",
146 .parent = &pll1_sysclk2,
147 .lpsc = DAVINCI_LPSC_ARM,
148 .flags = ALWAYS_ENABLED,
149 };
150
151 static struct clk vicp_clk = {
152 .name = "vicp",
153 .parent = &pll1_sysclk2,
154 .lpsc = DAVINCI_LPSC_IMCOP,
155 .domain = DAVINCI_GPSC_DSPDOMAIN,
156 .usecount = 1, /* REVISIT how to disable? */
157 };
158
159 static struct clk vpss_master_clk = {
160 .name = "vpss_master",
161 .parent = &pll1_sysclk3,
162 .lpsc = DAVINCI_LPSC_VPSSMSTR,
163 .flags = CLK_PSC,
164 };
165
166 static struct clk vpss_slave_clk = {
167 .name = "vpss_slave",
168 .parent = &pll1_sysclk3,
169 .lpsc = DAVINCI_LPSC_VPSSSLV,
170 };
171
172 static struct clk uart0_clk = {
173 .name = "uart0",
174 .parent = &pll1_aux_clk,
175 .lpsc = DAVINCI_LPSC_UART0,
176 };
177
178 static struct clk uart1_clk = {
179 .name = "uart1",
180 .parent = &pll1_aux_clk,
181 .lpsc = DAVINCI_LPSC_UART1,
182 };
183
184 static struct clk uart2_clk = {
185 .name = "uart2",
186 .parent = &pll1_aux_clk,
187 .lpsc = DAVINCI_LPSC_UART2,
188 };
189
190 static struct clk emac_clk = {
191 .name = "emac",
192 .parent = &pll1_sysclk5,
193 .lpsc = DAVINCI_LPSC_EMAC_WRAPPER,
194 };
195
196 static struct clk i2c_clk = {
197 .name = "i2c",
198 .parent = &pll1_aux_clk,
199 .lpsc = DAVINCI_LPSC_I2C,
200 };
201
202 static struct clk ide_clk = {
203 .name = "ide",
204 .parent = &pll1_sysclk5,
205 .lpsc = DAVINCI_LPSC_ATA,
206 };
207
208 static struct clk asp_clk = {
209 .name = "asp0",
210 .parent = &pll1_sysclk5,
211 .lpsc = DAVINCI_LPSC_McBSP,
212 };
213
214 static struct clk mmcsd_clk = {
215 .name = "mmcsd",
216 .parent = &pll1_sysclk5,
217 .lpsc = DAVINCI_LPSC_MMC_SD,
218 };
219
220 static struct clk spi_clk = {
221 .name = "spi",
222 .parent = &pll1_sysclk5,
223 .lpsc = DAVINCI_LPSC_SPI,
224 };
225
226 static struct clk gpio_clk = {
227 .name = "gpio",
228 .parent = &pll1_sysclk5,
229 .lpsc = DAVINCI_LPSC_GPIO,
230 };
231
232 static struct clk usb_clk = {
233 .name = "usb",
234 .parent = &pll1_sysclk5,
235 .lpsc = DAVINCI_LPSC_USB,
236 };
237
238 static struct clk vlynq_clk = {
239 .name = "vlynq",
240 .parent = &pll1_sysclk5,
241 .lpsc = DAVINCI_LPSC_VLYNQ,
242 };
243
244 static struct clk aemif_clk = {
245 .name = "aemif",
246 .parent = &pll1_sysclk5,
247 .lpsc = DAVINCI_LPSC_AEMIF,
248 };
249
250 static struct clk pwm0_clk = {
251 .name = "pwm0",
252 .parent = &pll1_aux_clk,
253 .lpsc = DAVINCI_LPSC_PWM0,
254 };
255
256 static struct clk pwm1_clk = {
257 .name = "pwm1",
258 .parent = &pll1_aux_clk,
259 .lpsc = DAVINCI_LPSC_PWM1,
260 };
261
262 static struct clk pwm2_clk = {
263 .name = "pwm2",
264 .parent = &pll1_aux_clk,
265 .lpsc = DAVINCI_LPSC_PWM2,
266 };
267
268 static struct clk timer0_clk = {
269 .name = "timer0",
270 .parent = &pll1_aux_clk,
271 .lpsc = DAVINCI_LPSC_TIMER0,
272 };
273
274 static struct clk timer1_clk = {
275 .name = "timer1",
276 .parent = &pll1_aux_clk,
277 .lpsc = DAVINCI_LPSC_TIMER1,
278 };
279
280 static struct clk timer2_clk = {
281 .name = "timer2",
282 .parent = &pll1_aux_clk,
283 .lpsc = DAVINCI_LPSC_TIMER2,
284 .usecount = 1, /* REVISIT: why can't this be disabled? */
285 };
286
287 static struct clk_lookup dm644x_clks[] = {
288 CLK(NULL, "ref", &ref_clk),
289 CLK(NULL, "pll1", &pll1_clk),
290 CLK(NULL, "pll1_sysclk1", &pll1_sysclk1),
291 CLK(NULL, "pll1_sysclk2", &pll1_sysclk2),
292 CLK(NULL, "pll1_sysclk3", &pll1_sysclk3),
293 CLK(NULL, "pll1_sysclk5", &pll1_sysclk5),
294 CLK(NULL, "pll1_aux", &pll1_aux_clk),
295 CLK(NULL, "pll1_sysclkbp", &pll1_sysclkbp),
296 CLK(NULL, "pll2", &pll2_clk),
297 CLK(NULL, "pll2_sysclk1", &pll2_sysclk1),
298 CLK(NULL, "pll2_sysclk2", &pll2_sysclk2),
299 CLK(NULL, "pll2_sysclkbp", &pll2_sysclkbp),
300 CLK(NULL, "dsp", &dsp_clk),
301 CLK(NULL, "arm", &arm_clk),
302 CLK(NULL, "vicp", &vicp_clk),
303 CLK("vpss", "master", &vpss_master_clk),
304 CLK("vpss", "slave", &vpss_slave_clk),
305 CLK(NULL, "arm", &arm_clk),
306 CLK("serial8250.0", NULL, &uart0_clk),
307 CLK("serial8250.1", NULL, &uart1_clk),
308 CLK("serial8250.2", NULL, &uart2_clk),
309 CLK("davinci_emac.1", NULL, &emac_clk),
310 CLK("davinci_mdio.0", "fck", &emac_clk),
311 CLK("i2c_davinci.1", NULL, &i2c_clk),
312 CLK("palm_bk3710", NULL, &ide_clk),
313 CLK("davinci-mcbsp", NULL, &asp_clk),
314 CLK("dm6441-mmc.0", NULL, &mmcsd_clk),
315 CLK(NULL, "spi", &spi_clk),
316 CLK(NULL, "gpio", &gpio_clk),
317 CLK(NULL, "usb", &usb_clk),
318 CLK(NULL, "vlynq", &vlynq_clk),
319 CLK(NULL, "aemif", &aemif_clk),
320 CLK(NULL, "pwm0", &pwm0_clk),
321 CLK(NULL, "pwm1", &pwm1_clk),
322 CLK(NULL, "pwm2", &pwm2_clk),
323 CLK(NULL, "timer0", &timer0_clk),
324 CLK(NULL, "timer1", &timer1_clk),
325 CLK("davinci-wdt", NULL, &timer2_clk),
326 CLK(NULL, NULL, NULL),
327 };
328
329 static struct emac_platform_data dm644x_emac_pdata = {
330 .ctrl_reg_offset = DM644X_EMAC_CNTRL_OFFSET,
331 .ctrl_mod_reg_offset = DM644X_EMAC_CNTRL_MOD_OFFSET,
332 .ctrl_ram_offset = DM644X_EMAC_CNTRL_RAM_OFFSET,
333 .ctrl_ram_size = DM644X_EMAC_CNTRL_RAM_SIZE,
334 .version = EMAC_VERSION_1,
335 };
336
337 static struct resource dm644x_emac_resources[] = {
338 {
339 .start = DM644X_EMAC_BASE,
340 .end = DM644X_EMAC_BASE + SZ_16K - 1,
341 .flags = IORESOURCE_MEM,
342 },
343 {
344 .start = IRQ_EMACINT,
345 .end = IRQ_EMACINT,
346 .flags = IORESOURCE_IRQ,
347 },
348 };
349
350 static struct platform_device dm644x_emac_device = {
351 .name = "davinci_emac",
352 .id = 1,
353 .dev = {
354 .platform_data = &dm644x_emac_pdata,
355 },
356 .num_resources = ARRAY_SIZE(dm644x_emac_resources),
357 .resource = dm644x_emac_resources,
358 };
359
360 static struct resource dm644x_mdio_resources[] = {
361 {
362 .start = DM644X_EMAC_MDIO_BASE,
363 .end = DM644X_EMAC_MDIO_BASE + SZ_4K - 1,
364 .flags = IORESOURCE_MEM,
365 },
366 };
367
368 static struct platform_device dm644x_mdio_device = {
369 .name = "davinci_mdio",
370 .id = 0,
371 .num_resources = ARRAY_SIZE(dm644x_mdio_resources),
372 .resource = dm644x_mdio_resources,
373 };
374
375 /*
376 * Device specific mux setup
377 *
378 * soc description mux mode mode mux dbg
379 * reg offset mask mode
380 */
381 static const struct mux_config dm644x_pins[] = {
382 #ifdef CONFIG_DAVINCI_MUX
383 MUX_CFG(DM644X, HDIREN, 0, 16, 1, 1, true)
384 MUX_CFG(DM644X, ATAEN, 0, 17, 1, 1, true)
385 MUX_CFG(DM644X, ATAEN_DISABLE, 0, 17, 1, 0, true)
386
387 MUX_CFG(DM644X, HPIEN_DISABLE, 0, 29, 1, 0, true)
388
389 MUX_CFG(DM644X, AEAW, 0, 0, 31, 31, true)
390 MUX_CFG(DM644X, AEAW0, 0, 0, 1, 0, true)
391 MUX_CFG(DM644X, AEAW1, 0, 1, 1, 0, true)
392 MUX_CFG(DM644X, AEAW2, 0, 2, 1, 0, true)
393 MUX_CFG(DM644X, AEAW3, 0, 3, 1, 0, true)
394 MUX_CFG(DM644X, AEAW4, 0, 4, 1, 0, true)
395
396 MUX_CFG(DM644X, MSTK, 1, 9, 1, 0, false)
397
398 MUX_CFG(DM644X, I2C, 1, 7, 1, 1, false)
399
400 MUX_CFG(DM644X, MCBSP, 1, 10, 1, 1, false)
401
402 MUX_CFG(DM644X, UART1, 1, 1, 1, 1, true)
403 MUX_CFG(DM644X, UART2, 1, 2, 1, 1, true)
404
405 MUX_CFG(DM644X, PWM0, 1, 4, 1, 1, false)
406
407 MUX_CFG(DM644X, PWM1, 1, 5, 1, 1, false)
408
409 MUX_CFG(DM644X, PWM2, 1, 6, 1, 1, false)
410
411 MUX_CFG(DM644X, VLYNQEN, 0, 15, 1, 1, false)
412 MUX_CFG(DM644X, VLSCREN, 0, 14, 1, 1, false)
413 MUX_CFG(DM644X, VLYNQWD, 0, 12, 3, 3, false)
414
415 MUX_CFG(DM644X, EMACEN, 0, 31, 1, 1, true)
416
417 MUX_CFG(DM644X, GPIO3V, 0, 31, 1, 0, true)
418
419 MUX_CFG(DM644X, GPIO0, 0, 24, 1, 0, true)
420 MUX_CFG(DM644X, GPIO3, 0, 25, 1, 0, false)
421 MUX_CFG(DM644X, GPIO43_44, 1, 7, 1, 0, false)
422 MUX_CFG(DM644X, GPIO46_47, 0, 22, 1, 0, true)
423
424 MUX_CFG(DM644X, RGB666, 0, 22, 1, 1, true)
425
426 MUX_CFG(DM644X, LOEEN, 0, 24, 1, 1, true)
427 MUX_CFG(DM644X, LFLDEN, 0, 25, 1, 1, false)
428 #endif
429 };
430
431 /* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */
432 static u8 dm644x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
433 [IRQ_VDINT0] = 2,
434 [IRQ_VDINT1] = 6,
435 [IRQ_VDINT2] = 6,
436 [IRQ_HISTINT] = 6,
437 [IRQ_H3AINT] = 6,
438 [IRQ_PRVUINT] = 6,
439 [IRQ_RSZINT] = 6,
440 [7] = 7,
441 [IRQ_VENCINT] = 6,
442 [IRQ_ASQINT] = 6,
443 [IRQ_IMXINT] = 6,
444 [IRQ_VLCDINT] = 6,
445 [IRQ_USBINT] = 4,
446 [IRQ_EMACINT] = 4,
447 [14] = 7,
448 [15] = 7,
449 [IRQ_CCINT0] = 5, /* dma */
450 [IRQ_CCERRINT] = 5, /* dma */
451 [IRQ_TCERRINT0] = 5, /* dma */
452 [IRQ_TCERRINT] = 5, /* dma */
453 [IRQ_PSCIN] = 7,
454 [21] = 7,
455 [IRQ_IDE] = 4,
456 [23] = 7,
457 [IRQ_MBXINT] = 7,
458 [IRQ_MBRINT] = 7,
459 [IRQ_MMCINT] = 7,
460 [IRQ_SDIOINT] = 7,
461 [28] = 7,
462 [IRQ_DDRINT] = 7,
463 [IRQ_AEMIFINT] = 7,
464 [IRQ_VLQINT] = 4,
465 [IRQ_TINT0_TINT12] = 2, /* clockevent */
466 [IRQ_TINT0_TINT34] = 2, /* clocksource */
467 [IRQ_TINT1_TINT12] = 7, /* DSP timer */
468 [IRQ_TINT1_TINT34] = 7, /* system tick */
469 [IRQ_PWMINT0] = 7,
470 [IRQ_PWMINT1] = 7,
471 [IRQ_PWMINT2] = 7,
472 [IRQ_I2C] = 3,
473 [IRQ_UARTINT0] = 3,
474 [IRQ_UARTINT1] = 3,
475 [IRQ_UARTINT2] = 3,
476 [IRQ_SPINT0] = 3,
477 [IRQ_SPINT1] = 3,
478 [45] = 7,
479 [IRQ_DSP2ARM0] = 4,
480 [IRQ_DSP2ARM1] = 4,
481 [IRQ_GPIO0] = 7,
482 [IRQ_GPIO1] = 7,
483 [IRQ_GPIO2] = 7,
484 [IRQ_GPIO3] = 7,
485 [IRQ_GPIO4] = 7,
486 [IRQ_GPIO5] = 7,
487 [IRQ_GPIO6] = 7,
488 [IRQ_GPIO7] = 7,
489 [IRQ_GPIOBNK0] = 7,
490 [IRQ_GPIOBNK1] = 7,
491 [IRQ_GPIOBNK2] = 7,
492 [IRQ_GPIOBNK3] = 7,
493 [IRQ_GPIOBNK4] = 7,
494 [IRQ_COMMTX] = 7,
495 [IRQ_COMMRX] = 7,
496 [IRQ_EMUINT] = 7,
497 };
498
499 /*----------------------------------------------------------------------*/
500
501 static s8
502 queue_priority_mapping[][2] = {
503 /* {event queue no, Priority} */
504 {0, 3},
505 {1, 7},
506 {-1, -1},
507 };
508
509 static struct edma_soc_info edma_cc0_info = {
510 .queue_priority_mapping = queue_priority_mapping,
511 .default_queue = EVENTQ_1,
512 };
513
514 static struct edma_soc_info *dm644x_edma_info[EDMA_MAX_CC] = {
515 &edma_cc0_info,
516 };
517
518 static struct resource edma_resources[] = {
519 {
520 .name = "edma_cc0",
521 .start = 0x01c00000,
522 .end = 0x01c00000 + SZ_64K - 1,
523 .flags = IORESOURCE_MEM,
524 },
525 {
526 .name = "edma_tc0",
527 .start = 0x01c10000,
528 .end = 0x01c10000 + SZ_1K - 1,
529 .flags = IORESOURCE_MEM,
530 },
531 {
532 .name = "edma_tc1",
533 .start = 0x01c10400,
534 .end = 0x01c10400 + SZ_1K - 1,
535 .flags = IORESOURCE_MEM,
536 },
537 {
538 .name = "edma0",
539 .start = IRQ_CCINT0,
540 .flags = IORESOURCE_IRQ,
541 },
542 {
543 .name = "edma0_err",
544 .start = IRQ_CCERRINT,
545 .flags = IORESOURCE_IRQ,
546 },
547 /* not using TC*_ERR */
548 };
549
550 static struct platform_device dm644x_edma_device = {
551 .name = "edma",
552 .id = 0,
553 .dev.platform_data = dm644x_edma_info,
554 .num_resources = ARRAY_SIZE(edma_resources),
555 .resource = edma_resources,
556 };
557
558 /* DM6446 EVM uses ASP0; line-out is a pair of RCA jacks */
559 static struct resource dm644x_asp_resources[] = {
560 {
561 .name = "mpu",
562 .start = DAVINCI_ASP0_BASE,
563 .end = DAVINCI_ASP0_BASE + SZ_8K - 1,
564 .flags = IORESOURCE_MEM,
565 },
566 {
567 .start = DAVINCI_DMA_ASP0_TX,
568 .end = DAVINCI_DMA_ASP0_TX,
569 .flags = IORESOURCE_DMA,
570 },
571 {
572 .start = DAVINCI_DMA_ASP0_RX,
573 .end = DAVINCI_DMA_ASP0_RX,
574 .flags = IORESOURCE_DMA,
575 },
576 };
577
578 static struct platform_device dm644x_asp_device = {
579 .name = "davinci-mcbsp",
580 .id = -1,
581 .num_resources = ARRAY_SIZE(dm644x_asp_resources),
582 .resource = dm644x_asp_resources,
583 };
584
585 #define DM644X_VPSS_BASE 0x01c73400
586
587 static struct resource dm644x_vpss_resources[] = {
588 {
589 /* VPSS Base address */
590 .name = "vpss",
591 .start = DM644X_VPSS_BASE,
592 .end = DM644X_VPSS_BASE + 0xff,
593 .flags = IORESOURCE_MEM,
594 },
595 };
596
597 static struct platform_device dm644x_vpss_device = {
598 .name = "vpss",
599 .id = -1,
600 .dev.platform_data = "dm644x_vpss",
601 .num_resources = ARRAY_SIZE(dm644x_vpss_resources),
602 .resource = dm644x_vpss_resources,
603 };
604
605 static struct resource dm644x_vpfe_resources[] = {
606 {
607 .start = IRQ_VDINT0,
608 .end = IRQ_VDINT0,
609 .flags = IORESOURCE_IRQ,
610 },
611 {
612 .start = IRQ_VDINT1,
613 .end = IRQ_VDINT1,
614 .flags = IORESOURCE_IRQ,
615 },
616 };
617
618 static u64 dm644x_video_dma_mask = DMA_BIT_MASK(32);
619 static struct resource dm644x_ccdc_resource[] = {
620 /* CCDC Base address */
621 {
622 .start = 0x01c70400,
623 .end = 0x01c70400 + 0xff,
624 .flags = IORESOURCE_MEM,
625 },
626 };
627
628 static struct platform_device dm644x_ccdc_dev = {
629 .name = "dm644x_ccdc",
630 .id = -1,
631 .num_resources = ARRAY_SIZE(dm644x_ccdc_resource),
632 .resource = dm644x_ccdc_resource,
633 .dev = {
634 .dma_mask = &dm644x_video_dma_mask,
635 .coherent_dma_mask = DMA_BIT_MASK(32),
636 },
637 };
638
639 static struct platform_device dm644x_vpfe_dev = {
640 .name = CAPTURE_DRV_NAME,
641 .id = -1,
642 .num_resources = ARRAY_SIZE(dm644x_vpfe_resources),
643 .resource = dm644x_vpfe_resources,
644 .dev = {
645 .dma_mask = &dm644x_video_dma_mask,
646 .coherent_dma_mask = DMA_BIT_MASK(32),
647 },
648 };
649
650 #define DM644X_OSD_BASE 0x01c72600
651
652 static struct resource dm644x_osd_resources[] = {
653 {
654 .start = DM644X_OSD_BASE,
655 .end = DM644X_OSD_BASE + 0x1ff,
656 .flags = IORESOURCE_MEM,
657 },
658 };
659
660 static struct platform_device dm644x_osd_dev = {
661 .name = DM644X_VPBE_OSD_SUBDEV_NAME,
662 .id = -1,
663 .num_resources = ARRAY_SIZE(dm644x_osd_resources),
664 .resource = dm644x_osd_resources,
665 .dev = {
666 .dma_mask = &dm644x_video_dma_mask,
667 .coherent_dma_mask = DMA_BIT_MASK(32),
668 },
669 };
670
671 #define DM644X_VENC_BASE 0x01c72400
672
673 static struct resource dm644x_venc_resources[] = {
674 {
675 .start = DM644X_VENC_BASE,
676 .end = DM644X_VENC_BASE + 0x17f,
677 .flags = IORESOURCE_MEM,
678 },
679 };
680
681 #define DM644X_VPSS_MUXSEL_PLL2_MODE BIT(0)
682 #define DM644X_VPSS_MUXSEL_VPBECLK_MODE BIT(1)
683 #define DM644X_VPSS_VENCLKEN BIT(3)
684 #define DM644X_VPSS_DACCLKEN BIT(4)
685
dm644x_venc_setup_clock(enum vpbe_enc_timings_type type,unsigned int pclock)686 static int dm644x_venc_setup_clock(enum vpbe_enc_timings_type type,
687 unsigned int pclock)
688 {
689 int ret = 0;
690 u32 v = DM644X_VPSS_VENCLKEN;
691
692 switch (type) {
693 case VPBE_ENC_STD:
694 v |= DM644X_VPSS_DACCLKEN;
695 writel(v, DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL));
696 break;
697 case VPBE_ENC_DV_TIMINGS:
698 if (pclock <= 27000000) {
699 v |= DM644X_VPSS_DACCLKEN;
700 writel(v, DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL));
701 } else {
702 /*
703 * For HD, use external clock source since
704 * HD requires higher clock rate
705 */
706 v |= DM644X_VPSS_MUXSEL_VPBECLK_MODE;
707 writel(v, DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL));
708 }
709 break;
710 default:
711 ret = -EINVAL;
712 }
713
714 return ret;
715 }
716
717 static struct resource dm644x_v4l2_disp_resources[] = {
718 {
719 .start = IRQ_VENCINT,
720 .end = IRQ_VENCINT,
721 .flags = IORESOURCE_IRQ,
722 },
723 };
724
725 static struct platform_device dm644x_vpbe_display = {
726 .name = "vpbe-v4l2",
727 .id = -1,
728 .num_resources = ARRAY_SIZE(dm644x_v4l2_disp_resources),
729 .resource = dm644x_v4l2_disp_resources,
730 .dev = {
731 .dma_mask = &dm644x_video_dma_mask,
732 .coherent_dma_mask = DMA_BIT_MASK(32),
733 },
734 };
735
736 static struct venc_platform_data dm644x_venc_pdata = {
737 .setup_clock = dm644x_venc_setup_clock,
738 };
739
740 static struct platform_device dm644x_venc_dev = {
741 .name = DM644X_VPBE_VENC_SUBDEV_NAME,
742 .id = -1,
743 .num_resources = ARRAY_SIZE(dm644x_venc_resources),
744 .resource = dm644x_venc_resources,
745 .dev = {
746 .dma_mask = &dm644x_video_dma_mask,
747 .coherent_dma_mask = DMA_BIT_MASK(32),
748 .platform_data = &dm644x_venc_pdata,
749 },
750 };
751
752 static struct platform_device dm644x_vpbe_dev = {
753 .name = "vpbe_controller",
754 .id = -1,
755 .dev = {
756 .dma_mask = &dm644x_video_dma_mask,
757 .coherent_dma_mask = DMA_BIT_MASK(32),
758 },
759 };
760
761 static struct resource dm644_gpio_resources[] = {
762 { /* registers */
763 .start = DAVINCI_GPIO_BASE,
764 .end = DAVINCI_GPIO_BASE + SZ_4K - 1,
765 .flags = IORESOURCE_MEM,
766 },
767 { /* interrupt */
768 .start = IRQ_GPIOBNK0,
769 .end = IRQ_GPIOBNK4,
770 .flags = IORESOURCE_IRQ,
771 },
772 };
773
774 static struct davinci_gpio_platform_data dm644_gpio_platform_data = {
775 .ngpio = 71,
776 };
777
dm644x_gpio_register(void)778 int __init dm644x_gpio_register(void)
779 {
780 return davinci_gpio_register(dm644_gpio_resources,
781 ARRAY_SIZE(dm644_gpio_resources),
782 &dm644_gpio_platform_data);
783 }
784 /*----------------------------------------------------------------------*/
785
786 static struct map_desc dm644x_io_desc[] = {
787 {
788 .virtual = IO_VIRT,
789 .pfn = __phys_to_pfn(IO_PHYS),
790 .length = IO_SIZE,
791 .type = MT_DEVICE
792 },
793 };
794
795 /* Contents of JTAG ID register used to identify exact cpu type */
796 static struct davinci_id dm644x_ids[] = {
797 {
798 .variant = 0x0,
799 .part_no = 0xb700,
800 .manufacturer = 0x017,
801 .cpu_id = DAVINCI_CPU_ID_DM6446,
802 .name = "dm6446",
803 },
804 {
805 .variant = 0x1,
806 .part_no = 0xb700,
807 .manufacturer = 0x017,
808 .cpu_id = DAVINCI_CPU_ID_DM6446,
809 .name = "dm6446a",
810 },
811 };
812
813 static u32 dm644x_psc_bases[] = { DAVINCI_PWR_SLEEP_CNTRL_BASE };
814
815 /*
816 * T0_BOT: Timer 0, bottom: clockevent source for hrtimers
817 * T0_TOP: Timer 0, top : clocksource for generic timekeeping
818 * T1_BOT: Timer 1, bottom: (used by DSP in TI DSPLink code)
819 * T1_TOP: Timer 1, top : <unused>
820 */
821 static struct davinci_timer_info dm644x_timer_info = {
822 .timers = davinci_timer_instance,
823 .clockevent_id = T0_BOT,
824 .clocksource_id = T0_TOP,
825 };
826
827 static struct plat_serial8250_port dm644x_serial0_platform_data[] = {
828 {
829 .mapbase = DAVINCI_UART0_BASE,
830 .irq = IRQ_UARTINT0,
831 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
832 UPF_IOREMAP,
833 .iotype = UPIO_MEM,
834 .regshift = 2,
835 },
836 {
837 .flags = 0,
838 }
839 };
840 static struct plat_serial8250_port dm644x_serial1_platform_data[] = {
841 {
842 .mapbase = DAVINCI_UART1_BASE,
843 .irq = IRQ_UARTINT1,
844 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
845 UPF_IOREMAP,
846 .iotype = UPIO_MEM,
847 .regshift = 2,
848 },
849 {
850 .flags = 0,
851 }
852 };
853 static struct plat_serial8250_port dm644x_serial2_platform_data[] = {
854 {
855 .mapbase = DAVINCI_UART2_BASE,
856 .irq = IRQ_UARTINT2,
857 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
858 UPF_IOREMAP,
859 .iotype = UPIO_MEM,
860 .regshift = 2,
861 },
862 {
863 .flags = 0,
864 }
865 };
866
867 struct platform_device dm644x_serial_device[] = {
868 {
869 .name = "serial8250",
870 .id = PLAT8250_DEV_PLATFORM,
871 .dev = {
872 .platform_data = dm644x_serial0_platform_data,
873 }
874 },
875 {
876 .name = "serial8250",
877 .id = PLAT8250_DEV_PLATFORM1,
878 .dev = {
879 .platform_data = dm644x_serial1_platform_data,
880 }
881 },
882 {
883 .name = "serial8250",
884 .id = PLAT8250_DEV_PLATFORM2,
885 .dev = {
886 .platform_data = dm644x_serial2_platform_data,
887 }
888 },
889 {
890 }
891 };
892
893 static struct davinci_soc_info davinci_soc_info_dm644x = {
894 .io_desc = dm644x_io_desc,
895 .io_desc_num = ARRAY_SIZE(dm644x_io_desc),
896 .jtag_id_reg = 0x01c40028,
897 .ids = dm644x_ids,
898 .ids_num = ARRAY_SIZE(dm644x_ids),
899 .cpu_clks = dm644x_clks,
900 .psc_bases = dm644x_psc_bases,
901 .psc_bases_num = ARRAY_SIZE(dm644x_psc_bases),
902 .pinmux_base = DAVINCI_SYSTEM_MODULE_BASE,
903 .pinmux_pins = dm644x_pins,
904 .pinmux_pins_num = ARRAY_SIZE(dm644x_pins),
905 .intc_base = DAVINCI_ARM_INTC_BASE,
906 .intc_type = DAVINCI_INTC_TYPE_AINTC,
907 .intc_irq_prios = dm644x_default_priorities,
908 .intc_irq_num = DAVINCI_N_AINTC_IRQ,
909 .timer_info = &dm644x_timer_info,
910 .emac_pdata = &dm644x_emac_pdata,
911 .sram_dma = 0x00008000,
912 .sram_len = SZ_16K,
913 };
914
dm644x_init_asp(struct snd_platform_data * pdata)915 void __init dm644x_init_asp(struct snd_platform_data *pdata)
916 {
917 davinci_cfg_reg(DM644X_MCBSP);
918 dm644x_asp_device.dev.platform_data = pdata;
919 platform_device_register(&dm644x_asp_device);
920 }
921
dm644x_init(void)922 void __init dm644x_init(void)
923 {
924 davinci_common_init(&davinci_soc_info_dm644x);
925 davinci_map_sysmod();
926 }
927
dm644x_init_video(struct vpfe_config * vpfe_cfg,struct vpbe_config * vpbe_cfg)928 int __init dm644x_init_video(struct vpfe_config *vpfe_cfg,
929 struct vpbe_config *vpbe_cfg)
930 {
931 if (vpfe_cfg || vpbe_cfg)
932 platform_device_register(&dm644x_vpss_device);
933
934 if (vpfe_cfg) {
935 dm644x_vpfe_dev.dev.platform_data = vpfe_cfg;
936 platform_device_register(&dm644x_ccdc_dev);
937 platform_device_register(&dm644x_vpfe_dev);
938 }
939
940 if (vpbe_cfg) {
941 dm644x_vpbe_dev.dev.platform_data = vpbe_cfg;
942 platform_device_register(&dm644x_osd_dev);
943 platform_device_register(&dm644x_venc_dev);
944 platform_device_register(&dm644x_vpbe_dev);
945 platform_device_register(&dm644x_vpbe_display);
946 }
947
948 return 0;
949 }
950
dm644x_init_devices(void)951 static int __init dm644x_init_devices(void)
952 {
953 int ret = 0;
954
955 if (!cpu_is_davinci_dm644x())
956 return 0;
957
958 platform_device_register(&dm644x_edma_device);
959
960 platform_device_register(&dm644x_mdio_device);
961 platform_device_register(&dm644x_emac_device);
962
963 ret = davinci_init_wdt();
964 if (ret)
965 pr_warn("%s: watchdog init failed: %d\n", __func__, ret);
966
967 return ret;
968 }
969 postcore_initcall(dm644x_init_devices);
970