1/* 2 * linux/arch/arm/kernel/pj4-cp0.c 3 * 4 * PJ4 iWMMXt coprocessor context switching and handling 5 * 6 * Copyright (c) 2010 Marvell International Inc. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 */ 12 13#include <linux/types.h> 14#include <linux/kernel.h> 15#include <linux/signal.h> 16#include <linux/sched.h> 17#include <linux/init.h> 18#include <linux/io.h> 19#include <asm/thread_notify.h> 20#include <asm/cputype.h> 21 22static int iwmmxt_do(struct notifier_block *self, unsigned long cmd, void *t) 23{ 24 struct thread_info *thread = t; 25 26 switch (cmd) { 27 case THREAD_NOTIFY_FLUSH: 28 /* 29 * flush_thread() zeroes thread->fpstate, so no need 30 * to do anything here. 31 * 32 * FALLTHROUGH: Ensure we don't try to overwrite our newly 33 * initialised state information on the first fault. 34 */ 35 36 case THREAD_NOTIFY_EXIT: 37 iwmmxt_task_release(thread); 38 break; 39 40 case THREAD_NOTIFY_SWITCH: 41 iwmmxt_task_switch(thread); 42 break; 43 } 44 45 return NOTIFY_DONE; 46} 47 48static struct notifier_block __maybe_unused iwmmxt_notifier_block = { 49 .notifier_call = iwmmxt_do, 50}; 51 52 53static u32 __init pj4_cp_access_read(void) 54{ 55 u32 value; 56 57 __asm__ __volatile__ ( 58 "mrc p15, 0, %0, c1, c0, 2\n\t" 59 : "=r" (value)); 60 return value; 61} 62 63static void __init pj4_cp_access_write(u32 value) 64{ 65 u32 temp; 66 67 __asm__ __volatile__ ( 68 "mcr p15, 0, %1, c1, c0, 2\n\t" 69 "mrc p15, 0, %0, c1, c0, 2\n\t" 70 "mov %0, %0\n\t" 71 "sub pc, pc, #4\n\t" 72 : "=r" (temp) : "r" (value)); 73} 74 75static int __init pj4_get_iwmmxt_version(void) 76{ 77 u32 cp_access, wcid; 78 79 cp_access = pj4_cp_access_read(); 80 pj4_cp_access_write(cp_access | 0xf); 81 82 /* check if coprocessor 0 and 1 are available */ 83 if ((pj4_cp_access_read() & 0xf) != 0xf) { 84 pj4_cp_access_write(cp_access); 85 return -ENODEV; 86 } 87 88 /* read iWMMXt coprocessor id register p1, c0 */ 89 __asm__ __volatile__ ("mrc p1, 0, %0, c0, c0, 0\n" : "=r" (wcid)); 90 91 pj4_cp_access_write(cp_access); 92 93 /* iWMMXt v1 */ 94 if ((wcid & 0xffffff00) == 0x56051000) 95 return 1; 96 /* iWMMXt v2 */ 97 if ((wcid & 0xffffff00) == 0x56052000) 98 return 2; 99 100 return -EINVAL; 101} 102 103/* 104 * Disable CP0/CP1 on boot, and let call_fpe() and the iWMMXt lazy 105 * switch code handle iWMMXt context switching. 106 */ 107static int __init pj4_cp0_init(void) 108{ 109 u32 __maybe_unused cp_access; 110 int vers; 111 112 if (!cpu_is_pj4()) 113 return 0; 114 115 vers = pj4_get_iwmmxt_version(); 116 if (vers < 0) 117 return 0; 118 119#ifndef CONFIG_IWMMXT 120 pr_info("PJ4 iWMMXt coprocessor detected, but kernel support is missing.\n"); 121#else 122 cp_access = pj4_cp_access_read() & ~0xf; 123 pj4_cp_access_write(cp_access); 124 125 pr_info("PJ4 iWMMXt v%d coprocessor enabled.\n", vers); 126 elf_hwcap |= HWCAP_IWMMXT; 127 thread_register_notifier(&iwmmxt_notifier_block); 128#endif 129 130 return 0; 131} 132 133late_initcall(pj4_cp0_init); 134