1/* 2 * arch/arm/include/asm/hardware/cache-l2x0.h 3 * 4 * Copyright (C) 2007 ARM Limited 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 18 */ 19 20#ifndef __ASM_ARM_HARDWARE_L2X0_H 21#define __ASM_ARM_HARDWARE_L2X0_H 22 23#include <linux/errno.h> 24 25#define L2X0_CACHE_ID 0x000 26#define L2X0_CACHE_TYPE 0x004 27#define L2X0_CTRL 0x100 28#define L2X0_AUX_CTRL 0x104 29#define L310_TAG_LATENCY_CTRL 0x108 30#define L310_DATA_LATENCY_CTRL 0x10C 31#define L2X0_EVENT_CNT_CTRL 0x200 32#define L2X0_EVENT_CNT1_CFG 0x204 33#define L2X0_EVENT_CNT0_CFG 0x208 34#define L2X0_EVENT_CNT1_VAL 0x20C 35#define L2X0_EVENT_CNT0_VAL 0x210 36#define L2X0_INTR_MASK 0x214 37#define L2X0_MASKED_INTR_STAT 0x218 38#define L2X0_RAW_INTR_STAT 0x21C 39#define L2X0_INTR_CLEAR 0x220 40#define L2X0_CACHE_SYNC 0x730 41#define L2X0_DUMMY_REG 0x740 42#define L2X0_INV_LINE_PA 0x770 43#define L2X0_INV_WAY 0x77C 44#define L2X0_CLEAN_LINE_PA 0x7B0 45#define L2X0_CLEAN_LINE_IDX 0x7B8 46#define L2X0_CLEAN_WAY 0x7BC 47#define L2X0_CLEAN_INV_LINE_PA 0x7F0 48#define L2X0_CLEAN_INV_LINE_IDX 0x7F8 49#define L2X0_CLEAN_INV_WAY 0x7FC 50/* 51 * The lockdown registers repeat 8 times for L310, the L210 has only one 52 * D and one I lockdown register at 0x0900 and 0x0904. 53 */ 54#define L2X0_LOCKDOWN_WAY_D_BASE 0x900 55#define L2X0_LOCKDOWN_WAY_I_BASE 0x904 56#define L2X0_LOCKDOWN_STRIDE 0x08 57#define L310_ADDR_FILTER_START 0xC00 58#define L310_ADDR_FILTER_END 0xC04 59#define L2X0_TEST_OPERATION 0xF00 60#define L2X0_LINE_DATA 0xF10 61#define L2X0_LINE_TAG 0xF30 62#define L2X0_DEBUG_CTRL 0xF40 63#define L310_PREFETCH_CTRL 0xF60 64#define L310_POWER_CTRL 0xF80 65#define L310_DYNAMIC_CLK_GATING_EN (1 << 1) 66#define L310_STNDBY_MODE_EN (1 << 0) 67 68/* Registers shifts and masks */ 69#define L2X0_CACHE_ID_PART_MASK (0xf << 6) 70#define L2X0_CACHE_ID_PART_L210 (1 << 6) 71#define L2X0_CACHE_ID_PART_L220 (2 << 6) 72#define L2X0_CACHE_ID_PART_L310 (3 << 6) 73#define L2X0_CACHE_ID_RTL_MASK 0x3f 74#define L210_CACHE_ID_RTL_R0P2_02 0x00 75#define L210_CACHE_ID_RTL_R0P1 0x01 76#define L210_CACHE_ID_RTL_R0P2_01 0x02 77#define L210_CACHE_ID_RTL_R0P3 0x03 78#define L210_CACHE_ID_RTL_R0P4 0x0b 79#define L210_CACHE_ID_RTL_R0P5 0x0f 80#define L220_CACHE_ID_RTL_R1P7_01REL0 0x06 81#define L310_CACHE_ID_RTL_R0P0 0x00 82#define L310_CACHE_ID_RTL_R1P0 0x02 83#define L310_CACHE_ID_RTL_R2P0 0x04 84#define L310_CACHE_ID_RTL_R3P0 0x05 85#define L310_CACHE_ID_RTL_R3P1 0x06 86#define L310_CACHE_ID_RTL_R3P1_50REL0 0x07 87#define L310_CACHE_ID_RTL_R3P2 0x08 88#define L310_CACHE_ID_RTL_R3P3 0x09 89 90/* L2C auxiliary control register - bits common to L2C-210/220/310 */ 91#define L2C_AUX_CTRL_WAY_SIZE_SHIFT 17 92#define L2C_AUX_CTRL_WAY_SIZE_MASK (7 << 17) 93#define L2C_AUX_CTRL_WAY_SIZE(n) ((n) << 17) 94#define L2C_AUX_CTRL_EVTMON_ENABLE BIT(20) 95#define L2C_AUX_CTRL_PARITY_ENABLE BIT(21) 96#define L2C_AUX_CTRL_SHARED_OVERRIDE BIT(22) 97/* L2C-210/220 common bits */ 98#define L2X0_AUX_CTRL_DATA_RD_LATENCY_SHIFT 0 99#define L2X0_AUX_CTRL_DATA_RD_LATENCY_MASK (7 << 0) 100#define L2X0_AUX_CTRL_DATA_WR_LATENCY_SHIFT 3 101#define L2X0_AUX_CTRL_DATA_WR_LATENCY_MASK (7 << 3) 102#define L2X0_AUX_CTRL_TAG_LATENCY_SHIFT 6 103#define L2X0_AUX_CTRL_TAG_LATENCY_MASK (7 << 6) 104#define L2X0_AUX_CTRL_DIRTY_LATENCY_SHIFT 9 105#define L2X0_AUX_CTRL_DIRTY_LATENCY_MASK (7 << 9) 106#define L2X0_AUX_CTRL_ASSOC_SHIFT 13 107#define L2X0_AUX_CTRL_ASSOC_MASK (15 << 13) 108/* L2C-210 specific bits */ 109#define L210_AUX_CTRL_WRAP_DISABLE BIT(12) 110#define L210_AUX_CTRL_WA_OVERRIDE BIT(23) 111#define L210_AUX_CTRL_EXCLUSIVE_ABORT BIT(24) 112/* L2C-220 specific bits */ 113#define L220_AUX_CTRL_EXCLUSIVE_CACHE BIT(12) 114#define L220_AUX_CTRL_FWA_SHIFT 23 115#define L220_AUX_CTRL_FWA_MASK (3 << 23) 116#define L220_AUX_CTRL_NS_LOCKDOWN BIT(26) 117#define L220_AUX_CTRL_NS_INT_CTRL BIT(27) 118/* L2C-310 specific bits */ 119#define L310_AUX_CTRL_FULL_LINE_ZERO BIT(0) /* R2P0+ */ 120#define L310_AUX_CTRL_HIGHPRIO_SO_DEV BIT(10) /* R2P0+ */ 121#define L310_AUX_CTRL_STORE_LIMITATION BIT(11) /* R2P0+ */ 122#define L310_AUX_CTRL_EXCLUSIVE_CACHE BIT(12) 123#define L310_AUX_CTRL_ASSOCIATIVITY_16 BIT(16) 124#define L310_AUX_CTRL_CACHE_REPLACE_RR BIT(25) /* R2P0+ */ 125#define L310_AUX_CTRL_NS_LOCKDOWN BIT(26) 126#define L310_AUX_CTRL_NS_INT_CTRL BIT(27) 127#define L310_AUX_CTRL_DATA_PREFETCH BIT(28) 128#define L310_AUX_CTRL_INSTR_PREFETCH BIT(29) 129#define L310_AUX_CTRL_EARLY_BRESP BIT(30) /* R2P0+ */ 130 131#define L310_LATENCY_CTRL_SETUP(n) ((n) << 0) 132#define L310_LATENCY_CTRL_RD(n) ((n) << 4) 133#define L310_LATENCY_CTRL_WR(n) ((n) << 8) 134 135#define L310_ADDR_FILTER_EN 1 136 137#define L310_PREFETCH_CTRL_OFFSET_MASK 0x1f 138#define L310_PREFETCH_CTRL_DBL_LINEFILL_INCR BIT(23) 139#define L310_PREFETCH_CTRL_PREFETCH_DROP BIT(24) 140#define L310_PREFETCH_CTRL_DBL_LINEFILL_WRAP BIT(27) 141#define L310_PREFETCH_CTRL_DATA_PREFETCH BIT(28) 142#define L310_PREFETCH_CTRL_INSTR_PREFETCH BIT(29) 143#define L310_PREFETCH_CTRL_DBL_LINEFILL BIT(30) 144 145#define L2X0_CTRL_EN 1 146 147#define L2X0_WAY_SIZE_SHIFT 3 148 149#ifndef __ASSEMBLY__ 150extern void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask); 151#if defined(CONFIG_CACHE_L2X0) && defined(CONFIG_OF) 152extern int l2x0_of_init(u32 aux_val, u32 aux_mask); 153#else 154static inline int l2x0_of_init(u32 aux_val, u32 aux_mask) 155{ 156 return -ENODEV; 157} 158#endif 159 160struct l2x0_regs { 161 unsigned long phy_base; 162 unsigned long aux_ctrl; 163 /* 164 * Whether the following registers need to be saved/restored 165 * depends on platform 166 */ 167 unsigned long tag_latency; 168 unsigned long data_latency; 169 unsigned long filter_start; 170 unsigned long filter_end; 171 unsigned long prefetch_ctrl; 172 unsigned long pwr_ctrl; 173 unsigned long ctrl; 174 unsigned long aux2_ctrl; 175}; 176 177extern struct l2x0_regs l2x0_saved_regs; 178 179#endif /* __ASSEMBLY__ */ 180 181#endif 182