1/* 2 * Copyright (C) 2011 - 2014 Xilinx 3 * Copyright (C) 2012 National Instruments Corp. 4 * 5 * This software is licensed under the terms of the GNU General Public 6 * License version 2, as published by the Free Software Foundation, and 7 * may be copied, distributed, and modified under those terms. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 */ 14/dts-v1/; 15/include/ "zynq-7000.dtsi" 16 17/ { 18 model = "Zynq ZC706 Development Board"; 19 compatible = "xlnx,zynq-zc706", "xlnx,zynq-7000"; 20 21 aliases { 22 ethernet0 = &gem0; 23 i2c0 = &i2c0; 24 serial0 = &uart1; 25 }; 26 27 memory { 28 device_type = "memory"; 29 reg = <0x0 0x40000000>; 30 }; 31 32 chosen { 33 bootargs = "console=ttyPS0,115200 earlyprintk"; 34 }; 35 36 usb_phy0: phy0 { 37 compatible = "usb-nop-xceiv"; 38 #phy-cells = <0>; 39 }; 40}; 41 42&clkc { 43 ps-clk-frequency = <33333333>; 44}; 45 46&gem0 { 47 status = "okay"; 48 phy-mode = "rgmii-id"; 49 phy-handle = <ðernet_phy>; 50 pinctrl-names = "default"; 51 pinctrl-0 = <&pinctrl_gem0_default>; 52 53 ethernet_phy: ethernet-phy@7 { 54 reg = <7>; 55 }; 56}; 57 58&gpio0 { 59 pinctrl-names = "default"; 60 pinctrl-0 = <&pinctrl_gpio0_default>; 61}; 62 63&i2c0 { 64 status = "okay"; 65 clock-frequency = <400000>; 66 pinctrl-names = "default"; 67 pinctrl-0 = <&pinctrl_i2c0_default>; 68 69 i2cswitch@74 { 70 compatible = "nxp,pca9548"; 71 #address-cells = <1>; 72 #size-cells = <0>; 73 reg = <0x74>; 74 75 i2c@0 { 76 #address-cells = <1>; 77 #size-cells = <0>; 78 reg = <0>; 79 si570: clock-generator@5d { 80 #clock-cells = <0>; 81 compatible = "silabs,si570"; 82 temperature-stability = <50>; 83 reg = <0x5d>; 84 factory-fout = <156250000>; 85 clock-frequency = <148500000>; 86 }; 87 }; 88 89 i2c@2 { 90 #address-cells = <1>; 91 #size-cells = <0>; 92 reg = <2>; 93 eeprom@54 { 94 compatible = "at,24c08"; 95 reg = <0x54>; 96 }; 97 }; 98 99 i2c@3 { 100 #address-cells = <1>; 101 #size-cells = <0>; 102 reg = <3>; 103 gpio@21 { 104 compatible = "ti,tca6416"; 105 reg = <0x21>; 106 gpio-controller; 107 #gpio-cells = <2>; 108 }; 109 }; 110 111 i2c@4 { 112 #address-cells = <1>; 113 #size-cells = <0>; 114 reg = <4>; 115 rtc@51 { 116 compatible = "nxp,pcf8563"; 117 reg = <0x51>; 118 }; 119 }; 120 121 i2c@7 { 122 #address-cells = <1>; 123 #size-cells = <0>; 124 reg = <7>; 125 ucd90120@65 { 126 compatible = "ti,ucd90120"; 127 reg = <0x65>; 128 }; 129 }; 130 }; 131}; 132 133&pinctrl0 { 134 pinctrl_gem0_default: gem0-default { 135 mux { 136 function = "ethernet0"; 137 groups = "ethernet0_0_grp"; 138 }; 139 140 conf { 141 groups = "ethernet0_0_grp"; 142 slew-rate = <0>; 143 io-standard = <4>; 144 }; 145 146 conf-rx { 147 pins = "MIO22", "MIO23", "MIO24", "MIO25", "MIO26", "MIO27"; 148 bias-high-impedance; 149 low-power-disable; 150 }; 151 152 conf-tx { 153 pins = "MIO16", "MIO17", "MIO18", "MIO19", "MIO20", "MIO21"; 154 low-power-enable; 155 bias-disable; 156 }; 157 158 mux-mdio { 159 function = "mdio0"; 160 groups = "mdio0_0_grp"; 161 }; 162 163 conf-mdio { 164 groups = "mdio0_0_grp"; 165 slew-rate = <0>; 166 io-standard = <1>; 167 bias-disable; 168 }; 169 }; 170 171 pinctrl_gpio0_default: gpio0-default { 172 mux { 173 function = "gpio0"; 174 groups = "gpio0_7_grp", "gpio0_46_grp", "gpio0_47_grp"; 175 }; 176 177 conf { 178 groups = "gpio0_7_grp", "gpio0_46_grp", "gpio0_47_grp"; 179 slew-rate = <0>; 180 io-standard = <1>; 181 }; 182 183 conf-pull-up { 184 pins = "MIO46", "MIO47"; 185 bias-pull-up; 186 }; 187 188 conf-pull-none { 189 pins = "MIO7"; 190 bias-disable; 191 }; 192 }; 193 194 pinctrl_i2c0_default: i2c0-default { 195 mux { 196 groups = "i2c0_10_grp"; 197 function = "i2c0"; 198 }; 199 200 conf { 201 groups = "i2c0_10_grp"; 202 bias-pull-up; 203 slew-rate = <0>; 204 io-standard = <1>; 205 }; 206 }; 207 208 pinctrl_sdhci0_default: sdhci0-default { 209 mux { 210 groups = "sdio0_2_grp"; 211 function = "sdio0"; 212 }; 213 214 conf { 215 groups = "sdio0_2_grp"; 216 slew-rate = <0>; 217 io-standard = <1>; 218 bias-disable; 219 }; 220 221 mux-cd { 222 groups = "gpio0_14_grp"; 223 function = "sdio0_cd"; 224 }; 225 226 conf-cd { 227 groups = "gpio0_14_grp"; 228 bias-high-impedance; 229 bias-pull-up; 230 slew-rate = <0>; 231 io-standard = <1>; 232 }; 233 234 mux-wp { 235 groups = "gpio0_15_grp"; 236 function = "sdio0_wp"; 237 }; 238 239 conf-wp { 240 groups = "gpio0_15_grp"; 241 bias-high-impedance; 242 bias-pull-up; 243 slew-rate = <0>; 244 io-standard = <1>; 245 }; 246 }; 247 248 pinctrl_uart1_default: uart1-default { 249 mux { 250 groups = "uart1_10_grp"; 251 function = "uart1"; 252 }; 253 254 conf { 255 groups = "uart1_10_grp"; 256 slew-rate = <0>; 257 io-standard = <1>; 258 }; 259 260 conf-rx { 261 pins = "MIO49"; 262 bias-high-impedance; 263 }; 264 265 conf-tx { 266 pins = "MIO48"; 267 bias-disable; 268 }; 269 }; 270 271 pinctrl_usb0_default: usb0-default { 272 mux { 273 groups = "usb0_0_grp"; 274 function = "usb0"; 275 }; 276 277 conf { 278 groups = "usb0_0_grp"; 279 slew-rate = <0>; 280 io-standard = <1>; 281 }; 282 283 conf-rx { 284 pins = "MIO29", "MIO31", "MIO36"; 285 bias-high-impedance; 286 }; 287 288 conf-tx { 289 pins = "MIO28", "MIO30", "MIO32", "MIO33", "MIO34", 290 "MIO35", "MIO37", "MIO38", "MIO39"; 291 bias-disable; 292 }; 293 }; 294}; 295 296&sdhci0 { 297 status = "okay"; 298 pinctrl-names = "default"; 299 pinctrl-0 = <&pinctrl_sdhci0_default>; 300}; 301 302&uart1 { 303 status = "okay"; 304 pinctrl-names = "default"; 305 pinctrl-0 = <&pinctrl_uart1_default>; 306}; 307 308&usb0 { 309 status = "okay"; 310 dr_mode = "host"; 311 usb-phy = <&usb_phy0>; 312 pinctrl-names = "default"; 313 pinctrl-0 = <&pinctrl_usb0_default>; 314}; 315