1/*
2 * ARM Ltd. Versatile Express
3 *
4 * CoreTile Express A15x2 A7x3
5 * Cortex-A15_A7 MPCore (V2P-CA15_A7)
6 *
7 * HBI-0249A
8 */
9
10/dts-v1/;
11
12/ {
13	model = "V2P-CA15_CA7";
14	arm,hbi = <0x249>;
15	arm,vexpress,site = <0xf>;
16	compatible = "arm,vexpress,v2p-ca15_a7", "arm,vexpress";
17	interrupt-parent = <&gic>;
18	#address-cells = <2>;
19	#size-cells = <2>;
20
21	chosen { };
22
23	aliases {
24		serial0 = &v2m_serial0;
25		serial1 = &v2m_serial1;
26		serial2 = &v2m_serial2;
27		serial3 = &v2m_serial3;
28		i2c0 = &v2m_i2c_dvi;
29		i2c1 = &v2m_i2c_pcie;
30	};
31
32	cpus {
33		#address-cells = <1>;
34		#size-cells = <0>;
35
36		cpu0: cpu@0 {
37			device_type = "cpu";
38			compatible = "arm,cortex-a15";
39			reg = <0>;
40			cci-control-port = <&cci_control1>;
41			cpu-idle-states = <&CLUSTER_SLEEP_BIG>;
42		};
43
44		cpu1: cpu@1 {
45			device_type = "cpu";
46			compatible = "arm,cortex-a15";
47			reg = <1>;
48			cci-control-port = <&cci_control1>;
49			cpu-idle-states = <&CLUSTER_SLEEP_BIG>;
50		};
51
52		cpu2: cpu@2 {
53			device_type = "cpu";
54			compatible = "arm,cortex-a7";
55			reg = <0x100>;
56			cci-control-port = <&cci_control2>;
57			cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>;
58		};
59
60		cpu3: cpu@3 {
61			device_type = "cpu";
62			compatible = "arm,cortex-a7";
63			reg = <0x101>;
64			cci-control-port = <&cci_control2>;
65			cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>;
66		};
67
68		cpu4: cpu@4 {
69			device_type = "cpu";
70			compatible = "arm,cortex-a7";
71			reg = <0x102>;
72			cci-control-port = <&cci_control2>;
73			cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>;
74		};
75
76		idle-states {
77			CLUSTER_SLEEP_BIG: cluster-sleep-big {
78				compatible = "arm,idle-state";
79				local-timer-stop;
80				entry-latency-us = <1000>;
81				exit-latency-us = <700>;
82				min-residency-us = <2000>;
83			};
84
85			CLUSTER_SLEEP_LITTLE: cluster-sleep-little {
86				compatible = "arm,idle-state";
87				local-timer-stop;
88				entry-latency-us = <1000>;
89				exit-latency-us = <500>;
90				min-residency-us = <2500>;
91			};
92		};
93	};
94
95	memory@80000000 {
96		device_type = "memory";
97		reg = <0 0x80000000 0 0x40000000>;
98	};
99
100	wdt@2a490000 {
101		compatible = "arm,sp805", "arm,primecell";
102		reg = <0 0x2a490000 0 0x1000>;
103		interrupts = <0 98 4>;
104		clocks = <&oscclk6a>, <&oscclk6a>;
105		clock-names = "wdogclk", "apb_pclk";
106	};
107
108	hdlcd@2b000000 {
109		compatible = "arm,hdlcd";
110		reg = <0 0x2b000000 0 0x1000>;
111		interrupts = <0 85 4>;
112		clocks = <&oscclk5>;
113		clock-names = "pxlclk";
114	};
115
116	memory-controller@2b0a0000 {
117		compatible = "arm,pl341", "arm,primecell";
118		reg = <0 0x2b0a0000 0 0x1000>;
119		clocks = <&oscclk6a>;
120		clock-names = "apb_pclk";
121	};
122
123	gic: interrupt-controller@2c001000 {
124		compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
125		#interrupt-cells = <3>;
126		#address-cells = <0>;
127		interrupt-controller;
128		reg = <0 0x2c001000 0 0x1000>,
129		      <0 0x2c002000 0 0x1000>,
130		      <0 0x2c004000 0 0x2000>,
131		      <0 0x2c006000 0 0x2000>;
132		interrupts = <1 9 0xf04>;
133	};
134
135	cci@2c090000 {
136		compatible = "arm,cci-400";
137		#address-cells = <1>;
138		#size-cells = <1>;
139		reg = <0 0x2c090000 0 0x1000>;
140		ranges = <0x0 0x0 0x2c090000 0x10000>;
141
142		cci_control1: slave-if@4000 {
143			compatible = "arm,cci-400-ctrl-if";
144			interface-type = "ace";
145			reg = <0x4000 0x1000>;
146		};
147
148		cci_control2: slave-if@5000 {
149			compatible = "arm,cci-400-ctrl-if";
150			interface-type = "ace";
151			reg = <0x5000 0x1000>;
152		};
153	};
154
155	memory-controller@7ffd0000 {
156		compatible = "arm,pl354", "arm,primecell";
157		reg = <0 0x7ffd0000 0 0x1000>;
158		interrupts = <0 86 4>,
159			     <0 87 4>;
160		clocks = <&oscclk6a>;
161		clock-names = "apb_pclk";
162	};
163
164	dma@7ff00000 {
165		compatible = "arm,pl330", "arm,primecell";
166		reg = <0 0x7ff00000 0 0x1000>;
167		interrupts = <0 92 4>,
168			     <0 88 4>,
169			     <0 89 4>,
170			     <0 90 4>,
171			     <0 91 4>;
172		clocks = <&oscclk6a>;
173		clock-names = "apb_pclk";
174	};
175
176        scc@7fff0000 {
177		compatible = "arm,vexpress-scc,v2p-ca15_a7", "arm,vexpress-scc";
178		reg = <0 0x7fff0000 0 0x1000>;
179		interrupts = <0 95 4>;
180        };
181
182	timer {
183		compatible = "arm,armv7-timer";
184		interrupts = <1 13 0xf08>,
185			     <1 14 0xf08>,
186			     <1 11 0xf08>,
187			     <1 10 0xf08>;
188	};
189
190	pmu {
191		compatible = "arm,cortex-a15-pmu";
192		interrupts = <0 68 4>,
193			     <0 69 4>;
194		interrupt-affinity = <&cpu0>, <&cpu1>;
195	};
196
197	oscclk6a: oscclk6a {
198		/* Reference 24MHz clock */
199		compatible = "fixed-clock";
200		#clock-cells = <0>;
201		clock-frequency = <24000000>;
202		clock-output-names = "oscclk6a";
203	};
204
205	dcc {
206		compatible = "arm,vexpress,config-bus";
207		arm,vexpress,config-bridge = <&v2m_sysreg>;
208
209		osc@0 {
210			/* A15 PLL 0 reference clock */
211			compatible = "arm,vexpress-osc";
212			arm,vexpress-sysreg,func = <1 0>;
213			freq-range = <17000000 50000000>;
214			#clock-cells = <0>;
215			clock-output-names = "oscclk0";
216		};
217
218		osc@1 {
219			/* A15 PLL 1 reference clock */
220			compatible = "arm,vexpress-osc";
221			arm,vexpress-sysreg,func = <1 1>;
222			freq-range = <17000000 50000000>;
223			#clock-cells = <0>;
224			clock-output-names = "oscclk1";
225		};
226
227		osc@2 {
228			/* A7 PLL 0 reference clock */
229			compatible = "arm,vexpress-osc";
230			arm,vexpress-sysreg,func = <1 2>;
231			freq-range = <17000000 50000000>;
232			#clock-cells = <0>;
233			clock-output-names = "oscclk2";
234		};
235
236		osc@3 {
237			/* A7 PLL 1 reference clock */
238			compatible = "arm,vexpress-osc";
239			arm,vexpress-sysreg,func = <1 3>;
240			freq-range = <17000000 50000000>;
241			#clock-cells = <0>;
242			clock-output-names = "oscclk3";
243		};
244
245		osc@4 {
246			/* External AXI master clock */
247			compatible = "arm,vexpress-osc";
248			arm,vexpress-sysreg,func = <1 4>;
249			freq-range = <20000000 40000000>;
250			#clock-cells = <0>;
251			clock-output-names = "oscclk4";
252		};
253
254		oscclk5: osc@5 {
255			/* HDLCD PLL reference clock */
256			compatible = "arm,vexpress-osc";
257			arm,vexpress-sysreg,func = <1 5>;
258			freq-range = <23750000 165000000>;
259			#clock-cells = <0>;
260			clock-output-names = "oscclk5";
261		};
262
263		smbclk: osc@6 {
264			/* Static memory controller clock */
265			compatible = "arm,vexpress-osc";
266			arm,vexpress-sysreg,func = <1 6>;
267			freq-range = <20000000 40000000>;
268			#clock-cells = <0>;
269			clock-output-names = "oscclk6";
270		};
271
272		osc@7 {
273			/* SYS PLL reference clock */
274			compatible = "arm,vexpress-osc";
275			arm,vexpress-sysreg,func = <1 7>;
276			freq-range = <17000000 50000000>;
277			#clock-cells = <0>;
278			clock-output-names = "oscclk7";
279		};
280
281		osc@8 {
282			/* DDR2 PLL reference clock */
283			compatible = "arm,vexpress-osc";
284			arm,vexpress-sysreg,func = <1 8>;
285			freq-range = <20000000 50000000>;
286			#clock-cells = <0>;
287			clock-output-names = "oscclk8";
288		};
289
290		volt@0 {
291			/* A15 CPU core voltage */
292			compatible = "arm,vexpress-volt";
293			arm,vexpress-sysreg,func = <2 0>;
294			regulator-name = "A15 Vcore";
295			regulator-min-microvolt = <800000>;
296			regulator-max-microvolt = <1050000>;
297			regulator-always-on;
298			label = "A15 Vcore";
299		};
300
301		volt@1 {
302			/* A7 CPU core voltage */
303			compatible = "arm,vexpress-volt";
304			arm,vexpress-sysreg,func = <2 1>;
305			regulator-name = "A7 Vcore";
306			regulator-min-microvolt = <800000>;
307			regulator-max-microvolt = <1050000>;
308			regulator-always-on;
309			label = "A7 Vcore";
310		};
311
312		amp@0 {
313			/* Total current for the two A15 cores */
314			compatible = "arm,vexpress-amp";
315			arm,vexpress-sysreg,func = <3 0>;
316			label = "A15 Icore";
317		};
318
319		amp@1 {
320			/* Total current for the three A7 cores */
321			compatible = "arm,vexpress-amp";
322			arm,vexpress-sysreg,func = <3 1>;
323			label = "A7 Icore";
324		};
325
326		temp@0 {
327			/* DCC internal temperature */
328			compatible = "arm,vexpress-temp";
329			arm,vexpress-sysreg,func = <4 0>;
330			label = "DCC";
331		};
332
333		power@0 {
334			/* Total power for the two A15 cores */
335			compatible = "arm,vexpress-power";
336			arm,vexpress-sysreg,func = <12 0>;
337			label = "A15 Pcore";
338		};
339
340		power@1 {
341			/* Total power for the three A7 cores */
342			compatible = "arm,vexpress-power";
343			arm,vexpress-sysreg,func = <12 1>;
344			label = "A7 Pcore";
345		};
346
347		energy@0 {
348			/* Total energy for the two A15 cores */
349			compatible = "arm,vexpress-energy";
350			arm,vexpress-sysreg,func = <13 0>, <13 1>;
351			label = "A15 Jcore";
352		};
353
354		energy@2 {
355			/* Total energy for the three A7 cores */
356			compatible = "arm,vexpress-energy";
357			arm,vexpress-sysreg,func = <13 2>, <13 3>;
358			label = "A7 Jcore";
359		};
360	};
361
362	etb@0,20010000 {
363		compatible = "arm,coresight-etb10", "arm,primecell";
364		reg = <0 0x20010000 0 0x1000>;
365
366		clocks = <&oscclk6a>;
367		clock-names = "apb_pclk";
368		port {
369			etb_in_port: endpoint@0 {
370				slave-mode;
371				remote-endpoint = <&replicator_out_port0>;
372			};
373		};
374	};
375
376	tpiu@0,20030000 {
377		compatible = "arm,coresight-tpiu", "arm,primecell";
378		reg = <0 0x20030000 0 0x1000>;
379
380		clocks = <&oscclk6a>;
381		clock-names = "apb_pclk";
382		port {
383			tpiu_in_port: endpoint@0 {
384				slave-mode;
385				remote-endpoint = <&replicator_out_port1>;
386			};
387		};
388	};
389
390	replicator {
391		/* non-configurable replicators don't show up on the
392		 * AMBA bus.  As such no need to add "arm,primecell".
393		 */
394		compatible = "arm,coresight-replicator";
395
396		ports {
397			#address-cells = <1>;
398			#size-cells = <0>;
399
400			/* replicator output ports */
401			port@0 {
402				reg = <0>;
403				replicator_out_port0: endpoint {
404					remote-endpoint = <&etb_in_port>;
405				};
406			};
407
408			port@1 {
409				reg = <1>;
410				replicator_out_port1: endpoint {
411					remote-endpoint = <&tpiu_in_port>;
412				};
413			};
414
415			/* replicator input port */
416			port@2 {
417				reg = <0>;
418				replicator_in_port0: endpoint {
419					slave-mode;
420					remote-endpoint = <&funnel_out_port0>;
421				};
422			};
423		};
424	};
425
426	funnel@0,20040000 {
427		compatible = "arm,coresight-funnel", "arm,primecell";
428		reg = <0 0x20040000 0 0x1000>;
429
430		clocks = <&oscclk6a>;
431		clock-names = "apb_pclk";
432		ports {
433			#address-cells = <1>;
434			#size-cells = <0>;
435
436			/* funnel output port */
437			port@0 {
438				reg = <0>;
439				funnel_out_port0: endpoint {
440					remote-endpoint =
441						<&replicator_in_port0>;
442				};
443			};
444
445			/* funnel input ports */
446			port@1 {
447				reg = <0>;
448				funnel_in_port0: endpoint {
449					slave-mode;
450					remote-endpoint = <&ptm0_out_port>;
451				};
452			};
453
454			port@2 {
455				reg = <1>;
456				funnel_in_port1: endpoint {
457					slave-mode;
458					remote-endpoint = <&ptm1_out_port>;
459				};
460			};
461
462			port@3 {
463				reg = <2>;
464				funnel_in_port2: endpoint {
465					slave-mode;
466					remote-endpoint = <&etm0_out_port>;
467				};
468			};
469
470			/* Input port #3 is for ITM, not supported here */
471
472			port@4 {
473				reg = <4>;
474				funnel_in_port4: endpoint {
475					slave-mode;
476					remote-endpoint = <&etm1_out_port>;
477				};
478			};
479
480			port@5 {
481				reg = <5>;
482				funnel_in_port5: endpoint {
483					slave-mode;
484					remote-endpoint = <&etm2_out_port>;
485				};
486			};
487		};
488	};
489
490	ptm@0,2201c000 {
491		compatible = "arm,coresight-etm3x", "arm,primecell";
492		reg = <0 0x2201c000 0 0x1000>;
493
494		cpu = <&cpu0>;
495		clocks = <&oscclk6a>;
496		clock-names = "apb_pclk";
497		port {
498			ptm0_out_port: endpoint {
499				remote-endpoint = <&funnel_in_port0>;
500			};
501		};
502	};
503
504	ptm@0,2201d000 {
505		compatible = "arm,coresight-etm3x", "arm,primecell";
506		reg = <0 0x2201d000 0 0x1000>;
507
508		cpu = <&cpu1>;
509		clocks = <&oscclk6a>;
510		clock-names = "apb_pclk";
511		port {
512			ptm1_out_port: endpoint {
513				remote-endpoint = <&funnel_in_port1>;
514			};
515		};
516	};
517
518	etm@0,2203c000 {
519		compatible = "arm,coresight-etm3x", "arm,primecell";
520		reg = <0 0x2203c000 0 0x1000>;
521
522		cpu = <&cpu2>;
523		clocks = <&oscclk6a>;
524		clock-names = "apb_pclk";
525		port {
526			etm0_out_port: endpoint {
527				remote-endpoint = <&funnel_in_port2>;
528			};
529		};
530	};
531
532	etm@0,2203d000 {
533		compatible = "arm,coresight-etm3x", "arm,primecell";
534		reg = <0 0x2203d000 0 0x1000>;
535
536		cpu = <&cpu3>;
537		clocks = <&oscclk6a>;
538		clock-names = "apb_pclk";
539		port {
540			etm1_out_port: endpoint {
541				remote-endpoint = <&funnel_in_port4>;
542			};
543		};
544	};
545
546	etm@0,2203e000 {
547		compatible = "arm,coresight-etm3x", "arm,primecell";
548		reg = <0 0x2203e000 0 0x1000>;
549
550		cpu = <&cpu4>;
551		clocks = <&oscclk6a>;
552		clock-names = "apb_pclk";
553		port {
554			etm2_out_port: endpoint {
555				remote-endpoint = <&funnel_in_port5>;
556			};
557		};
558	};
559
560	smb {
561		compatible = "simple-bus";
562
563		#address-cells = <2>;
564		#size-cells = <1>;
565		ranges = <0 0 0 0x08000000 0x04000000>,
566			 <1 0 0 0x14000000 0x04000000>,
567			 <2 0 0 0x18000000 0x04000000>,
568			 <3 0 0 0x1c000000 0x04000000>,
569			 <4 0 0 0x0c000000 0x04000000>,
570			 <5 0 0 0x10000000 0x04000000>;
571
572		#interrupt-cells = <1>;
573		interrupt-map-mask = <0 0 63>;
574		interrupt-map = <0 0  0 &gic 0  0 4>,
575				<0 0  1 &gic 0  1 4>,
576				<0 0  2 &gic 0  2 4>,
577				<0 0  3 &gic 0  3 4>,
578				<0 0  4 &gic 0  4 4>,
579				<0 0  5 &gic 0  5 4>,
580				<0 0  6 &gic 0  6 4>,
581				<0 0  7 &gic 0  7 4>,
582				<0 0  8 &gic 0  8 4>,
583				<0 0  9 &gic 0  9 4>,
584				<0 0 10 &gic 0 10 4>,
585				<0 0 11 &gic 0 11 4>,
586				<0 0 12 &gic 0 12 4>,
587				<0 0 13 &gic 0 13 4>,
588				<0 0 14 &gic 0 14 4>,
589				<0 0 15 &gic 0 15 4>,
590				<0 0 16 &gic 0 16 4>,
591				<0 0 17 &gic 0 17 4>,
592				<0 0 18 &gic 0 18 4>,
593				<0 0 19 &gic 0 19 4>,
594				<0 0 20 &gic 0 20 4>,
595				<0 0 21 &gic 0 21 4>,
596				<0 0 22 &gic 0 22 4>,
597				<0 0 23 &gic 0 23 4>,
598				<0 0 24 &gic 0 24 4>,
599				<0 0 25 &gic 0 25 4>,
600				<0 0 26 &gic 0 26 4>,
601				<0 0 27 &gic 0 27 4>,
602				<0 0 28 &gic 0 28 4>,
603				<0 0 29 &gic 0 29 4>,
604				<0 0 30 &gic 0 30 4>,
605				<0 0 31 &gic 0 31 4>,
606				<0 0 32 &gic 0 32 4>,
607				<0 0 33 &gic 0 33 4>,
608				<0 0 34 &gic 0 34 4>,
609				<0 0 35 &gic 0 35 4>,
610				<0 0 36 &gic 0 36 4>,
611				<0 0 37 &gic 0 37 4>,
612				<0 0 38 &gic 0 38 4>,
613				<0 0 39 &gic 0 39 4>,
614				<0 0 40 &gic 0 40 4>,
615				<0 0 41 &gic 0 41 4>,
616				<0 0 42 &gic 0 42 4>;
617
618		/include/ "vexpress-v2m-rs1.dtsi"
619	};
620};
621