1
2/*
3 * Copyright (C) 2013 STMicroelectronics Limited.
4 * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * publishhed by the Free Software Foundation.
9 */
10#include "st-pincfg.h"
11#include <dt-bindings/interrupt-controller/arm-gic.h>
12/ {
13
14	aliases {
15		gpio0	= &pio0;
16		gpio1	= &pio1;
17		gpio2	= &pio2;
18		gpio3	= &pio3;
19		gpio4	= &pio4;
20		gpio5	= &pio40;
21		gpio6	= &pio5;
22		gpio7	= &pio6;
23		gpio8	= &pio7;
24		gpio9	= &pio8;
25		gpio10	= &pio9;
26		gpio11	= &pio10;
27		gpio12	= &pio11;
28		gpio13	= &pio12;
29		gpio14	= &pio30;
30		gpio15	= &pio31;
31		gpio16	= &pio13;
32		gpio17	= &pio14;
33		gpio18	= &pio15;
34		gpio19	= &pio16;
35		gpio20	= &pio17;
36		gpio21	= &pio18;
37		gpio22	= &pio100;
38		gpio23	= &pio101;
39		gpio24	= &pio102;
40		gpio25	= &pio103;
41		gpio26	= &pio104;
42		gpio27	= &pio105;
43		gpio28	= &pio106;
44		gpio29	= &pio107;
45	};
46
47	soc {
48		pin-controller-sbc {
49			#address-cells	= <1>;
50			#size-cells	= <1>;
51			compatible	= "st,stih416-sbc-pinctrl";
52			st,syscfg	= <&syscfg_sbc>;
53			reg 		= <0xfe61f080 0x4>;
54			reg-names	= "irqmux";
55			interrupts 	= <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
56			interrupt-names	= "irqmux";
57			ranges		= <0 0xfe610000 0x6000>;
58
59			pio0: gpio@fe610000 {
60				gpio-controller;
61				#gpio-cells = <1>;
62				interrupt-controller;
63				#interrupt-cells = <2>;
64				reg		= <0 0x100>;
65				st,bank-name	= "PIO0";
66			};
67			pio1: gpio@fe611000 {
68				gpio-controller;
69				#gpio-cells	= <1>;
70				interrupt-controller;
71				#interrupt-cells = <2>;
72				reg		= <0x1000 0x100>;
73				st,bank-name	= "PIO1";
74			};
75			pio2: gpio@fe612000 {
76				gpio-controller;
77				#gpio-cells	= <1>;
78				interrupt-controller;
79				#interrupt-cells = <2>;
80				reg		= <0x2000 0x100>;
81				st,bank-name	= "PIO2";
82			};
83			pio3: gpio@fe613000 {
84				gpio-controller;
85				#gpio-cells	= <1>;
86				interrupt-controller;
87				#interrupt-cells = <2>;
88				reg		= <0x3000 0x100>;
89				st,bank-name	= "PIO3";
90			};
91			pio4: gpio@fe614000 {
92				gpio-controller;
93				#gpio-cells	= <1>;
94				interrupt-controller;
95				#interrupt-cells = <2>;
96				reg		= <0x4000 0x100>;
97				st,bank-name	= "PIO4";
98			};
99			pio40: gpio@fe615000 {
100				gpio-controller;
101				#gpio-cells	= <1>;
102				interrupt-controller;
103				#interrupt-cells = <2>;
104				reg		= <0x5000 0x100>;
105				st,bank-name	= "PIO40";
106				st,retime-pin-mask = <0x7f>;
107			};
108
109			rc{
110				pinctrl_ir: ir0 {
111					st,pins {
112						ir = <&pio4 0 ALT2 IN>;
113					};
114				};
115			};
116			sbc_serial1 {
117				pinctrl_sbc_serial1: sbc_serial1 {
118					st,pins {
119						tx	= <&pio2 6 ALT3 OUT>;
120						rx	= <&pio2 7 ALT3 IN>;
121					};
122				};
123			};
124
125			keyscan {
126				pinctrl_keyscan: keyscan {
127					st,pins {
128						keyin0 = <&pio0 2 ALT2 IN>;
129						keyin1 = <&pio0 3 ALT2 IN>;
130						keyin2 = <&pio0 4 ALT2 IN>;
131						keyin3 = <&pio2 6 ALT2 IN>;
132
133						keyout0 = <&pio1 6 ALT2 OUT>;
134						keyout1 = <&pio1 7 ALT2 OUT>;
135						keyout2 = <&pio0 6 ALT2 OUT>;
136						keyout3 = <&pio2 7 ALT2 OUT>;
137					};
138				};
139			};
140
141			sbc_i2c0 {
142				pinctrl_sbc_i2c0_default: sbc_i2c0-default {
143					st,pins {
144						sda = <&pio4 6 ALT1 BIDIR>;
145						scl = <&pio4 5 ALT1 BIDIR>;
146					};
147				};
148			};
149
150			usb {
151				pinctrl_usb3: usb3 {
152					st,pins {
153						oc-detect = <&pio40 0 ALT1 IN>;
154						pwr-enable = <&pio40 1 ALT1 OUT>;
155					};
156				};
157			};
158
159			sbc_i2c1 {
160				pinctrl_sbc_i2c1_default: sbc_i2c1-default {
161					st,pins {
162						sda = <&pio3 2 ALT2 BIDIR>;
163						scl = <&pio3 1 ALT2 BIDIR>;
164					};
165				};
166			};
167
168			gmac1 {
169				pinctrl_mii1: mii1 {
170					st,pins {
171						txd0 = <&pio0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
172						txd1 = <&pio0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
173						txd2 = <&pio0 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
174						txd3 = <&pio0 3 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
175						txer = <&pio0 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
176						txen = <&pio0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
177						txclk = <&pio0 6 ALT1 IN NICLK 0 CLK_A>;
178						col =   <&pio0 7 ALT1 IN BYPASS 1000>;
179
180						mdio =  <&pio1 0 ALT1 OUT BYPASS 1500>;
181						mdc =   <&pio1 1 ALT1 OUT NICLK 0 CLK_A>;
182						crs =   <&pio1 2 ALT1 IN BYPASS 1000>;
183						mdint = <&pio1 3 ALT1 IN BYPASS 0>;
184						rxd0 =  <&pio1 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
185						rxd1 =  <&pio1 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
186						rxd2 =  <&pio1 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
187						rxd3 =  <&pio1 7 ALT1 IN SE_NICLK_IO 0 CLK_A>;
188
189						rxdv =  <&pio2 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
190						rx_er = <&pio2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
191						rxclk = <&pio2 2 ALT1 IN NICLK 0 CLK_A>;
192						phyclk = <&pio2 3 ALT1 OUT NICLK 0 CLK_A>;
193					};
194				};
195				pinctrl_rgmii1: rgmii1-0 {
196					st,pins {
197						txd0 =  <&pio0 0 ALT1 OUT DE_IO 500 CLK_A>;
198						txd1 =  <&pio0 1 ALT1 OUT DE_IO 500 CLK_A>;
199						txd2 =  <&pio0 2 ALT1 OUT DE_IO 500 CLK_A>;
200						txd3 =  <&pio0 3 ALT1 OUT DE_IO 500 CLK_A>;
201						txen =  <&pio0 5 ALT1 OUT DE_IO 0   CLK_A>;
202						txclk = <&pio0 6 ALT1 IN  NICLK 0   CLK_A>;
203
204						mdio = <&pio1 0 ALT1 OUT BYPASS 0>;
205						mdc  = <&pio1 1 ALT1 OUT NICLK  0 CLK_A>;
206						rxd0 = <&pio1 4 ALT1 IN DE_IO 500 CLK_A>;
207						rxd1 = <&pio1 5 ALT1 IN DE_IO 500 CLK_A>;
208						rxd2 = <&pio1 6 ALT1 IN DE_IO 500 CLK_A>;
209						rxd3 = <&pio1 7 ALT1 IN DE_IO 500 CLK_A>;
210
211						rxdv   = <&pio2 0 ALT1 IN  DE_IO 500 CLK_A>;
212						rxclk  = <&pio2 2 ALT1 IN  NICLK 0   CLK_A>;
213						phyclk = <&pio2 3 ALT4 OUT NICLK 0   CLK_B>;
214
215						clk125= <&pio3 7 ALT4 IN NICLK 0 CLK_A>;
216					};
217				};
218			};
219		};
220
221		pin-controller-front {
222			#address-cells	= <1>;
223			#size-cells	= <1>;
224			compatible	= "st,stih416-front-pinctrl";
225			st,syscfg	= <&syscfg_front>;
226			reg 		= <0xfee0f080 0x4>;
227			reg-names	= "irqmux";
228			interrupts 	= <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
229			interrupt-names	= "irqmux";
230			ranges		= <0 0xfee00000 0x10000>;
231
232			pio5: gpio@fee00000 {
233				gpio-controller;
234				#gpio-cells	= <1>;
235				interrupt-controller;
236				#interrupt-cells = <2>;
237				reg		= <0 0x100>;
238				st,bank-name	= "PIO5";
239			};
240			pio6: gpio@fee01000 {
241				gpio-controller;
242				#gpio-cells	= <1>;
243				interrupt-controller;
244				#interrupt-cells = <2>;
245				reg		= <0x1000 0x100>;
246				st,bank-name	= "PIO6";
247			};
248			pio7: gpio@fee02000 {
249				gpio-controller;
250				#gpio-cells	= <1>;
251				interrupt-controller;
252				#interrupt-cells = <2>;
253				reg		= <0x2000 0x100>;
254				st,bank-name	= "PIO7";
255			};
256			pio8: gpio@fee03000 {
257				gpio-controller;
258				#gpio-cells	= <1>;
259				interrupt-controller;
260				#interrupt-cells = <2>;
261				reg		= <0x3000 0x100>;
262				st,bank-name	= "PIO8";
263			};
264			pio9: gpio@fee04000 {
265				gpio-controller;
266				#gpio-cells	= <1>;
267				interrupt-controller;
268				#interrupt-cells = <2>;
269				reg		= <0x4000 0x100>;
270				st,bank-name	= "PIO9";
271			};
272			pio10: gpio@fee05000 {
273				gpio-controller;
274				#gpio-cells	= <1>;
275				interrupt-controller;
276				#interrupt-cells = <2>;
277				reg		= <0x5000 0x100>;
278				st,bank-name	= "PIO10";
279			};
280			pio11: gpio@fee06000 {
281				gpio-controller;
282				#gpio-cells	= <1>;
283				interrupt-controller;
284				#interrupt-cells = <2>;
285				reg		= <0x6000 0x100>;
286				st,bank-name	= "PIO11";
287			};
288			pio12: gpio@fee07000 {
289				gpio-controller;
290				#gpio-cells	= <1>;
291				interrupt-controller;
292				#interrupt-cells = <2>;
293				reg		= <0x7000 0x100>;
294				st,bank-name	= "PIO12";
295			};
296			pio30: gpio@fee08000 {
297				gpio-controller;
298				#gpio-cells	= <1>;
299				interrupt-controller;
300				#interrupt-cells = <2>;
301				reg		= <0x8000 0x100>;
302				st,bank-name	= "PIO30";
303			};
304			pio31: gpio@fee09000 {
305				gpio-controller;
306				#gpio-cells	= <1>;
307				interrupt-controller;
308				#interrupt-cells = <2>;
309				reg		= <0x9000 0x100>;
310				st,bank-name	= "PIO31";
311			};
312
313			serial2-oe {
314				pinctrl_serial2_oe: serial2-1 {
315					st,pins {
316						output-enable	= <&pio11 3 ALT2 OUT>;
317					};
318				};
319			};
320
321			i2c0 {
322				pinctrl_i2c0_default: i2c0-default {
323					st,pins {
324						sda = <&pio9 3 ALT1 BIDIR>;
325						scl = <&pio9 2 ALT1 BIDIR>;
326					};
327				};
328			};
329
330			usb {
331				pinctrl_usb0: usb0 {
332					st,pins {
333						oc-detect = <&pio9 4 ALT1 IN>;
334						pwr-enable = <&pio9 5 ALT1 OUT>;
335					};
336				};
337			};
338
339
340			i2c1 {
341				pinctrl_i2c1_default: i2c1-default {
342					st,pins {
343						sda = <&pio12 1 ALT1 BIDIR>;
344						scl = <&pio12 0 ALT1 BIDIR>;
345					};
346				};
347			};
348
349			fsm {
350				pinctrl_fsm: fsm {
351					st,pins {
352						spi-fsm-clk  = <&pio12 2 ALT1 OUT>;
353						spi-fsm-cs   = <&pio12 3 ALT1 OUT>;
354						spi-fsm-mosi = <&pio12 4 ALT1 OUT>;
355						spi-fsm-miso = <&pio12 5 ALT1 IN>;
356						spi-fsm-hol  = <&pio12 6 ALT1 OUT>;
357						spi-fsm-wp   = <&pio12 7 ALT1 OUT>;
358					};
359				};
360			};
361		};
362
363		pin-controller-rear {
364			#address-cells	= <1>;
365			#size-cells	= <1>;
366			compatible	= "st,stih416-rear-pinctrl";
367			st,syscfg	= <&syscfg_rear>;
368			reg 		= <0xfe82f080 0x4>;
369			reg-names	= "irqmux";
370			interrupts 	= <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
371			interrupt-names	= "irqmux";
372			ranges 		= <0 0xfe820000 0x6000>;
373
374			pio13: gpio@fe820000 {
375				gpio-controller;
376				#gpio-cells	= <1>;
377				interrupt-controller;
378				#interrupt-cells = <2>;
379				reg		= <0 0x100>;
380				st,bank-name	= "PIO13";
381			};
382			pio14: gpio@fe821000 {
383				gpio-controller;
384				#gpio-cells	= <1>;
385				interrupt-controller;
386				#interrupt-cells = <2>;
387				reg		= <0x1000 0x100>;
388				st,bank-name	= "PIO14";
389			};
390			pio15: gpio@fe822000 {
391				gpio-controller;
392				#gpio-cells	= <1>;
393				interrupt-controller;
394				#interrupt-cells = <2>;
395				reg		= <0x2000 0x100>;
396				st,bank-name	= "PIO15";
397			};
398			pio16: gpio@fe823000 {
399				gpio-controller;
400				#gpio-cells	= <1>;
401				interrupt-controller;
402				#interrupt-cells = <2>;
403				reg		= <0x3000 0x100>;
404				st,bank-name	= "PIO16";
405			};
406			pio17: gpio@fe824000 {
407				gpio-controller;
408				#gpio-cells	= <1>;
409				interrupt-controller;
410				#interrupt-cells = <2>;
411				reg		= <0x4000 0x100>;
412				st,bank-name	= "PIO17";
413			};
414			pio18: gpio@fe825000 {
415				gpio-controller;
416				#gpio-cells	= <1>;
417				interrupt-controller;
418				#interrupt-cells = <2>;
419				reg		= <0x5000 0x100>;
420				st,bank-name	= "PIO18";
421				st,retime-pin-mask = <0xf>;
422			};
423
424			serial2 {
425				pinctrl_serial2: serial2-0 {
426					st,pins {
427						tx	= <&pio17 4 ALT2 OUT>;
428						rx	= <&pio17 5 ALT2 IN>;
429					};
430				};
431			};
432
433			gmac0 {
434				pinctrl_mii0: mii0 {
435					st,pins {
436						mdint = <&pio13 6 ALT2 IN  BYPASS      0>;
437						txen =  <&pio13 7 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
438						txd0 =  <&pio14 0 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
439						txd1 =  <&pio14 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
440						txd2 =  <&pio14 2 ALT2 OUT SE_NICLK_IO 0 CLK_B>;
441						txd3 =  <&pio14 3 ALT2 OUT SE_NICLK_IO 0 CLK_B>;
442
443						txclk = <&pio15 0 ALT2 IN  NICLK       0 CLK_A>;
444						txer =  <&pio15 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
445						crs = <&pio15 2 ALT2 IN  BYPASS 1000>;
446						col = <&pio15 3 ALT2 IN  BYPASS 1000>;
447						mdio= <&pio15 4 ALT2 OUT BYPASS 1500>;
448						mdc = <&pio15 5 ALT2 OUT NICLK  0    CLK_B>;
449
450						rxd0 =  <&pio16 0 ALT2 IN SE_NICLK_IO 0 CLK_A>;
451						rxd1 =  <&pio16 1 ALT2 IN SE_NICLK_IO 0 CLK_A>;
452						rxd2 =  <&pio16 2 ALT2 IN SE_NICLK_IO 0 CLK_A>;
453						rxd3 =  <&pio16 3 ALT2 IN SE_NICLK_IO 0 CLK_A>;
454						rxdv =  <&pio15 6 ALT2 IN SE_NICLK_IO 0 CLK_A>;
455						rx_er = <&pio15 7 ALT2 IN SE_NICLK_IO 0 CLK_A>;
456						rxclk = <&pio17 0 ALT2 IN NICLK 0 CLK_A>;
457						phyclk = <&pio13 5 ALT2 OUT NICLK 0 CLK_B>;
458					};
459				};
460
461				pinctrl_gmii0: gmii0 {
462					st,pins {
463						};
464				};
465				pinctrl_rgmii0: rgmii0 {
466					st,pins {
467						 phyclk = <&pio13  5 ALT4 OUT NICLK 0 CLK_B>;
468						 txen = <&pio13 7 ALT2 OUT DE_IO 0 CLK_A>;
469						 txd0  = <&pio14 0 ALT2 OUT DE_IO 500 CLK_A>;
470						 txd1  = <&pio14 1 ALT2 OUT DE_IO 500 CLK_A>;
471						 txd2  = <&pio14 2 ALT2 OUT DE_IO 500 CLK_B>;
472						 txd3  = <&pio14 3 ALT2 OUT DE_IO 500 CLK_B>;
473						 txclk = <&pio15 0 ALT2 IN NICLK 0 CLK_A>;
474
475						 mdio = <&pio15 4 ALT2 OUT BYPASS 0>;
476						 mdc = <&pio15 5 ALT2 OUT NICLK 0 CLK_B>;
477
478						 rxdv = <&pio15 6 ALT2 IN DE_IO 500 CLK_A>;
479						 rxd0 =<&pio16 0 ALT2 IN DE_IO	500 CLK_A>;
480						 rxd1 =<&pio16 1 ALT2 IN DE_IO	500 CLK_A>;
481						 rxd2 =<&pio16 2 ALT2 IN DE_IO	500 CLK_A>;
482						 rxd3  =<&pio16 3 ALT2 IN DE_IO 500 CLK_A>;
483						 rxclk =<&pio17 0 ALT2 IN NICLK 0 CLK_A>;
484
485						 clk125=<&pio17 6 ALT1 IN NICLK 0 CLK_A>;
486					};
487				};
488			};
489
490			mmc0 {
491				pinctrl_mmc0: mmc0 {
492					st,pins {
493						mmcclk  = <&pio13 4 ALT4 BIDIR_PU NICLK 0 CLK_B>;
494						data0   = <&pio14 4 ALT4 BIDIR_PU BYPASS 0>;
495						data1   = <&pio14 5 ALT4 BIDIR_PU BYPASS 0>;
496						data2   = <&pio14 6 ALT4 BIDIR_PU BYPASS 0>;
497						data3   = <&pio14 7 ALT4 BIDIR_PU BYPASS 0>;
498						cmd     = <&pio15 1 ALT4 BIDIR_PU BYPASS 0>;
499						wp      = <&pio15 3 ALT4 IN>;
500						data4   = <&pio16 4 ALT4 BIDIR_PU BYPASS 0>;
501						data5   = <&pio16 5 ALT4 BIDIR_PU BYPASS 0>;
502						data6   = <&pio16 6 ALT4 BIDIR_PU BYPASS 0>;
503						data7   = <&pio16 7 ALT4 BIDIR_PU BYPASS 0>;
504						pwr     = <&pio17 1 ALT4 OUT>;
505						cd      = <&pio17 2 ALT4 IN>;
506						led     = <&pio17 3 ALT4 OUT>;
507					};
508				};
509			};
510			mmc1 {
511				pinctrl_mmc1: mmc1 {
512					st,pins {
513						mmcclk  = <&pio15 0 ALT3 BIDIR_PU NICLK 0 CLK_B>;
514						data0   = <&pio13 7 ALT3 BIDIR_PU BYPASS 0>;
515						data1   = <&pio14 1 ALT3 BIDIR_PU BYPASS 0>;
516						data2   = <&pio14 2 ALT3 BIDIR_PU BYPASS 0>;
517						data3   = <&pio14 3 ALT3 BIDIR_PU BYPASS 0>;
518						cmd     = <&pio15 4 ALT3 BIDIR_PU BYPASS 0>;
519						data4   = <&pio15 6 ALT3 BIDIR_PU BYPASS 0>;
520						data5   = <&pio15 7 ALT3 BIDIR_PU BYPASS 0>;
521						data6   = <&pio16 0 ALT3 BIDIR_PU BYPASS 0>;
522						data7   = <&pio16 1 ALT3 BIDIR_PU BYPASS 0>;
523						pwr     = <&pio16 2 ALT3 OUT>;
524						nreset  = <&pio13 6 ALT3 OUT>;
525					};
526				};
527			};
528
529			usb {
530				pinctrl_usb1: usb1 {
531					st,pins {
532						oc-detect = <&pio18 0 ALT1 IN>;
533						pwr-enable = <&pio18 1 ALT1 OUT>;
534					};
535				};
536				pinctrl_usb2: usb2 {
537					st,pins {
538						oc-detect = <&pio18 2 ALT1 IN>;
539						pwr-enable = <&pio18 3 ALT1 OUT>;
540					};
541				};
542			};
543		};
544
545		pin-controller-fvdp-fe {
546			#address-cells	= <1>;
547			#size-cells	= <1>;
548			compatible	= "st,stih416-fvdp-fe-pinctrl";
549			st,syscfg	= <&syscfg_fvdp_fe>;
550			reg 		= <0xfd6bf080 0x4>;
551			reg-names	= "irqmux";
552			interrupts 	= <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
553			interrupt-names	= "irqmux";
554			ranges		= <0 0xfd6b0000 0x3000>;
555
556			pio100: gpio@fd6b0000 {
557				gpio-controller;
558				#gpio-cells	= <1>;
559				interrupt-controller;
560				#interrupt-cells = <2>;
561				reg		= <0 0x100>;
562				st,bank-name	= "PIO100";
563			};
564			pio101: gpio@fd6b1000 {
565				gpio-controller;
566				#gpio-cells	= <1>;
567				interrupt-controller;
568				#interrupt-cells = <2>;
569				reg		= <0x1000 0x100>;
570				st,bank-name	= "PIO101";
571			};
572			pio102: gpio@fd6b2000 {
573				gpio-controller;
574				#gpio-cells	= <1>;
575				interrupt-controller;
576				#interrupt-cells = <2>;
577				reg		= <0x2000 0x100>;
578				st,bank-name	= "PIO102";
579			};
580		};
581
582		pin-controller-fvdp-lite {
583			#address-cells	= <1>;
584			#size-cells	= <1>;
585			compatible	= "st,stih416-fvdp-lite-pinctrl";
586			st,syscfg		= <&syscfg_fvdp_lite>;
587			reg 		= <0xfd33f080 0x4>;
588			reg-names	= "irqmux";
589			interrupts 	= <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
590			interrupt-names	= "irqmux";
591			ranges			= <0 0xfd330000 0x5000>;
592
593			pio103: gpio@fd330000 {
594				gpio-controller;
595				#gpio-cells	= <1>;
596				interrupt-controller;
597				#interrupt-cells = <2>;
598				reg		= <0 0x100>;
599				st,bank-name	= "PIO103";
600			};
601			pio104: gpio@fd331000 {
602				gpio-controller;
603				#gpio-cells	= <1>;
604				interrupt-controller;
605				#interrupt-cells = <2>;
606				reg		= <0x1000 0x100>;
607				st,bank-name	= "PIO104";
608			};
609			pio105: gpio@fd332000 {
610				gpio-controller;
611				#gpio-cells	= <1>;
612				interrupt-controller;
613				#interrupt-cells = <2>;
614				reg		= <0x2000 0x100>;
615				st,bank-name	= "PIO105";
616			};
617			pio106: gpio@fd333000 {
618				gpio-controller;
619				#gpio-cells	= <1>;
620				interrupt-controller;
621				#interrupt-cells = <2>;
622				reg		= <0x3000 0x100>;
623				st,bank-name	= "PIO106";
624			};
625
626			pio107: gpio@fd334000 {
627				gpio-controller;
628				#gpio-cells	= <1>;
629				interrupt-controller;
630				#interrupt-cells = <2>;
631				reg		= <0x4000 0x100>;
632				st,bank-name	= "PIO107";
633				st,retime-pin-mask = <0xf>;
634			};
635		};
636	};
637};
638