1/* 2 * Device Tree Source for Renesas r8a7779 3 * 4 * Copyright (C) 2013 Renesas Solutions Corp. 5 * Copyright (C) 2013 Simon Horman 6 * 7 * This file is licensed under the terms of the GNU General Public License 8 * version 2. This program is licensed "as is" without any warranty of any 9 * kind, whether express or implied. 10 */ 11 12/include/ "skeleton.dtsi" 13 14#include <dt-bindings/clock/r8a7779-clock.h> 15#include <dt-bindings/interrupt-controller/arm-gic.h> 16#include <dt-bindings/interrupt-controller/irq.h> 17 18/ { 19 compatible = "renesas,r8a7779"; 20 interrupt-parent = <&gic>; 21 22 cpus { 23 #address-cells = <1>; 24 #size-cells = <0>; 25 26 cpu@0 { 27 device_type = "cpu"; 28 compatible = "arm,cortex-a9"; 29 reg = <0>; 30 clock-frequency = <1000000000>; 31 }; 32 cpu@1 { 33 device_type = "cpu"; 34 compatible = "arm,cortex-a9"; 35 reg = <1>; 36 clock-frequency = <1000000000>; 37 }; 38 cpu@2 { 39 device_type = "cpu"; 40 compatible = "arm,cortex-a9"; 41 reg = <2>; 42 clock-frequency = <1000000000>; 43 }; 44 cpu@3 { 45 device_type = "cpu"; 46 compatible = "arm,cortex-a9"; 47 reg = <3>; 48 clock-frequency = <1000000000>; 49 }; 50 }; 51 52 aliases { 53 spi0 = &hspi0; 54 spi1 = &hspi1; 55 spi2 = &hspi2; 56 }; 57 58 gic: interrupt-controller@f0001000 { 59 compatible = "arm,cortex-a9-gic"; 60 #interrupt-cells = <3>; 61 interrupt-controller; 62 reg = <0xf0001000 0x1000>, 63 <0xf0000100 0x100>; 64 }; 65 66 timer@f0000600 { 67 compatible = "arm,cortex-a9-twd-timer"; 68 reg = <0xf0000600 0x20>; 69 interrupts = <GIC_PPI 13 70 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 71 clocks = <&cpg_clocks R8A7779_CLK_ZS>; 72 }; 73 74 gpio0: gpio@ffc40000 { 75 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; 76 reg = <0xffc40000 0x2c>; 77 interrupts = <0 141 IRQ_TYPE_LEVEL_HIGH>; 78 #gpio-cells = <2>; 79 gpio-controller; 80 gpio-ranges = <&pfc 0 0 32>; 81 #interrupt-cells = <2>; 82 interrupt-controller; 83 }; 84 85 gpio1: gpio@ffc41000 { 86 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; 87 reg = <0xffc41000 0x2c>; 88 interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>; 89 #gpio-cells = <2>; 90 gpio-controller; 91 gpio-ranges = <&pfc 0 32 32>; 92 #interrupt-cells = <2>; 93 interrupt-controller; 94 }; 95 96 gpio2: gpio@ffc42000 { 97 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; 98 reg = <0xffc42000 0x2c>; 99 interrupts = <0 143 IRQ_TYPE_LEVEL_HIGH>; 100 #gpio-cells = <2>; 101 gpio-controller; 102 gpio-ranges = <&pfc 0 64 32>; 103 #interrupt-cells = <2>; 104 interrupt-controller; 105 }; 106 107 gpio3: gpio@ffc43000 { 108 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; 109 reg = <0xffc43000 0x2c>; 110 interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>; 111 #gpio-cells = <2>; 112 gpio-controller; 113 gpio-ranges = <&pfc 0 96 32>; 114 #interrupt-cells = <2>; 115 interrupt-controller; 116 }; 117 118 gpio4: gpio@ffc44000 { 119 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; 120 reg = <0xffc44000 0x2c>; 121 interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>; 122 #gpio-cells = <2>; 123 gpio-controller; 124 gpio-ranges = <&pfc 0 128 32>; 125 #interrupt-cells = <2>; 126 interrupt-controller; 127 }; 128 129 gpio5: gpio@ffc45000 { 130 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; 131 reg = <0xffc45000 0x2c>; 132 interrupts = <0 146 IRQ_TYPE_LEVEL_HIGH>; 133 #gpio-cells = <2>; 134 gpio-controller; 135 gpio-ranges = <&pfc 0 160 32>; 136 #interrupt-cells = <2>; 137 interrupt-controller; 138 }; 139 140 gpio6: gpio@ffc46000 { 141 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; 142 reg = <0xffc46000 0x2c>; 143 interrupts = <0 147 IRQ_TYPE_LEVEL_HIGH>; 144 #gpio-cells = <2>; 145 gpio-controller; 146 gpio-ranges = <&pfc 0 192 9>; 147 #interrupt-cells = <2>; 148 interrupt-controller; 149 }; 150 151 irqpin0: irqpin@fe780010 { 152 compatible = "renesas,intc-irqpin-r8a7779", "renesas,intc-irqpin"; 153 #interrupt-cells = <2>; 154 status = "disabled"; 155 interrupt-controller; 156 reg = <0xfe78001c 4>, 157 <0xfe780010 4>, 158 <0xfe780024 4>, 159 <0xfe780044 4>, 160 <0xfe780064 4>; 161 interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH 162 0 28 IRQ_TYPE_LEVEL_HIGH 163 0 29 IRQ_TYPE_LEVEL_HIGH 164 0 30 IRQ_TYPE_LEVEL_HIGH>; 165 sense-bitfield-width = <2>; 166 }; 167 168 i2c0: i2c@ffc70000 { 169 #address-cells = <1>; 170 #size-cells = <0>; 171 compatible = "renesas,i2c-r8a7779"; 172 reg = <0xffc70000 0x1000>; 173 interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>; 174 clocks = <&mstp0_clks R8A7779_CLK_I2C0>; 175 status = "disabled"; 176 }; 177 178 i2c1: i2c@ffc71000 { 179 #address-cells = <1>; 180 #size-cells = <0>; 181 compatible = "renesas,i2c-r8a7779"; 182 reg = <0xffc71000 0x1000>; 183 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>; 184 clocks = <&mstp0_clks R8A7779_CLK_I2C1>; 185 status = "disabled"; 186 }; 187 188 i2c2: i2c@ffc72000 { 189 #address-cells = <1>; 190 #size-cells = <0>; 191 compatible = "renesas,i2c-r8a7779"; 192 reg = <0xffc72000 0x1000>; 193 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>; 194 clocks = <&mstp0_clks R8A7779_CLK_I2C2>; 195 status = "disabled"; 196 }; 197 198 i2c3: i2c@ffc73000 { 199 #address-cells = <1>; 200 #size-cells = <0>; 201 compatible = "renesas,i2c-r8a7779"; 202 reg = <0xffc73000 0x1000>; 203 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>; 204 clocks = <&mstp0_clks R8A7779_CLK_I2C3>; 205 status = "disabled"; 206 }; 207 208 scif0: serial@ffe40000 { 209 compatible = "renesas,scif-r8a7779", "renesas,scif"; 210 reg = <0xffe40000 0x100>; 211 interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH>; 212 clocks = <&mstp0_clks R8A7779_CLK_SCIF0>; 213 clock-names = "sci_ick"; 214 status = "disabled"; 215 }; 216 217 scif1: serial@ffe41000 { 218 compatible = "renesas,scif-r8a7779", "renesas,scif"; 219 reg = <0xffe41000 0x100>; 220 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>; 221 clocks = <&mstp0_clks R8A7779_CLK_SCIF1>; 222 clock-names = "sci_ick"; 223 status = "disabled"; 224 }; 225 226 scif2: serial@ffe42000 { 227 compatible = "renesas,scif-r8a7779", "renesas,scif"; 228 reg = <0xffe42000 0x100>; 229 interrupts = <0 90 IRQ_TYPE_LEVEL_HIGH>; 230 clocks = <&mstp0_clks R8A7779_CLK_SCIF2>; 231 clock-names = "sci_ick"; 232 status = "disabled"; 233 }; 234 235 scif3: serial@ffe43000 { 236 compatible = "renesas,scif-r8a7779", "renesas,scif"; 237 reg = <0xffe43000 0x100>; 238 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>; 239 clocks = <&mstp0_clks R8A7779_CLK_SCIF3>; 240 clock-names = "sci_ick"; 241 status = "disabled"; 242 }; 243 244 scif4: serial@ffe44000 { 245 compatible = "renesas,scif-r8a7779", "renesas,scif"; 246 reg = <0xffe44000 0x100>; 247 interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>; 248 clocks = <&mstp0_clks R8A7779_CLK_SCIF4>; 249 clock-names = "sci_ick"; 250 status = "disabled"; 251 }; 252 253 scif5: serial@ffe45000 { 254 compatible = "renesas,scif-r8a7779", "renesas,scif"; 255 reg = <0xffe45000 0x100>; 256 interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>; 257 clocks = <&mstp0_clks R8A7779_CLK_SCIF5>; 258 clock-names = "sci_ick"; 259 status = "disabled"; 260 }; 261 262 pfc: pfc@fffc0000 { 263 compatible = "renesas,pfc-r8a7779"; 264 reg = <0xfffc0000 0x23c>; 265 }; 266 267 thermal@ffc48000 { 268 compatible = "renesas,thermal-r8a7779", "renesas,rcar-thermal"; 269 reg = <0xffc48000 0x38>; 270 }; 271 272 tmu0: timer@ffd80000 { 273 compatible = "renesas,tmu-r8a7779", "renesas,tmu"; 274 reg = <0xffd80000 0x30>; 275 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>, 276 <0 33 IRQ_TYPE_LEVEL_HIGH>, 277 <0 34 IRQ_TYPE_LEVEL_HIGH>; 278 clocks = <&mstp0_clks R8A7779_CLK_TMU0>; 279 clock-names = "fck"; 280 281 #renesas,channels = <3>; 282 283 status = "disabled"; 284 }; 285 286 tmu1: timer@ffd81000 { 287 compatible = "renesas,tmu-r8a7779", "renesas,tmu"; 288 reg = <0xffd81000 0x30>; 289 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>, 290 <0 37 IRQ_TYPE_LEVEL_HIGH>, 291 <0 38 IRQ_TYPE_LEVEL_HIGH>; 292 clocks = <&mstp0_clks R8A7779_CLK_TMU1>; 293 clock-names = "fck"; 294 295 #renesas,channels = <3>; 296 297 status = "disabled"; 298 }; 299 300 tmu2: timer@ffd82000 { 301 compatible = "renesas,tmu-r8a7779", "renesas,tmu"; 302 reg = <0xffd82000 0x30>; 303 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>, 304 <0 41 IRQ_TYPE_LEVEL_HIGH>, 305 <0 42 IRQ_TYPE_LEVEL_HIGH>; 306 clocks = <&mstp0_clks R8A7779_CLK_TMU2>; 307 clock-names = "fck"; 308 309 #renesas,channels = <3>; 310 311 status = "disabled"; 312 }; 313 314 sata: sata@fc600000 { 315 compatible = "renesas,sata-r8a7779", "renesas,rcar-sata"; 316 reg = <0xfc600000 0x2000>; 317 interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>; 318 clocks = <&mstp1_clks R8A7779_CLK_SATA>; 319 }; 320 321 sdhi0: sd@ffe4c000 { 322 compatible = "renesas,sdhi-r8a7779"; 323 reg = <0xffe4c000 0x100>; 324 interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>; 325 clocks = <&mstp3_clks R8A7779_CLK_SDHI0>; 326 status = "disabled"; 327 }; 328 329 sdhi1: sd@ffe4d000 { 330 compatible = "renesas,sdhi-r8a7779"; 331 reg = <0xffe4d000 0x100>; 332 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>; 333 clocks = <&mstp3_clks R8A7779_CLK_SDHI1>; 334 status = "disabled"; 335 }; 336 337 sdhi2: sd@ffe4e000 { 338 compatible = "renesas,sdhi-r8a7779"; 339 reg = <0xffe4e000 0x100>; 340 interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>; 341 clocks = <&mstp3_clks R8A7779_CLK_SDHI2>; 342 status = "disabled"; 343 }; 344 345 sdhi3: sd@ffe4f000 { 346 compatible = "renesas,sdhi-r8a7779"; 347 reg = <0xffe4f000 0x100>; 348 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; 349 clocks = <&mstp3_clks R8A7779_CLK_SDHI3>; 350 status = "disabled"; 351 }; 352 353 hspi0: spi@fffc7000 { 354 compatible = "renesas,hspi-r8a7779", "renesas,hspi"; 355 reg = <0xfffc7000 0x18>; 356 interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>; 357 #address-cells = <1>; 358 #size-cells = <0>; 359 clocks = <&mstp0_clks R8A7779_CLK_HSPI>; 360 status = "disabled"; 361 }; 362 363 hspi1: spi@fffc8000 { 364 compatible = "renesas,hspi-r8a7779", "renesas,hspi"; 365 reg = <0xfffc8000 0x18>; 366 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>; 367 #address-cells = <1>; 368 #size-cells = <0>; 369 clocks = <&mstp0_clks R8A7779_CLK_HSPI>; 370 status = "disabled"; 371 }; 372 373 hspi2: spi@fffc6000 { 374 compatible = "renesas,hspi-r8a7779", "renesas,hspi"; 375 reg = <0xfffc6000 0x18>; 376 interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>; 377 #address-cells = <1>; 378 #size-cells = <0>; 379 clocks = <&mstp0_clks R8A7779_CLK_HSPI>; 380 status = "disabled"; 381 }; 382 383 du: display@fff80000 { 384 compatible = "renesas,du-r8a7779"; 385 reg = <0 0xfff80000 0 0x40000>; 386 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>; 387 clocks = <&mstp1_clks R8A7779_CLK_DU>; 388 status = "disabled"; 389 390 ports { 391 #address-cells = <1>; 392 #size-cells = <0>; 393 394 port@0 { 395 reg = <0>; 396 du_out_rgb0: endpoint { 397 }; 398 }; 399 port@1 { 400 reg = <1>; 401 du_out_rgb1: endpoint { 402 }; 403 }; 404 }; 405 }; 406 407 clocks { 408 #address-cells = <1>; 409 #size-cells = <1>; 410 ranges; 411 412 /* External root clock */ 413 extal_clk: extal_clk { 414 compatible = "fixed-clock"; 415 #clock-cells = <0>; 416 /* This value must be overriden by the board. */ 417 clock-frequency = <0>; 418 clock-output-names = "extal"; 419 }; 420 421 /* Special CPG clocks */ 422 cpg_clocks: clocks@ffc80000 { 423 compatible = "renesas,r8a7779-cpg-clocks"; 424 reg = <0xffc80000 0x30>; 425 clocks = <&extal_clk>; 426 #clock-cells = <1>; 427 clock-output-names = "plla", "z", "zs", "s", 428 "s1", "p", "b", "out"; 429 }; 430 431 /* Fixed factor clocks */ 432 i_clk: i_clk { 433 compatible = "fixed-factor-clock"; 434 clocks = <&cpg_clocks R8A7779_CLK_PLLA>; 435 #clock-cells = <0>; 436 clock-div = <2>; 437 clock-mult = <1>; 438 clock-output-names = "i"; 439 }; 440 s3_clk: s3_clk { 441 compatible = "fixed-factor-clock"; 442 clocks = <&cpg_clocks R8A7779_CLK_PLLA>; 443 #clock-cells = <0>; 444 clock-div = <8>; 445 clock-mult = <1>; 446 clock-output-names = "s3"; 447 }; 448 s4_clk: s4_clk { 449 compatible = "fixed-factor-clock"; 450 clocks = <&cpg_clocks R8A7779_CLK_PLLA>; 451 #clock-cells = <0>; 452 clock-div = <16>; 453 clock-mult = <1>; 454 clock-output-names = "s4"; 455 }; 456 g_clk: g_clk { 457 compatible = "fixed-factor-clock"; 458 clocks = <&cpg_clocks R8A7779_CLK_PLLA>; 459 #clock-cells = <0>; 460 clock-div = <24>; 461 clock-mult = <1>; 462 clock-output-names = "g"; 463 }; 464 465 /* Gate clocks */ 466 mstp0_clks: clocks@ffc80030 { 467 compatible = "renesas,r8a7779-mstp-clocks", 468 "renesas,cpg-mstp-clocks"; 469 reg = <0xffc80030 4>; 470 clocks = <&cpg_clocks R8A7779_CLK_S>, 471 <&cpg_clocks R8A7779_CLK_P>, 472 <&cpg_clocks R8A7779_CLK_P>, 473 <&cpg_clocks R8A7779_CLK_P>, 474 <&cpg_clocks R8A7779_CLK_S>, 475 <&cpg_clocks R8A7779_CLK_S>, 476 <&cpg_clocks R8A7779_CLK_P>, 477 <&cpg_clocks R8A7779_CLK_P>, 478 <&cpg_clocks R8A7779_CLK_P>, 479 <&cpg_clocks R8A7779_CLK_P>, 480 <&cpg_clocks R8A7779_CLK_P>, 481 <&cpg_clocks R8A7779_CLK_P>, 482 <&cpg_clocks R8A7779_CLK_P>, 483 <&cpg_clocks R8A7779_CLK_P>, 484 <&cpg_clocks R8A7779_CLK_P>, 485 <&cpg_clocks R8A7779_CLK_P>; 486 #clock-cells = <1>; 487 clock-indices = < 488 R8A7779_CLK_HSPI R8A7779_CLK_TMU2 489 R8A7779_CLK_TMU1 R8A7779_CLK_TMU0 490 R8A7779_CLK_HSCIF1 R8A7779_CLK_HSCIF0 491 R8A7779_CLK_SCIF5 R8A7779_CLK_SCIF4 492 R8A7779_CLK_SCIF3 R8A7779_CLK_SCIF2 493 R8A7779_CLK_SCIF1 R8A7779_CLK_SCIF0 494 R8A7779_CLK_I2C3 R8A7779_CLK_I2C2 495 R8A7779_CLK_I2C1 R8A7779_CLK_I2C0 496 >; 497 clock-output-names = 498 "hspi", "tmu2", "tmu1", "tmu0", "hscif1", 499 "hscif0", "scif5", "scif4", "scif3", "scif2", 500 "scif1", "scif0", "i2c3", "i2c2", "i2c1", 501 "i2c0"; 502 }; 503 mstp1_clks: clocks@ffc80034 { 504 compatible = "renesas,r8a7779-mstp-clocks", 505 "renesas,cpg-mstp-clocks"; 506 reg = <0xffc80034 4>, <0xffc80044 4>; 507 clocks = <&cpg_clocks R8A7779_CLK_P>, 508 <&cpg_clocks R8A7779_CLK_P>, 509 <&cpg_clocks R8A7779_CLK_S>, 510 <&cpg_clocks R8A7779_CLK_S>, 511 <&cpg_clocks R8A7779_CLK_S>, 512 <&cpg_clocks R8A7779_CLK_S>, 513 <&cpg_clocks R8A7779_CLK_P>, 514 <&cpg_clocks R8A7779_CLK_P>, 515 <&cpg_clocks R8A7779_CLK_P>, 516 <&cpg_clocks R8A7779_CLK_S>; 517 #clock-cells = <1>; 518 clock-indices = < 519 R8A7779_CLK_USB01 R8A7779_CLK_USB2 520 R8A7779_CLK_DU R8A7779_CLK_VIN2 521 R8A7779_CLK_VIN1 R8A7779_CLK_VIN0 522 R8A7779_CLK_ETHER R8A7779_CLK_SATA 523 R8A7779_CLK_PCIE R8A7779_CLK_VIN3 524 >; 525 clock-output-names = 526 "usb01", "usb2", 527 "du", "vin2", 528 "vin1", "vin0", 529 "ether", "sata", 530 "pcie", "vin3"; 531 }; 532 mstp3_clks: clocks@ffc8003c { 533 compatible = "renesas,r8a7779-mstp-clocks", 534 "renesas,cpg-mstp-clocks"; 535 reg = <0xffc8003c 4>; 536 clocks = <&s4_clk>, <&s4_clk>, <&s4_clk>, <&s4_clk>, 537 <&s4_clk>, <&s4_clk>; 538 #clock-cells = <1>; 539 clock-indices = < 540 R8A7779_CLK_SDHI3 R8A7779_CLK_SDHI2 541 R8A7779_CLK_SDHI1 R8A7779_CLK_SDHI0 542 R8A7779_CLK_MMC1 R8A7779_CLK_MMC0 543 >; 544 clock-output-names = 545 "sdhi3", "sdhi2", "sdhi1", "sdhi0", 546 "mmc1", "mmc0"; 547 }; 548 }; 549}; 550