1/*
2 * Device Tree Source for OMAP2 SoC
3 *
4 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2.  This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11#include <dt-bindings/gpio/gpio.h>
12#include <dt-bindings/interrupt-controller/irq.h>
13#include <dt-bindings/pinctrl/omap.h>
14
15#include "skeleton.dtsi"
16
17/ {
18	compatible = "ti,omap2430", "ti,omap2420", "ti,omap2";
19	interrupt-parent = <&intc>;
20
21	aliases {
22		serial0 = &uart1;
23		serial1 = &uart2;
24		serial2 = &uart3;
25		i2c0 = &i2c1;
26		i2c1 = &i2c2;
27	};
28
29	cpus {
30		#address-cells = <0>;
31		#size-cells = <0>;
32
33		cpu {
34			compatible = "arm,arm1136jf-s";
35			device_type = "cpu";
36		};
37	};
38
39	pmu {
40		compatible = "arm,arm1136-pmu";
41		interrupts = <3>;
42	};
43
44	soc {
45		compatible = "ti,omap-infra";
46		mpu {
47			compatible = "ti,omap2-mpu";
48			ti,hwmods = "mpu";
49		};
50	};
51
52	ocp {
53		compatible = "simple-bus";
54		#address-cells = <1>;
55		#size-cells = <1>;
56		ranges;
57		ti,hwmods = "l3_main";
58
59		aes: aes@480a6000 {
60			compatible = "ti,omap2-aes";
61			ti,hwmods = "aes";
62			reg = <0x480a6000 0x50>;
63			dmas = <&sdma 9 &sdma 10>;
64			dma-names = "tx", "rx";
65		};
66
67		hdq1w: 1w@480b2000 {
68			compatible = "ti,omap2420-1w";
69			ti,hwmods = "hdq1w";
70			reg = <0x480b2000 0x1000>;
71			interrupts = <58>;
72		};
73
74		intc: interrupt-controller@1 {
75			compatible = "ti,omap2-intc";
76			interrupt-controller;
77			#interrupt-cells = <1>;
78			reg = <0x480FE000 0x1000>;
79		};
80
81		sdma: dma-controller@48056000 {
82			compatible = "ti,omap2430-sdma", "ti,omap2420-sdma";
83			ti,hwmods = "dma";
84			reg = <0x48056000 0x1000>;
85			interrupts = <12>,
86				     <13>,
87				     <14>,
88				     <15>;
89			#dma-cells = <1>;
90			dma-channels = <32>;
91			dma-requests = <64>;
92		};
93
94		i2c1: i2c@48070000 {
95			compatible = "ti,omap2-i2c";
96			ti,hwmods = "i2c1";
97			reg = <0x48070000 0x80>;
98			#address-cells = <1>;
99			#size-cells = <0>;
100			interrupts = <56>;
101			dmas = <&sdma 27 &sdma 28>;
102			dma-names = "tx", "rx";
103		};
104
105		i2c2: i2c@48072000 {
106			compatible = "ti,omap2-i2c";
107			ti,hwmods = "i2c2";
108			reg = <0x48072000 0x80>;
109			#address-cells = <1>;
110			#size-cells = <0>;
111			interrupts = <57>;
112			dmas = <&sdma 29 &sdma 30>;
113			dma-names = "tx", "rx";
114		};
115
116		mcspi1: mcspi@48098000 {
117			compatible = "ti,omap2-mcspi";
118			ti,hwmods = "mcspi1";
119			reg = <0x48098000 0x100>;
120			interrupts = <65>;
121			dmas = <&sdma 35 &sdma 36 &sdma 37 &sdma 38
122				&sdma 39 &sdma 40 &sdma 41 &sdma 42>;
123			dma-names = "tx0", "rx0", "tx1", "rx1",
124				    "tx2", "rx2", "tx3", "rx3";
125		};
126
127		mcspi2: mcspi@4809a000 {
128			compatible = "ti,omap2-mcspi";
129			ti,hwmods = "mcspi2";
130			reg = <0x4809a000 0x100>;
131			interrupts = <66>;
132			dmas = <&sdma 43 &sdma 44 &sdma 45 &sdma 46>;
133			dma-names = "tx0", "rx0", "tx1", "rx1";
134		};
135
136		rng: rng@480a0000 {
137			compatible = "ti,omap2-rng";
138			ti,hwmods = "rng";
139			reg = <0x480a0000 0x50>;
140			interrupts = <52>;
141		};
142
143		sham: sham@480a4000 {
144			compatible = "ti,omap2-sham";
145			ti,hwmods = "sham";
146			reg = <0x480a4000 0x64>;
147			interrupts = <51>;
148			dmas = <&sdma 13>;
149			dma-names = "rx";
150		};
151
152		uart1: serial@4806a000 {
153			compatible = "ti,omap2-uart";
154			ti,hwmods = "uart1";
155			reg = <0x4806a000 0x2000>;
156			interrupts = <72>;
157			dmas = <&sdma 49 &sdma 50>;
158			dma-names = "tx", "rx";
159			clock-frequency = <48000000>;
160		};
161
162		uart2: serial@4806c000 {
163			compatible = "ti,omap2-uart";
164			ti,hwmods = "uart2";
165			reg = <0x4806c000 0x400>;
166			interrupts = <73>;
167			dmas = <&sdma 51 &sdma 52>;
168			dma-names = "tx", "rx";
169			clock-frequency = <48000000>;
170		};
171
172		uart3: serial@4806e000 {
173			compatible = "ti,omap2-uart";
174			ti,hwmods = "uart3";
175			reg = <0x4806e000 0x400>;
176			interrupts = <74>;
177			dmas = <&sdma 53 &sdma 54>;
178			dma-names = "tx", "rx";
179			clock-frequency = <48000000>;
180		};
181
182		timer2: timer@4802a000 {
183			compatible = "ti,omap2420-timer";
184			reg = <0x4802a000 0x400>;
185			interrupts = <38>;
186			ti,hwmods = "timer2";
187		};
188
189		timer3: timer@48078000 {
190			compatible = "ti,omap2420-timer";
191			reg = <0x48078000 0x400>;
192			interrupts = <39>;
193			ti,hwmods = "timer3";
194		};
195
196		timer4: timer@4807a000 {
197			compatible = "ti,omap2420-timer";
198			reg = <0x4807a000 0x400>;
199			interrupts = <40>;
200			ti,hwmods = "timer4";
201		};
202
203		timer5: timer@4807c000 {
204			compatible = "ti,omap2420-timer";
205			reg = <0x4807c000 0x400>;
206			interrupts = <41>;
207			ti,hwmods = "timer5";
208			ti,timer-dsp;
209		};
210
211		timer6: timer@4807e000 {
212			compatible = "ti,omap2420-timer";
213			reg = <0x4807e000 0x400>;
214			interrupts = <42>;
215			ti,hwmods = "timer6";
216			ti,timer-dsp;
217		};
218
219		timer7: timer@48080000 {
220			compatible = "ti,omap2420-timer";
221			reg = <0x48080000 0x400>;
222			interrupts = <43>;
223			ti,hwmods = "timer7";
224			ti,timer-dsp;
225		};
226
227		timer8: timer@48082000 {
228			compatible = "ti,omap2420-timer";
229			reg = <0x48082000 0x400>;
230			interrupts = <44>;
231			ti,hwmods = "timer8";
232			ti,timer-dsp;
233		};
234
235		timer9: timer@48084000 {
236			compatible = "ti,omap2420-timer";
237			reg = <0x48084000 0x400>;
238			interrupts = <45>;
239			ti,hwmods = "timer9";
240			ti,timer-pwm;
241		};
242
243		timer10: timer@48086000 {
244			compatible = "ti,omap2420-timer";
245			reg = <0x48086000 0x400>;
246			interrupts = <46>;
247			ti,hwmods = "timer10";
248			ti,timer-pwm;
249		};
250
251		timer11: timer@48088000 {
252			compatible = "ti,omap2420-timer";
253			reg = <0x48088000 0x400>;
254			interrupts = <47>;
255			ti,hwmods = "timer11";
256			ti,timer-pwm;
257		};
258
259		timer12: timer@4808a000 {
260			compatible = "ti,omap2420-timer";
261			reg = <0x4808a000 0x400>;
262			interrupts = <48>;
263			ti,hwmods = "timer12";
264			ti,timer-pwm;
265		};
266
267		dss: dss@48050000 {
268			compatible = "ti,omap2-dss";
269			reg = <0x48050000 0x400>;
270			status = "disabled";
271			ti,hwmods = "dss_core";
272			#address-cells = <1>;
273			#size-cells = <1>;
274			ranges;
275
276			dispc@48050400 {
277				compatible = "ti,omap2-dispc";
278				reg = <0x48050400 0x400>;
279				interrupts = <25>;
280				ti,hwmods = "dss_dispc";
281			};
282
283			rfbi: encoder@48050800 {
284				compatible = "ti,omap2-rfbi";
285				reg = <0x48050800 0x400>;
286				status = "disabled";
287				ti,hwmods = "dss_rfbi";
288			};
289
290			venc: encoder@48050c00 {
291				compatible = "ti,omap2-venc";
292				reg = <0x48050c00 0x400>;
293				status = "disabled";
294				ti,hwmods = "dss_venc";
295			};
296		};
297	};
298};
299