1/* 2 * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru> 3 * 4 * The code contained herein is licensed under the GNU General Public 5 * License. You may obtain a copy of the GNU General Public License 6 * Version 2 or later at the following locations: 7 * 8 * http://www.opensource.org/licenses/gpl-license.html 9 * http://www.gnu.org/copyleft/gpl.html 10 */ 11 12/dts-v1/; 13#include "imx27.dtsi" 14 15/ { 16 model = "Eukrea CPUIMX27"; 17 compatible = "eukrea,cpuimx27", "fsl,imx27"; 18 19 memory { 20 reg = <0xa0000000 0x04000000>; 21 }; 22 23 clocks { 24 #address-cells = <1>; 25 #size-cells = <0>; 26 compatible = "simple-bus"; 27 28 clk14745600: clock@0 { 29 #clock-cells = <0>; 30 compatible = "fixed-clock"; 31 clock-frequency = <14745600>; 32 reg = <0>; 33 }; 34 }; 35}; 36 37&fec { 38 pinctrl-names = "default"; 39 pinctrl-0 = <&pinctrl_fec>; 40 status = "okay"; 41}; 42 43&i2c1 { 44 pinctrl-names = "default"; 45 pinctrl-0 = <&pinctrl_i2c1>; 46 status = "okay"; 47 48 pcf8563@51 { 49 compatible = "nxp,pcf8563"; 50 reg = <0x51>; 51 }; 52}; 53 54&nfc { 55 pinctrl-names = "default"; 56 pinctrl-0 = <&pinctrl_nfc>; 57 nand-bus-width = <8>; 58 nand-ecc-mode = "hw"; 59 nand-on-flash-bbt; 60 status = "okay"; 61}; 62 63&owire { 64 pinctrl-names = "default"; 65 pinctrl-0 = <&pinctrl_owire>; 66 status = "okay"; 67}; 68 69&sdhci2 { 70 pinctrl-names = "default"; 71 pinctrl-0 = <&pinctrl_sdhc2>; 72 bus-width = <4>; 73 non-removable; 74 status = "okay"; 75}; 76 77&uart4 { 78 pinctrl-names = "default"; 79 pinctrl-0 = <&pinctrl_uart4>; 80 fsl,uart-has-rtscts; 81 status = "okay"; 82}; 83 84&usbh2 { 85 pinctrl-names = "default"; 86 pinctrl-0 = <&pinctrl_usbh2>; 87 dr_mode = "host"; 88 phy_type = "ulpi"; 89 disable-over-current; 90 status = "okay"; 91}; 92 93&usbotg { 94 pinctrl-names = "default"; 95 pinctrl-0 = <&pinctrl_usbotg>; 96 dr_mode = "otg"; 97 phy_type = "ulpi"; 98 disable-over-current; 99 status = "okay"; 100}; 101 102&weim { 103 status = "okay"; 104 105 nor: nor@0,0 { 106 #address-cells = <1>; 107 #size-cells = <1>; 108 compatible = "cfi-flash"; 109 reg = <0 0x00000000 0x04000000>; 110 bank-width = <2>; 111 linux,mtd-name = "physmap-flash.0"; 112 fsl,weim-cs-timing = <0x00008f03 0xa0330d01 0x002208c0>; 113 }; 114 115 uart8250@3,200000 { 116 pinctrl-names = "default"; 117 pinctrl-0 = <&pinctrl_uart8250_1>; 118 compatible = "ns8250"; 119 clocks = <&clk14745600>; 120 fsl,weim-cs-timing = <0x0000d603 0x0d1d0d01 0x00d20000>; 121 interrupts = <&gpio2 23 IRQ_TYPE_LEVEL_LOW>; 122 reg = <3 0x200000 0x1000>; 123 reg-shift = <1>; 124 reg-io-width = <1>; 125 no-loopback-test; 126 }; 127 128 uart8250@3,400000 { 129 pinctrl-names = "default"; 130 pinctrl-0 = <&pinctrl_uart8250_2>; 131 compatible = "ns8250"; 132 clocks = <&clk14745600>; 133 fsl,weim-cs-timing = <0x0000d603 0x0d1d0d01 0x00d20000>; 134 interrupts = <&gpio2 22 IRQ_TYPE_LEVEL_LOW>; 135 reg = <3 0x400000 0x1000>; 136 reg-shift = <1>; 137 reg-io-width = <1>; 138 no-loopback-test; 139 }; 140 141 uart8250@3,800000 { 142 pinctrl-names = "default"; 143 pinctrl-0 = <&pinctrl_uart8250_3>; 144 compatible = "ns8250"; 145 clocks = <&clk14745600>; 146 fsl,weim-cs-timing = <0x0000d603 0x0d1d0d01 0x00d20000>; 147 interrupts = <&gpio2 27 IRQ_TYPE_LEVEL_LOW>; 148 reg = <3 0x800000 0x1000>; 149 reg-shift = <1>; 150 reg-io-width = <1>; 151 no-loopback-test; 152 }; 153 154 uart8250@3,1000000 { 155 pinctrl-names = "default"; 156 pinctrl-0 = <&pinctrl_uart8250_4>; 157 compatible = "ns8250"; 158 clocks = <&clk14745600>; 159 fsl,weim-cs-timing = <0x0000d603 0x0d1d0d01 0x00d20000>; 160 interrupts = <&gpio2 30 IRQ_TYPE_LEVEL_LOW>; 161 reg = <3 0x1000000 0x1000>; 162 reg-shift = <1>; 163 reg-io-width = <1>; 164 no-loopback-test; 165 }; 166}; 167 168&iomuxc { 169 imx27-eukrea-cpuimx27 { 170 pinctrl_fec: fecgrp { 171 fsl,pins = < 172 MX27_PAD_SD3_CMD__FEC_TXD0 0x0 173 MX27_PAD_SD3_CLK__FEC_TXD1 0x0 174 MX27_PAD_ATA_DATA0__FEC_TXD2 0x0 175 MX27_PAD_ATA_DATA1__FEC_TXD3 0x0 176 MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0 177 MX27_PAD_ATA_DATA3__FEC_RXD1 0x0 178 MX27_PAD_ATA_DATA4__FEC_RXD2 0x0 179 MX27_PAD_ATA_DATA5__FEC_RXD3 0x0 180 MX27_PAD_ATA_DATA6__FEC_MDIO 0x0 181 MX27_PAD_ATA_DATA7__FEC_MDC 0x0 182 MX27_PAD_ATA_DATA8__FEC_CRS 0x0 183 MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0 184 MX27_PAD_ATA_DATA10__FEC_RXD0 0x0 185 MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0 186 MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0 187 MX27_PAD_ATA_DATA13__FEC_COL 0x0 188 MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0 189 MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0 190 >; 191 }; 192 193 pinctrl_i2c1: i2c1grp { 194 fsl,pins = < 195 MX27_PAD_I2C_DATA__I2C_DATA 0x0 196 MX27_PAD_I2C_CLK__I2C_CLK 0x0 197 >; 198 }; 199 200 pinctrl_nfc: nfcgrp { 201 fsl,pins = < 202 MX27_PAD_NFRB__NFRB 0x0 203 MX27_PAD_NFCLE__NFCLE 0x0 204 MX27_PAD_NFWP_B__NFWP_B 0x0 205 MX27_PAD_NFCE_B__NFCE_B 0x0 206 MX27_PAD_NFALE__NFALE 0x0 207 MX27_PAD_NFRE_B__NFRE_B 0x0 208 MX27_PAD_NFWE_B__NFWE_B 0x0 209 >; 210 }; 211 212 pinctrl_owire: owiregrp { 213 fsl,pins = < 214 MX27_PAD_RTCK__OWIRE 0x0 215 >; 216 }; 217 218 pinctrl_sdhc2: sdhc2grp { 219 fsl,pins = < 220 MX27_PAD_SD2_CLK__SD2_CLK 0x0 221 MX27_PAD_SD2_CMD__SD2_CMD 0x0 222 MX27_PAD_SD2_D0__SD2_D0 0x0 223 MX27_PAD_SD2_D1__SD2_D1 0x0 224 MX27_PAD_SD2_D2__SD2_D2 0x0 225 MX27_PAD_SD2_D3__SD2_D3 0x0 226 >; 227 }; 228 229 pinctrl_uart4: uart4grp { 230 fsl,pins = < 231 MX27_PAD_USBH1_TXDM__UART4_TXD 0x0 232 MX27_PAD_USBH1_RXDP__UART4_RXD 0x0 233 MX27_PAD_USBH1_TXDP__UART4_CTS 0x0 234 MX27_PAD_USBH1_FS__UART4_RTS 0x0 235 >; 236 }; 237 238 pinctrl_uart8250_1: uart82501grp { 239 fsl,pins = < 240 MX27_PAD_USB_PWR__GPIO2_23 0x0 241 >; 242 }; 243 244 pinctrl_uart8250_2: uart82502grp { 245 fsl,pins = < 246 MX27_PAD_USBH1_SUSP__GPIO2_22 0x0 247 >; 248 }; 249 250 pinctrl_uart8250_3: uart82503grp { 251 fsl,pins = < 252 MX27_PAD_USBH1_OE_B__GPIO2_27 0x0 253 >; 254 }; 255 256 pinctrl_uart8250_4: uart82504grp { 257 fsl,pins = < 258 MX27_PAD_USBH1_RXDM__GPIO2_30 0x0 259 >; 260 }; 261 262 pinctrl_usbh2: usbh2grp { 263 fsl,pins = < 264 MX27_PAD_USBH2_CLK__USBH2_CLK 0x0 265 MX27_PAD_USBH2_DIR__USBH2_DIR 0x0 266 MX27_PAD_USBH2_NXT__USBH2_NXT 0x0 267 MX27_PAD_USBH2_STP__USBH2_STP 0x0 268 MX27_PAD_CSPI2_SCLK__USBH2_DATA0 0x0 269 MX27_PAD_CSPI2_MOSI__USBH2_DATA1 0x0 270 MX27_PAD_CSPI2_MISO__USBH2_DATA2 0x0 271 MX27_PAD_CSPI2_SS1__USBH2_DATA3 0x0 272 MX27_PAD_CSPI2_SS2__USBH2_DATA4 0x0 273 MX27_PAD_CSPI1_SS2__USBH2_DATA5 0x0 274 MX27_PAD_CSPI2_SS0__USBH2_DATA6 0x0 275 MX27_PAD_USBH2_DATA7__USBH2_DATA7 0x0 276 >; 277 }; 278 279 pinctrl_usbotg: usbotggrp { 280 fsl,pins = < 281 MX27_PAD_USBOTG_CLK__USBOTG_CLK 0x0 282 MX27_PAD_USBOTG_DIR__USBOTG_DIR 0x0 283 MX27_PAD_USBOTG_NXT__USBOTG_NXT 0x0 284 MX27_PAD_USBOTG_STP__USBOTG_STP 0x0 285 MX27_PAD_USBOTG_DATA0__USBOTG_DATA0 0x0 286 MX27_PAD_USBOTG_DATA1__USBOTG_DATA1 0x0 287 MX27_PAD_USBOTG_DATA2__USBOTG_DATA2 0x0 288 MX27_PAD_USBOTG_DATA3__USBOTG_DATA3 0x0 289 MX27_PAD_USBOTG_DATA4__USBOTG_DATA4 0x0 290 MX27_PAD_USBOTG_DATA5__USBOTG_DATA5 0x0 291 MX27_PAD_USBOTG_DATA6__USBOTG_DATA6 0x0 292 MX27_PAD_USBOTG_DATA7__USBOTG_DATA7 0x0 293 >; 294 }; 295 }; 296}; 297