1/* 2 * SAMSUNG EXYNOS5410 SoC device tree source 3 * 4 * Copyright (c) 2013 Samsung Electronics Co., Ltd. 5 * http://www.samsung.com 6 * 7 * SAMSUNG EXYNOS5410 SoC device nodes are listed in this file. 8 * EXYNOS5410 based board files can include this file and provide 9 * values for board specfic bindings. 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License version 2 as 13 * published by the Free Software Foundation. 14 */ 15 16#include "skeleton.dtsi" 17#include <dt-bindings/clock/exynos5410.h> 18 19/ { 20 compatible = "samsung,exynos5410", "samsung,exynos5"; 21 interrupt-parent = <&gic>; 22 23 aliases { 24 serial0 = &uart0; 25 serial1 = &uart1; 26 serial2 = &uart2; 27 }; 28 29 cpus { 30 #address-cells = <1>; 31 #size-cells = <0>; 32 33 CPU0: cpu@0 { 34 device_type = "cpu"; 35 compatible = "arm,cortex-a15"; 36 reg = <0x0>; 37 clock-frequency = <1600000000>; 38 }; 39 40 CPU1: cpu@1 { 41 device_type = "cpu"; 42 compatible = "arm,cortex-a15"; 43 reg = <0x1>; 44 clock-frequency = <1600000000>; 45 }; 46 47 CPU2: cpu@2 { 48 device_type = "cpu"; 49 compatible = "arm,cortex-a15"; 50 reg = <0x2>; 51 clock-frequency = <1600000000>; 52 }; 53 54 CPU3: cpu@3 { 55 device_type = "cpu"; 56 compatible = "arm,cortex-a15"; 57 reg = <0x3>; 58 clock-frequency = <1600000000>; 59 }; 60 }; 61 62 soc: soc { 63 compatible = "simple-bus"; 64 #address-cells = <1>; 65 #size-cells = <1>; 66 ranges; 67 68 combiner: interrupt-controller@10440000 { 69 compatible = "samsung,exynos4210-combiner"; 70 #interrupt-cells = <2>; 71 interrupt-controller; 72 samsung,combiner-nr = <32>; 73 reg = <0x10440000 0x1000>; 74 interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>, 75 <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>, 76 <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>, 77 <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>, 78 <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>, 79 <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>, 80 <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>, 81 <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>; 82 }; 83 84 gic: interrupt-controller@10481000 { 85 compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; 86 #interrupt-cells = <3>; 87 interrupt-controller; 88 reg = <0x10481000 0x1000>, 89 <0x10482000 0x1000>, 90 <0x10484000 0x2000>, 91 <0x10486000 0x2000>; 92 interrupts = <1 9 0xf04>; 93 }; 94 95 chipid@10000000 { 96 compatible = "samsung,exynos4210-chipid"; 97 reg = <0x10000000 0x100>; 98 }; 99 100 pmu_system_controller: system-controller@10040000 { 101 compatible = "samsung,exynos5410-pmu", "syscon"; 102 reg = <0x10040000 0x5000>; 103 }; 104 105 mct: mct@101C0000 { 106 compatible = "samsung,exynos4210-mct"; 107 reg = <0x101C0000 0xB00>; 108 interrupt-parent = <&interrupt_map>; 109 interrupts = <0>, <1>, <2>, <3>, 110 <4>, <5>, <6>, <7>, 111 <8>, <9>, <10>, <11>; 112 clocks = <&fin_pll>, <&clock CLK_MCT>; 113 clock-names = "fin_pll", "mct"; 114 115 interrupt_map: interrupt-map { 116 #interrupt-cells = <1>; 117 #address-cells = <0>; 118 #size-cells = <0>; 119 interrupt-map = <0 &combiner 23 3>, 120 <1 &combiner 23 4>, 121 <2 &combiner 25 2>, 122 <3 &combiner 25 3>, 123 <4 &gic 0 120 0>, 124 <5 &gic 0 121 0>, 125 <6 &gic 0 122 0>, 126 <7 &gic 0 123 0>, 127 <8 &gic 0 128 0>, 128 <9 &gic 0 129 0>, 129 <10 &gic 0 130 0>, 130 <11 &gic 0 131 0>; 131 }; 132 }; 133 134 sysram@02020000 { 135 compatible = "mmio-sram"; 136 reg = <0x02020000 0x54000>; 137 #address-cells = <1>; 138 #size-cells = <1>; 139 ranges = <0 0x02020000 0x54000>; 140 141 smp-sysram@0 { 142 compatible = "samsung,exynos4210-sysram"; 143 reg = <0x0 0x1000>; 144 }; 145 146 smp-sysram@53000 { 147 compatible = "samsung,exynos4210-sysram-ns"; 148 reg = <0x53000 0x1000>; 149 }; 150 }; 151 152 clock: clock-controller@10010000 { 153 compatible = "samsung,exynos5410-clock"; 154 reg = <0x10010000 0x30000>; 155 #clock-cells = <1>; 156 }; 157 158 mmc_0: mmc@12200000 { 159 compatible = "samsung,exynos5250-dw-mshc"; 160 reg = <0x12200000 0x1000>; 161 interrupts = <0 75 0>; 162 #address-cells = <1>; 163 #size-cells = <0>; 164 clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>; 165 clock-names = "biu", "ciu"; 166 fifo-depth = <0x80>; 167 status = "disabled"; 168 }; 169 170 mmc_1: mmc@12210000 { 171 compatible = "samsung,exynos5250-dw-mshc"; 172 reg = <0x12210000 0x1000>; 173 interrupts = <0 76 0>; 174 #address-cells = <1>; 175 #size-cells = <0>; 176 clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>; 177 clock-names = "biu", "ciu"; 178 fifo-depth = <0x80>; 179 status = "disabled"; 180 }; 181 182 mmc_2: mmc@12220000 { 183 compatible = "samsung,exynos5250-dw-mshc"; 184 reg = <0x12220000 0x1000>; 185 interrupts = <0 77 0>; 186 #address-cells = <1>; 187 #size-cells = <0>; 188 clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>; 189 clock-names = "biu", "ciu"; 190 fifo-depth = <0x80>; 191 status = "disabled"; 192 }; 193 194 uart0: serial@12C00000 { 195 compatible = "samsung,exynos4210-uart"; 196 reg = <0x12C00000 0x100>; 197 interrupts = <0 51 0>; 198 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>; 199 clock-names = "uart", "clk_uart_baud0"; 200 status = "disabled"; 201 }; 202 203 uart1: serial@12C10000 { 204 compatible = "samsung,exynos4210-uart"; 205 reg = <0x12C10000 0x100>; 206 interrupts = <0 52 0>; 207 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>; 208 clock-names = "uart", "clk_uart_baud0"; 209 status = "disabled"; 210 }; 211 212 uart2: serial@12C20000 { 213 compatible = "samsung,exynos4210-uart"; 214 reg = <0x12C20000 0x100>; 215 interrupts = <0 53 0>; 216 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>; 217 clock-names = "uart", "clk_uart_baud0"; 218 status = "disabled"; 219 }; 220 }; 221}; 222