1/*
2 * Copyright (C) 2014 Antoine Ténart <antoine.tenart@free-electrons.com>
3 *
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2. This program is licensed "as is" without any
6 * warranty of any kind, whether express or implied.
7 */
8
9#include <dt-bindings/clock/berlin2q.h>
10#include <dt-bindings/interrupt-controller/arm-gic.h>
11
12#include "skeleton.dtsi"
13
14/ {
15	model = "Marvell Armada 1500 pro (BG2-Q) SoC";
16	compatible = "marvell,berlin2q", "marvell,berlin";
17
18	cpus {
19		#address-cells = <1>;
20		#size-cells = <0>;
21		enable-method = "marvell,berlin-smp";
22
23		cpu@0 {
24			compatible = "arm,cortex-a9";
25			device_type = "cpu";
26			next-level-cache = <&l2>;
27			reg = <0>;
28		};
29
30		cpu@1 {
31			compatible = "arm,cortex-a9";
32			device_type = "cpu";
33			next-level-cache = <&l2>;
34			reg = <1>;
35		};
36
37		cpu@2 {
38			compatible = "arm,cortex-a9";
39			device_type = "cpu";
40			next-level-cache = <&l2>;
41			reg = <2>;
42		};
43
44		cpu@3 {
45			compatible = "arm,cortex-a9";
46			device_type = "cpu";
47			next-level-cache = <&l2>;
48			reg = <3>;
49		};
50	};
51
52	refclk: oscillator {
53		compatible = "fixed-clock";
54		#clock-cells = <0>;
55		clock-frequency = <25000000>;
56	};
57
58	soc {
59		compatible = "simple-bus";
60		#address-cells = <1>;
61		#size-cells = <1>;
62
63		ranges = <0 0xf7000000 0x1000000>;
64		interrupt-parent = <&gic>;
65
66		pmu {
67			compatible = "arm,cortex-a9-pmu";
68			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
69				     <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
70				     <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
71				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
72		};
73
74		sdhci0: sdhci@ab0000 {
75			compatible = "mrvl,pxav3-mmc";
76			reg = <0xab0000 0x200>;
77			clocks = <&chip CLKID_SDIO1XIN>;
78			interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
79			status = "disabled";
80		};
81
82		sdhci1: sdhci@ab0800 {
83			compatible = "mrvl,pxav3-mmc";
84			reg = <0xab0800 0x200>;
85			clocks = <&chip CLKID_SDIO1XIN>;
86			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
87			status = "disabled";
88		};
89
90		sdhci2: sdhci@ab1000 {
91			compatible = "mrvl,pxav3-mmc";
92			reg = <0xab1000 0x200>;
93			interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
94			clocks = <&chip CLKID_NFC_ECC>, <&chip CLKID_NFC>;
95			clock-names = "io", "core";
96			status = "disabled";
97		};
98
99		l2: l2-cache-controller@ac0000 {
100			compatible = "arm,pl310-cache";
101			reg = <0xac0000 0x1000>;
102			cache-level = <2>;
103			arm,data-latency = <2 2 2>;
104			arm,tag-latency = <2 2 2>;
105		};
106
107		scu: snoop-control-unit@ad0000 {
108			compatible = "arm,cortex-a9-scu";
109			reg = <0xad0000 0x58>;
110		};
111
112		local-timer@ad0600 {
113			compatible = "arm,cortex-a9-twd-timer";
114			reg = <0xad0600 0x20>;
115			clocks = <&chip CLKID_TWD>;
116			interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
117		};
118
119		gic: interrupt-controller@ad1000 {
120			compatible = "arm,cortex-a9-gic";
121			reg = <0xad1000 0x1000>, <0xad0100 0x100>;
122			interrupt-controller;
123			#interrupt-cells = <3>;
124		};
125
126		usb_phy2: phy@a2f400 {
127			compatible = "marvell,berlin2-usb-phy";
128			reg = <0xa2f400 0x128>;
129			#phy-cells = <0>;
130			resets = <&chip 0x104 14>;
131			status = "disabled";
132		};
133
134		usb2: usb@a30000 {
135			compatible = "chipidea,usb2";
136			reg = <0xa30000 0x10000>;
137			interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
138			clocks = <&chip CLKID_USB2>;
139			phys = <&usb_phy2>;
140			phy-names = "usb-phy";
141			status = "disabled";
142		};
143
144		usb_phy0: phy@b74000 {
145			compatible = "marvell,berlin2-usb-phy";
146			reg = <0xb74000 0x128>;
147			#phy-cells = <0>;
148			resets = <&chip 0x104 12>;
149			status = "disabled";
150		};
151
152		usb_phy1: phy@b78000 {
153			compatible = "marvell,berlin2-usb-phy";
154			reg = <0xb78000 0x128>;
155			#phy-cells = <0>;
156			resets = <&chip 0x104 13>;
157			status = "disabled";
158		};
159
160		eth0: ethernet@b90000 {
161			compatible = "marvell,pxa168-eth";
162			reg = <0xb90000 0x10000>;
163			clocks = <&chip CLKID_GETH0>;
164			interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
165			/* set by bootloader */
166			local-mac-address = [00 00 00 00 00 00];
167			#address-cells = <1>;
168			#size-cells = <0>;
169			phy-connection-type = "mii";
170			phy-handle = <&ethphy0>;
171			status = "disabled";
172
173			ethphy0: ethernet-phy@0 {
174				reg = <0>;
175			};
176		};
177
178		cpu-ctrl@dd0000 {
179			compatible = "marvell,berlin-cpu-ctrl";
180			reg = <0xdd0000 0x10000>;
181		};
182
183		apb@e80000 {
184			compatible = "simple-bus";
185			#address-cells = <1>;
186			#size-cells = <1>;
187
188			ranges = <0 0xe80000 0x10000>;
189			interrupt-parent = <&aic>;
190
191			gpio0: gpio@0400 {
192				compatible = "snps,dw-apb-gpio";
193				reg = <0x0400 0x400>;
194				#address-cells = <1>;
195				#size-cells = <0>;
196
197				porta: gpio-port@0 {
198					compatible = "snps,dw-apb-gpio-port";
199					gpio-controller;
200					#gpio-cells = <2>;
201					snps,nr-gpios = <32>;
202					reg = <0>;
203					interrupt-controller;
204					#interrupt-cells = <2>;
205					interrupts = <0>;
206				};
207			};
208
209			gpio1: gpio@0800 {
210				compatible = "snps,dw-apb-gpio";
211				reg = <0x0800 0x400>;
212				#address-cells = <1>;
213				#size-cells = <0>;
214
215				portb: gpio-port@1 {
216					compatible = "snps,dw-apb-gpio-port";
217					gpio-controller;
218					#gpio-cells = <2>;
219					snps,nr-gpios = <32>;
220					reg = <0>;
221					interrupt-controller;
222					#interrupt-cells = <2>;
223					interrupts = <1>;
224				};
225			};
226
227			gpio2: gpio@0c00 {
228				compatible = "snps,dw-apb-gpio";
229				reg = <0x0c00 0x400>;
230				#address-cells = <1>;
231				#size-cells = <0>;
232
233				portc: gpio-port@2 {
234					compatible = "snps,dw-apb-gpio-port";
235					gpio-controller;
236					#gpio-cells = <2>;
237					snps,nr-gpios = <32>;
238					reg = <0>;
239					interrupt-controller;
240					#interrupt-cells = <2>;
241					interrupts = <2>;
242				};
243			};
244
245			gpio3: gpio@1000 {
246				compatible = "snps,dw-apb-gpio";
247				reg = <0x1000 0x400>;
248				#address-cells = <1>;
249				#size-cells = <0>;
250
251				portd: gpio-port@3 {
252					compatible = "snps,dw-apb-gpio-port";
253					gpio-controller;
254					#gpio-cells = <2>;
255					snps,nr-gpios = <32>;
256					reg = <0>;
257					interrupt-controller;
258					#interrupt-cells = <2>;
259					interrupts = <3>;
260				};
261			};
262
263			i2c0: i2c@1400 {
264				compatible = "snps,designware-i2c";
265				#address-cells = <1>;
266				#size-cells = <0>;
267				reg = <0x1400 0x100>;
268				interrupt-parent = <&aic>;
269				interrupts = <4>;
270				clocks = <&chip CLKID_CFG>;
271				pinctrl-0 = <&twsi0_pmux>;
272				pinctrl-names = "default";
273				status = "disabled";
274			};
275
276			i2c1: i2c@1800 {
277				compatible = "snps,designware-i2c";
278				#address-cells = <1>;
279				#size-cells = <0>;
280				reg = <0x1800 0x100>;
281				interrupt-parent = <&aic>;
282				interrupts = <5>;
283				clocks = <&chip CLKID_CFG>;
284				pinctrl-0 = <&twsi1_pmux>;
285				pinctrl-names = "default";
286				status = "disabled";
287			};
288
289			timer0: timer@2c00 {
290				compatible = "snps,dw-apb-timer";
291				reg = <0x2c00 0x14>;
292				clocks = <&chip CLKID_CFG>;
293				clock-names = "timer";
294				interrupts = <8>;
295			};
296
297			timer1: timer@2c14 {
298				compatible = "snps,dw-apb-timer";
299				reg = <0x2c14 0x14>;
300				clocks = <&chip CLKID_CFG>;
301				clock-names = "timer";
302			};
303
304			timer2: timer@2c28 {
305				compatible = "snps,dw-apb-timer";
306				reg = <0x2c28 0x14>;
307				clocks = <&chip CLKID_CFG>;
308				clock-names = "timer";
309				status = "disabled";
310			};
311
312			timer3: timer@2c3c {
313				compatible = "snps,dw-apb-timer";
314				reg = <0x2c3c 0x14>;
315				clocks = <&chip CLKID_CFG>;
316				clock-names = "timer";
317				status = "disabled";
318			};
319
320			timer4: timer@2c50 {
321				compatible = "snps,dw-apb-timer";
322				reg = <0x2c50 0x14>;
323				clocks = <&chip CLKID_CFG>;
324				clock-names = "timer";
325				status = "disabled";
326			};
327
328			timer5: timer@2c64 {
329				compatible = "snps,dw-apb-timer";
330				reg = <0x2c64 0x14>;
331				clocks = <&chip CLKID_CFG>;
332				clock-names = "timer";
333				status = "disabled";
334			};
335
336			timer6: timer@2c78 {
337				compatible = "snps,dw-apb-timer";
338				reg = <0x2c78 0x14>;
339				clocks = <&chip CLKID_CFG>;
340				clock-names = "timer";
341				status = "disabled";
342			};
343
344			timer7: timer@2c8c {
345				compatible = "snps,dw-apb-timer";
346				reg = <0x2c8c 0x14>;
347				clocks = <&chip CLKID_CFG>;
348				clock-names = "timer";
349				status = "disabled";
350			};
351
352			aic: interrupt-controller@3800 {
353				compatible = "snps,dw-apb-ictl";
354				reg = <0x3800 0x30>;
355				interrupt-controller;
356				#interrupt-cells = <1>;
357				interrupt-parent = <&gic>;
358				interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
359			};
360		};
361
362		chip: chip-control@ea0000 {
363			compatible = "marvell,berlin2q-chip-ctrl";
364			#clock-cells = <1>;
365			#reset-cells = <2>;
366			reg = <0xea0000 0x400>, <0xdd0170 0x10>;
367			clocks = <&refclk>;
368			clock-names = "refclk";
369
370			twsi0_pmux: twsi0-pmux {
371				groups = "G6";
372				function = "twsi0";
373			};
374
375			twsi1_pmux: twsi1-pmux {
376				groups = "G7";
377				function = "twsi1";
378			};
379		};
380
381		ahci: sata@e90000 {
382			compatible = "marvell,berlin2q-ahci", "generic-ahci";
383			reg = <0xe90000 0x1000>;
384			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
385			clocks = <&chip CLKID_SATA>;
386			#address-cells = <1>;
387			#size-cells = <0>;
388
389			sata0: sata-port@0 {
390				reg = <0>;
391				phys = <&sata_phy 0>;
392				status = "disabled";
393			};
394
395			sata1: sata-port@1 {
396				reg = <1>;
397				phys = <&sata_phy 1>;
398				status = "disabled";
399			};
400		};
401
402		sata_phy: phy@e900a0 {
403			compatible = "marvell,berlin2q-sata-phy";
404			reg = <0xe900a0 0x200>;
405			clocks = <&chip CLKID_SATA>;
406			#address-cells = <1>;
407			#size-cells = <0>;
408			#phy-cells = <1>;
409			status = "disabled";
410
411			sata-phy@0 {
412				reg = <0>;
413			};
414
415			sata-phy@1 {
416				reg = <1>;
417			};
418		};
419
420		usb0: usb@ed0000 {
421			compatible = "chipidea,usb2";
422			reg = <0xed0000 0x10000>;
423			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
424			clocks = <&chip CLKID_USB0>;
425			phys = <&usb_phy0>;
426			phy-names = "usb-phy";
427			status = "disabled";
428		};
429
430		usb1: usb@ee0000 {
431			compatible = "chipidea,usb2";
432			reg = <0xee0000 0x10000>;
433			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
434			clocks = <&chip CLKID_USB1>;
435			phys = <&usb_phy1>;
436			phy-names = "usb-phy";
437			status = "disabled";
438		};
439
440		apb@fc0000 {
441			compatible = "simple-bus";
442			#address-cells = <1>;
443			#size-cells = <1>;
444
445			ranges = <0 0xfc0000 0x10000>;
446			interrupt-parent = <&sic>;
447
448			sm_gpio1: gpio@5000 {
449				compatible = "snps,dw-apb-gpio";
450				reg = <0x5000 0x400>;
451				#address-cells = <1>;
452				#size-cells = <0>;
453
454				portf: gpio-port@5 {
455					compatible = "snps,dw-apb-gpio-port";
456					gpio-controller;
457					#gpio-cells = <2>;
458					snps,nr-gpios = <32>;
459					reg = <0>;
460				};
461			};
462
463			i2c2: i2c@7000 {
464				compatible = "snps,designware-i2c";
465				#address-cells = <1>;
466				#size-cells = <0>;
467				reg = <0x7000 0x100>;
468				interrupt-parent = <&sic>;
469				interrupts = <6>;
470				clocks = <&refclk>;
471				pinctrl-0 = <&twsi2_pmux>;
472				pinctrl-names = "default";
473				status = "disabled";
474			};
475
476			i2c3: i2c@8000 {
477				compatible = "snps,designware-i2c";
478				#address-cells = <1>;
479				#size-cells = <0>;
480				reg = <0x8000 0x100>;
481				interrupt-parent = <&sic>;
482				interrupts = <7>;
483				clocks = <&refclk>;
484				pinctrl-0 = <&twsi3_pmux>;
485				pinctrl-names = "default";
486				status = "disabled";
487			};
488
489			uart0: uart@9000 {
490				compatible = "snps,dw-apb-uart";
491				reg = <0x9000 0x100>;
492				interrupt-parent = <&sic>;
493				interrupts = <8>;
494				clocks = <&refclk>;
495				reg-shift = <2>;
496				pinctrl-0 = <&uart0_pmux>;
497				pinctrl-names = "default";
498				status = "disabled";
499			};
500
501			uart1: uart@a000 {
502				compatible = "snps,dw-apb-uart";
503				reg = <0xa000 0x100>;
504				interrupt-parent = <&sic>;
505				interrupts = <9>;
506				clocks = <&refclk>;
507				reg-shift = <2>;
508				pinctrl-0 = <&uart1_pmux>;
509				pinctrl-names = "default";
510				status = "disabled";
511			};
512
513			sm_gpio0: gpio@c000 {
514				compatible = "snps,dw-apb-gpio";
515				reg = <0xc000 0x400>;
516				#address-cells = <1>;
517				#size-cells = <0>;
518
519				porte: gpio-port@4 {
520					compatible = "snps,dw-apb-gpio-port";
521					gpio-controller;
522					#gpio-cells = <2>;
523					snps,nr-gpios = <32>;
524					reg = <0>;
525				};
526			};
527
528			sysctrl: pin-controller@d000 {
529				compatible = "marvell,berlin2q-system-ctrl";
530				reg = <0xd000 0x100>;
531
532				uart0_pmux: uart0-pmux {
533					groups = "GSM12";
534					function = "uart0";
535				};
536
537				uart1_pmux: uart1-pmux {
538					groups = "GSM14";
539					function = "uart1";
540				};
541
542				twsi2_pmux: twsi2-pmux {
543					groups = "GSM13";
544					function = "twsi2";
545				};
546
547				twsi3_pmux: twsi3-pmux {
548					groups = "GSM14";
549					function = "twsi3";
550				};
551			};
552
553			sic: interrupt-controller@e000 {
554				compatible = "snps,dw-apb-ictl";
555				reg = <0xe000 0x30>;
556				interrupt-controller;
557				#interrupt-cells = <1>;
558				interrupt-parent = <&gic>;
559				interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
560			};
561		};
562	};
563};
564