1/*
2 * at91rm9200.dtsi - Device Tree Include file for AT91RM9200 family SoC
3 *
4 *  Copyright (C) 2011 Atmel,
5 *                2011 Nicolas Ferre <nicolas.ferre@atmel.com>,
6 *                2012 Joachim Eastwood <manabian@gmail.com>
7 *
8 * Based on at91sam9260.dtsi
9 *
10 * Licensed under GPLv2 or later.
11 */
12
13#include "skeleton.dtsi"
14#include <dt-bindings/pinctrl/at91.h>
15#include <dt-bindings/interrupt-controller/irq.h>
16#include <dt-bindings/gpio/gpio.h>
17#include <dt-bindings/clock/at91.h>
18
19/ {
20	model = "Atmel AT91RM9200 family SoC";
21	compatible = "atmel,at91rm9200";
22	interrupt-parent = <&aic>;
23
24	aliases {
25		serial0 = &dbgu;
26		serial1 = &usart0;
27		serial2 = &usart1;
28		serial3 = &usart2;
29		serial4 = &usart3;
30		gpio0 = &pioA;
31		gpio1 = &pioB;
32		gpio2 = &pioC;
33		gpio3 = &pioD;
34		tcb0 = &tcb0;
35		tcb1 = &tcb1;
36		i2c0 = &i2c0;
37		ssc0 = &ssc0;
38		ssc1 = &ssc1;
39		ssc2 = &ssc2;
40	};
41	cpus {
42		#address-cells = <0>;
43		#size-cells = <0>;
44
45		cpu {
46			compatible = "arm,arm920t";
47			device_type = "cpu";
48		};
49	};
50
51	memory {
52		reg = <0x20000000 0x04000000>;
53	};
54
55	clocks {
56		slow_xtal: slow_xtal {
57			compatible = "fixed-clock";
58			#clock-cells = <0>;
59			clock-frequency = <0>;
60		};
61
62		main_xtal: main_xtal {
63			compatible = "fixed-clock";
64			#clock-cells = <0>;
65			clock-frequency = <0>;
66		};
67	};
68
69	sram: sram@00200000 {
70		compatible = "mmio-sram";
71		reg = <0x00200000 0x4000>;
72	};
73
74	ahb {
75		compatible = "simple-bus";
76		#address-cells = <1>;
77		#size-cells = <1>;
78		ranges;
79
80		apb {
81			compatible = "simple-bus";
82			#address-cells = <1>;
83			#size-cells = <1>;
84			ranges;
85
86			aic: interrupt-controller@fffff000 {
87				#interrupt-cells = <3>;
88				compatible = "atmel,at91rm9200-aic";
89				interrupt-controller;
90				reg = <0xfffff000 0x200>;
91				atmel,external-irqs = <25 26 27 28 29 30 31>;
92			};
93
94			ramc0: ramc@ffffff00 {
95				compatible = "atmel,at91rm9200-sdramc";
96				reg = <0xffffff00 0x100>;
97			};
98
99			pmc: pmc@fffffc00 {
100				compatible = "atmel,at91rm9200-pmc";
101				reg = <0xfffffc00 0x100>;
102				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
103				interrupt-controller;
104				#address-cells = <1>;
105				#size-cells = <0>;
106				#interrupt-cells = <1>;
107
108				main_osc: main_osc {
109					compatible = "atmel,at91rm9200-clk-main-osc";
110					#clock-cells = <0>;
111					interrupts-extended = <&pmc AT91_PMC_MOSCS>;
112					clocks = <&main_xtal>;
113				};
114
115				main: mainck {
116					compatible = "atmel,at91rm9200-clk-main";
117					#clock-cells = <0>;
118					clocks = <&main_osc>;
119				};
120
121				plla: pllack {
122					compatible = "atmel,at91rm9200-clk-pll";
123					#clock-cells = <0>;
124					interrupts-extended = <&pmc AT91_PMC_LOCKA>;
125					clocks = <&main>;
126					reg = <0>;
127					atmel,clk-input-range = <1000000 32000000>;
128					#atmel,pll-clk-output-range-cells = <3>;
129					atmel,pll-clk-output-ranges = <80000000 160000000 0>,
130								<150000000 180000000 2>;
131				};
132
133				pllb: pllbck {
134					compatible = "atmel,at91rm9200-clk-pll";
135					#clock-cells = <0>;
136					interrupts-extended = <&pmc AT91_PMC_LOCKB>;
137					clocks = <&main>;
138					reg = <1>;
139					atmel,clk-input-range = <1000000 32000000>;
140					#atmel,pll-clk-output-range-cells = <3>;
141					atmel,pll-clk-output-ranges = <80000000 160000000 0>,
142								<150000000 180000000 2>;
143				};
144
145				mck: masterck {
146					compatible = "atmel,at91rm9200-clk-master";
147					#clock-cells = <0>;
148					interrupts-extended = <&pmc AT91_PMC_MCKRDY>;
149					clocks = <&slow_xtal>, <&main>, <&plla>, <&pllb>;
150					atmel,clk-output-range = <0 80000000>;
151					atmel,clk-divisors = <1 2 3 4>;
152				};
153
154				usb: usbck {
155					compatible = "atmel,at91rm9200-clk-usb";
156					#clock-cells = <0>;
157					atmel,clk-divisors = <1 2 0 0>;
158					clocks = <&pllb>;
159				};
160
161				prog: progck {
162					compatible = "atmel,at91rm9200-clk-programmable";
163					#address-cells = <1>;
164					#size-cells = <0>;
165					interrupt-parent = <&pmc>;
166					clocks = <&slow_xtal>, <&main>, <&plla>, <&pllb>;
167
168					prog0: prog0 {
169						#clock-cells = <0>;
170						reg = <0>;
171						interrupts = <AT91_PMC_PCKRDY(0)>;
172					};
173
174					prog1: prog1 {
175						#clock-cells = <0>;
176						reg = <1>;
177						interrupts = <AT91_PMC_PCKRDY(1)>;
178					};
179
180					prog2: prog2 {
181						#clock-cells = <0>;
182						reg = <2>;
183						interrupts = <AT91_PMC_PCKRDY(2)>;
184					};
185
186					prog3: prog3 {
187						#clock-cells = <0>;
188						reg = <3>;
189						interrupts = <AT91_PMC_PCKRDY(3)>;
190					};
191				};
192
193				systemck {
194					compatible = "atmel,at91rm9200-clk-system";
195					#address-cells = <1>;
196					#size-cells = <0>;
197
198					udpck: udpck {
199						#clock-cells = <0>;
200						reg = <2>;
201						clocks = <&usb>;
202					};
203
204					uhpck: uhpck {
205						#clock-cells = <0>;
206						reg = <4>;
207						clocks = <&usb>;
208					};
209
210					pck0: pck0 {
211						#clock-cells = <0>;
212						reg = <8>;
213						clocks = <&prog0>;
214					};
215
216					pck1: pck1 {
217						#clock-cells = <0>;
218						reg = <9>;
219						clocks = <&prog1>;
220					};
221
222					pck2: pck2 {
223						#clock-cells = <0>;
224						reg = <10>;
225						clocks = <&prog2>;
226					};
227
228					pck3: pck3 {
229						#clock-cells = <0>;
230						reg = <11>;
231						clocks = <&prog3>;
232					};
233				};
234
235				periphck {
236					compatible = "atmel,at91rm9200-clk-peripheral";
237					#address-cells = <1>;
238					#size-cells = <0>;
239					clocks = <&mck>;
240
241					pioA_clk: pioA_clk {
242						#clock-cells = <0>;
243						reg = <2>;
244					};
245
246					pioB_clk: pioB_clk {
247						#clock-cells = <0>;
248						reg = <3>;
249					};
250
251					pioC_clk: pioC_clk {
252						#clock-cells = <0>;
253						reg = <4>;
254					};
255
256					pioD_clk: pioD_clk {
257						#clock-cells = <0>;
258						reg = <5>;
259					};
260
261					usart0_clk: usart0_clk {
262						#clock-cells = <0>;
263						reg = <6>;
264					};
265
266					usart1_clk: usart1_clk {
267						#clock-cells = <0>;
268						reg = <7>;
269					};
270
271					usart2_clk: usart2_clk {
272						#clock-cells = <0>;
273						reg = <8>;
274					};
275
276					usart3_clk: usart3_clk {
277						#clock-cells = <0>;
278						reg = <9>;
279					};
280
281					mci0_clk: mci0_clk {
282						#clock-cells = <0>;
283						reg = <10>;
284					};
285
286					udc_clk: udc_clk {
287						#clock-cells = <0>;
288						reg = <11>;
289					};
290
291					twi0_clk: twi0_clk {
292						reg = <12>;
293						#clock-cells = <0>;
294					};
295
296					spi0_clk: spi0_clk {
297						#clock-cells = <0>;
298						reg = <13>;
299					};
300
301					ssc0_clk: ssc0_clk {
302						#clock-cells = <0>;
303						reg = <14>;
304					};
305
306					ssc1_clk: ssc1_clk {
307						#clock-cells = <0>;
308						reg = <15>;
309					};
310
311					ssc2_clk: ssc2_clk {
312						#clock-cells = <0>;
313						reg = <16>;
314					};
315
316					tc0_clk: tc0_clk {
317						#clock-cells = <0>;
318						reg = <17>;
319					};
320
321					tc1_clk: tc1_clk {
322						#clock-cells = <0>;
323						reg = <18>;
324					};
325
326					tc2_clk: tc2_clk {
327						#clock-cells = <0>;
328						reg = <19>;
329					};
330
331					tc3_clk: tc3_clk {
332						#clock-cells = <0>;
333						reg = <20>;
334					};
335
336					tc4_clk: tc4_clk {
337						#clock-cells = <0>;
338						reg = <21>;
339					};
340
341					tc5_clk: tc5_clk {
342						#clock-cells = <0>;
343						reg = <22>;
344					};
345
346					ohci_clk: ohci_clk {
347						#clock-cells = <0>;
348						reg = <23>;
349					};
350
351					macb0_clk: macb0_clk {
352						#clock-cells = <0>;
353						reg = <24>;
354					};
355				};
356			};
357
358			st: timer@fffffd00 {
359				compatible = "atmel,at91rm9200-st", "syscon", "simple-mfd";
360				reg = <0xfffffd00 0x100>;
361				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
362
363				watchdog {
364					compatible = "atmel,at91rm9200-wdt";
365				};
366			};
367
368			rtc: rtc@fffffe00 {
369				compatible = "atmel,at91rm9200-rtc";
370				reg = <0xfffffe00 0x40>;
371				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
372				status = "disabled";
373			};
374
375			tcb0: timer@fffa0000 {
376				compatible = "atmel,at91rm9200-tcb";
377				reg = <0xfffa0000 0x100>;
378				interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0
379					      18 IRQ_TYPE_LEVEL_HIGH 0
380					      19 IRQ_TYPE_LEVEL_HIGH 0>;
381				clocks = <&tc0_clk>, <&tc1_clk>, <&tc2_clk>;
382				clock-names = "t0_clk", "t1_clk", "t2_clk";
383			};
384
385			tcb1: timer@fffa4000 {
386				compatible = "atmel,at91rm9200-tcb";
387				reg = <0xfffa4000 0x100>;
388				interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0
389					      21 IRQ_TYPE_LEVEL_HIGH 0
390					      22 IRQ_TYPE_LEVEL_HIGH 0>;
391				clocks = <&tc3_clk>, <&tc4_clk>, <&tc5_clk>;
392				clock-names = "t0_clk", "t1_clk", "t2_clk";
393			};
394
395			i2c0: i2c@fffb8000 {
396				compatible = "atmel,at91rm9200-i2c";
397				reg = <0xfffb8000 0x4000>;
398				interrupts = <12 IRQ_TYPE_LEVEL_HIGH 6>;
399				pinctrl-names = "default";
400				pinctrl-0 = <&pinctrl_twi>;
401				clocks = <&twi0_clk>;
402				#address-cells = <1>;
403				#size-cells = <0>;
404				status = "disabled";
405			};
406
407			mmc0: mmc@fffb4000 {
408				compatible = "atmel,hsmci";
409				reg = <0xfffb4000 0x4000>;
410				interrupts = <10 IRQ_TYPE_LEVEL_HIGH 0>;
411				clocks = <&mci0_clk>;
412				clock-names = "mci_clk";
413				#address-cells = <1>;
414				#size-cells = <0>;
415				pinctrl-names = "default";
416				status = "disabled";
417			};
418
419			ssc0: ssc@fffd0000 {
420				compatible = "atmel,at91rm9200-ssc";
421				reg = <0xfffd0000 0x4000>;
422				interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>;
423				pinctrl-names = "default";
424				pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
425				clocks = <&ssc0_clk>;
426				clock-names = "pclk";
427				status = "disable";
428			};
429
430			ssc1: ssc@fffd4000 {
431				compatible = "atmel,at91rm9200-ssc";
432				reg = <0xfffd4000 0x4000>;
433				interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>;
434				pinctrl-names = "default";
435				pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
436				clocks = <&ssc1_clk>;
437				clock-names = "pclk";
438				status = "disable";
439			};
440
441			ssc2: ssc@fffd8000 {
442				compatible = "atmel,at91rm9200-ssc";
443				reg = <0xfffd8000 0x4000>;
444				interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>;
445				pinctrl-names = "default";
446				pinctrl-0 = <&pinctrl_ssc2_tx &pinctrl_ssc2_rx>;
447				clocks = <&ssc2_clk>;
448				clock-names = "pclk";
449				status = "disable";
450			};
451
452			macb0: ethernet@fffbc000 {
453				compatible = "cdns,at91rm9200-emac", "cdns,emac";
454				reg = <0xfffbc000 0x4000>;
455				interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>;
456				phy-mode = "rmii";
457				pinctrl-names = "default";
458				pinctrl-0 = <&pinctrl_macb_rmii>;
459				clocks = <&macb0_clk>;
460				clock-names = "ether_clk";
461				status = "disabled";
462			};
463
464			pinctrl@fffff400 {
465				#address-cells = <1>;
466				#size-cells = <1>;
467				compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
468				ranges = <0xfffff400 0xfffff400 0x800>;
469
470				atmel,mux-mask = <
471					/*    A         B     */
472					 0xffffffff 0xffffffff  /* pioA */
473					 0xffffffff 0x083fffff  /* pioB */
474					 0xffff3fff 0x00000000  /* pioC */
475					 0x03ff87ff 0x0fffff80  /* pioD */
476					>;
477
478				/* shared pinctrl settings */
479				dbgu {
480					pinctrl_dbgu: dbgu-0 {
481						atmel,pins =
482							<AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PA30 periph A */
483							 AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;	/* PA31 periph with pullup */
484					};
485				};
486
487				uart0 {
488					pinctrl_uart0: uart0-0 {
489						atmel,pins =
490							<AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PA17 periph A */
491							 AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PA18 periph A */
492					};
493
494					pinctrl_uart0_cts: uart0_cts-0 {
495						atmel,pins =
496							<AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PA20 periph A */
497					};
498
499					pinctrl_uart0_rts: uart0_rts-0 {
500						atmel,pins =
501							<AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PA21 periph A */
502					};
503				};
504
505				uart1 {
506					pinctrl_uart1: uart1-0 {
507						atmel,pins =
508							<AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP	/* PB20 periph A with pullup */
509							 AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PB21 periph A */
510					};
511
512					pinctrl_uart1_rts: uart1_rts-0 {
513						atmel,pins =
514							<AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PB24 periph A */
515					};
516
517					pinctrl_uart1_cts: uart1_cts-0 {
518						atmel,pins =
519							<AT91_PIOB 26 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PB26 periph A */
520					};
521
522					pinctrl_uart1_dtr_dsr: uart1_dtr_dsr-0 {
523						atmel,pins =
524							<AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB19 periph A */
525							 AT91_PIOB 25 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PB25 periph A */
526					};
527
528					pinctrl_uart1_dcd: uart1_dcd-0 {
529						atmel,pins =
530							<AT91_PIOB 23 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PB23 periph A */
531					};
532
533					pinctrl_uart1_ri: uart1_ri-0 {
534						atmel,pins =
535							<AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PB18 periph A */
536					};
537				};
538
539				uart2 {
540					pinctrl_uart2: uart2-0 {
541						atmel,pins =
542							<AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PA22 periph A */
543							 AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;	/* PA23 periph A with pullup */
544					};
545
546					pinctrl_uart2_rts: uart2_rts-0 {
547						atmel,pins =
548							<AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* PA30 periph B */
549					};
550
551					pinctrl_uart2_cts: uart2_cts-0 {
552						atmel,pins =
553							<AT91_PIOA 31 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* PA31 periph B */
554					};
555				};
556
557				uart3 {
558					pinctrl_uart3: uart3-0 {
559						atmel,pins =
560							<AT91_PIOA 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP	/* PA5 periph B with pullup */
561							 AT91_PIOA 6 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* PA6 periph B */
562					};
563
564					pinctrl_uart3_rts: uart3_rts-0 {
565						atmel,pins =
566							<AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* PB0 periph B */
567					};
568
569					pinctrl_uart3_cts: uart3_cts-0 {
570						atmel,pins =
571							<AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* PB1 periph B */
572					};
573				};
574
575				nand {
576					pinctrl_nand: nand-0 {
577						atmel,pins =
578							<AT91_PIOC 2 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP	/* PC2 gpio RDY pin pull_up */
579							 AT91_PIOB 1 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;	/* PB1 gpio CD pin pull_up */
580					};
581				};
582
583				macb {
584					pinctrl_macb_rmii: macb_rmii-0 {
585						atmel,pins =
586							<AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PA7 periph A */
587							 AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PA8 periph A */
588							 AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PA9 periph A */
589							 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PA10 periph A */
590							 AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PA11 periph A */
591							 AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PA12 periph A */
592							 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PA13 periph A */
593							 AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PA14 periph A */
594							 AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PA15 periph A */
595							 AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PA16 periph A */
596					};
597
598					pinctrl_macb_rmii_mii: macb_rmii_mii-0 {
599						atmel,pins =
600							<AT91_PIOB 12 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PB12 periph B */
601							 AT91_PIOB 13 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PB13 periph B */
602							 AT91_PIOB 14 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PB14 periph B */
603							 AT91_PIOB 15 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PB15 periph B */
604							 AT91_PIOB 16 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PB16 periph B */
605							 AT91_PIOB 17 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PB17 periph B */
606							 AT91_PIOB 18 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PB18 periph B */
607							 AT91_PIOB 19 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* PB19 periph B */
608					};
609				};
610
611				mmc0 {
612					pinctrl_mmc0_clk: mmc0_clk-0 {
613						atmel,pins =
614							<AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PA27 periph A */
615					};
616
617					pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 {
618						atmel,pins =
619							<AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_PULL_UP	/* PA28 periph A with pullup */
620							 AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;	/* PA29 periph A with pullup */
621					};
622
623					pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
624						atmel,pins =
625							<AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_PULL_UP	/* PB3 periph B with pullup */
626							 AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_PULL_UP	/* PB4 periph B with pullup */
627							 AT91_PIOB 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>;	/* PB5 periph B with pullup */
628					};
629
630					pinctrl_mmc0_slot1_cmd_dat0: mmc0_slot1_cmd_dat0-0 {
631						atmel,pins =
632							<AT91_PIOA 8 AT91_PERIPH_B AT91_PINCTRL_PULL_UP	/* PA8 periph B with pullup */
633							 AT91_PIOA 9 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>;	/* PA9 periph B with pullup */
634					};
635
636					pinctrl_mmc0_slot1_dat1_3: mmc0_slot1_dat1_3-0 {
637						atmel,pins =
638							<AT91_PIOA 10 AT91_PERIPH_B AT91_PINCTRL_PULL_UP	/* PA10 periph B with pullup */
639							 AT91_PIOA 11 AT91_PERIPH_B AT91_PINCTRL_PULL_UP	/* PA11 periph B with pullup */
640							 AT91_PIOA 12 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>;	/* PA12 periph B with pullup */
641					};
642				};
643
644				ssc0 {
645					pinctrl_ssc0_tx: ssc0_tx-0 {
646						atmel,pins =
647							<AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB0 periph A */
648							 AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB1 periph A */
649							 AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PB2 periph A */
650					};
651
652					pinctrl_ssc0_rx: ssc0_rx-0 {
653						atmel,pins =
654							<AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB3 periph A */
655							 AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB4 periph A */
656							 AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PB5 periph A */
657					};
658				};
659
660				ssc1 {
661					pinctrl_ssc1_tx: ssc1_tx-0 {
662						atmel,pins =
663							<AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB6 periph A */
664							 AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB7 periph A */
665							 AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PB8 periph A */
666					};
667
668					pinctrl_ssc1_rx: ssc1_rx-0 {
669						atmel,pins =
670							<AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB9 periph A */
671							 AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB10 periph A */
672							 AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PB11 periph A */
673					};
674				};
675
676				ssc2 {
677					pinctrl_ssc2_tx: ssc2_tx-0 {
678						atmel,pins =
679							<AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB12 periph A */
680							 AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB13 periph A */
681							 AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PB14 periph A */
682					};
683
684					pinctrl_ssc2_rx: ssc2_rx-0 {
685						atmel,pins =
686							<AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB15 periph A */
687							 AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB16 periph A */
688							 AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PB17 periph A */
689					};
690				};
691
692				twi {
693					pinctrl_twi: twi-0 {
694						atmel,pins =
695							<AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_MULTI_DRIVE	/* PA25 periph A with multi drive */
696							 AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_MULTI_DRIVE>;	/* PA26 periph A with multi drive */
697					};
698
699					pinctrl_twi_gpio: twi_gpio-0 {
700						atmel,pins =
701							<AT91_PIOA 25 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE	/* PA25 GPIO with multi drive */
702							 AT91_PIOA 26 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>;	/* PA26 GPIO with multi drive */
703					};
704				};
705
706				tcb0 {
707					pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
708						atmel,pins = <AT91_PIOA 13 AT91_PERIPH_B AT91_PINCTRL_NONE>;
709					};
710
711					pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
712						atmel,pins = <AT91_PIOA 14 AT91_PERIPH_B AT91_PINCTRL_NONE>;
713					};
714
715					pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
716						atmel,pins = <AT91_PIOA 15 AT91_PERIPH_B AT91_PINCTRL_NONE>;
717					};
718
719					pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
720						atmel,pins = <AT91_PIOA 17 AT91_PERIPH_B AT91_PINCTRL_NONE>;
721					};
722
723					pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
724						atmel,pins = <AT91_PIOA 19 AT91_PERIPH_B AT91_PINCTRL_NONE>;
725					};
726
727					pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
728						atmel,pins = <AT91_PIOA 21 AT91_PERIPH_B AT91_PINCTRL_NONE>;
729					};
730
731					pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
732						atmel,pins = <AT91_PIOA 18 AT91_PERIPH_B AT91_PINCTRL_NONE>;
733					};
734
735					pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
736						atmel,pins = <AT91_PIOA 20 AT91_PERIPH_B AT91_PINCTRL_NONE>;
737					};
738
739					pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
740						atmel,pins = <AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE>;
741					};
742				};
743
744				tcb1 {
745					pinctrl_tcb1_tclk0: tcb1_tclk0-0 {
746						atmel,pins = <AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE>;
747					};
748
749					pinctrl_tcb1_tclk1: tcb1_tclk1-0 {
750						atmel,pins = <AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE>;
751					};
752
753					pinctrl_tcb1_tclk2: tcb1_tclk2-0 {
754						atmel,pins = <AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE>;
755					};
756
757					pinctrl_tcb1_tioa0: tcb1_tioa0-0 {
758						atmel,pins = <AT91_PIOB 6 AT91_PERIPH_B AT91_PINCTRL_NONE>;
759					};
760
761					pinctrl_tcb1_tioa1: tcb1_tioa1-0 {
762						atmel,pins = <AT91_PIOB 8 AT91_PERIPH_B AT91_PINCTRL_NONE>;
763					};
764
765					pinctrl_tcb1_tioa2: tcb1_tioa2-0 {
766						atmel,pins = <AT91_PIOB 10 AT91_PERIPH_B AT91_PINCTRL_NONE>;
767					};
768
769					pinctrl_tcb1_tiob0: tcb1_tiob0-0 {
770						atmel,pins = <AT91_PIOB 7 AT91_PERIPH_B AT91_PINCTRL_NONE>;
771					};
772
773					pinctrl_tcb1_tiob1: tcb1_tiob1-0 {
774						atmel,pins = <AT91_PIOB 9 AT91_PERIPH_B AT91_PINCTRL_NONE>;
775					};
776
777					pinctrl_tcb1_tiob2: tcb1_tiob2-0 {
778						atmel,pins = <AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>;
779					};
780				};
781
782				spi0 {
783					pinctrl_spi0: spi0-0 {
784						atmel,pins =
785							<AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PA0 periph A SPI0_MISO pin */
786							 AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PA1 periph A SPI0_MOSI pin */
787							 AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PA2 periph A SPI0_SPCK pin */
788					};
789				};
790
791				pioA: gpio@fffff400 {
792					compatible = "atmel,at91rm9200-gpio";
793					reg = <0xfffff400 0x200>;
794					interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
795					#gpio-cells = <2>;
796					gpio-controller;
797					interrupt-controller;
798					#interrupt-cells = <2>;
799					clocks = <&pioA_clk>;
800				};
801
802				pioB: gpio@fffff600 {
803					compatible = "atmel,at91rm9200-gpio";
804					reg = <0xfffff600 0x200>;
805					interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
806					#gpio-cells = <2>;
807					gpio-controller;
808					interrupt-controller;
809					#interrupt-cells = <2>;
810					clocks = <&pioB_clk>;
811				};
812
813				pioC: gpio@fffff800 {
814					compatible = "atmel,at91rm9200-gpio";
815					reg = <0xfffff800 0x200>;
816					interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
817					#gpio-cells = <2>;
818					gpio-controller;
819					interrupt-controller;
820					#interrupt-cells = <2>;
821					clocks = <&pioC_clk>;
822				};
823
824				pioD: gpio@fffffa00 {
825					compatible = "atmel,at91rm9200-gpio";
826					reg = <0xfffffa00 0x200>;
827					interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>;
828					#gpio-cells = <2>;
829					gpio-controller;
830					interrupt-controller;
831					#interrupt-cells = <2>;
832					clocks = <&pioD_clk>;
833				};
834			};
835
836			dbgu: serial@fffff200 {
837				compatible = "atmel,at91rm9200-dbgu", "atmel,at91rm9200-usart";
838				reg = <0xfffff200 0x200>;
839				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
840				pinctrl-names = "default";
841				pinctrl-0 = <&pinctrl_dbgu>;
842				clocks = <&mck>;
843				clock-names = "usart";
844				status = "disabled";
845			};
846
847			usart0: serial@fffc0000 {
848				compatible = "atmel,at91rm9200-usart";
849				reg = <0xfffc0000 0x200>;
850				interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>;
851				atmel,use-dma-rx;
852				atmel,use-dma-tx;
853				pinctrl-names = "default";
854				pinctrl-0 = <&pinctrl_uart0>;
855				clocks = <&usart0_clk>;
856				clock-names = "usart";
857				status = "disabled";
858			};
859
860			usart1: serial@fffc4000 {
861				compatible = "atmel,at91rm9200-usart";
862				reg = <0xfffc4000 0x200>;
863				interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
864				atmel,use-dma-rx;
865				atmel,use-dma-tx;
866				pinctrl-names = "default";
867				pinctrl-0 = <&pinctrl_uart1>;
868				clocks = <&usart1_clk>;
869				clock-names = "usart";
870				status = "disabled";
871			};
872
873			usart2: serial@fffc8000 {
874				compatible = "atmel,at91rm9200-usart";
875				reg = <0xfffc8000 0x200>;
876				interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
877				atmel,use-dma-rx;
878				atmel,use-dma-tx;
879				pinctrl-names = "default";
880				pinctrl-0 = <&pinctrl_uart2>;
881				clocks = <&usart2_clk>;
882				clock-names = "usart";
883				status = "disabled";
884			};
885
886			usart3: serial@fffcc000 {
887				compatible = "atmel,at91rm9200-usart";
888				reg = <0xfffcc000 0x200>;
889				interrupts = <23 IRQ_TYPE_LEVEL_HIGH 5>;
890				atmel,use-dma-rx;
891				atmel,use-dma-tx;
892				pinctrl-names = "default";
893				pinctrl-0 = <&pinctrl_uart3>;
894				clocks = <&usart3_clk>;
895				clock-names = "usart";
896				status = "disabled";
897			};
898
899			usb1: gadget@fffb0000 {
900				compatible = "atmel,at91rm9200-udc";
901				reg = <0xfffb0000 0x4000>;
902				interrupts = <11 IRQ_TYPE_LEVEL_HIGH 2>;
903				clocks = <&udc_clk>, <&udpck>;
904				clock-names = "pclk", "hclk";
905				status = "disabled";
906			};
907
908			spi0: spi@fffe0000 {
909				#address-cells = <1>;
910				#size-cells = <0>;
911				compatible = "atmel,at91rm9200-spi";
912				reg = <0xfffe0000 0x200>;
913				interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>;
914				pinctrl-names = "default";
915				pinctrl-0 = <&pinctrl_spi0>;
916				clocks = <&spi0_clk>;
917				clock-names = "spi_clk";
918				status = "disabled";
919			};
920		};
921
922		nand0: nand@40000000 {
923			compatible = "atmel,at91rm9200-nand";
924			#address-cells = <1>;
925			#size-cells = <1>;
926			reg = <0x40000000 0x10000000>;
927			atmel,nand-addr-offset = <21>;
928			atmel,nand-cmd-offset = <22>;
929			pinctrl-names = "default";
930			pinctrl-0 = <&pinctrl_nand>;
931			nand-ecc-mode = "soft";
932			gpios = <&pioC 2 GPIO_ACTIVE_HIGH
933				 0
934				 &pioB 1 GPIO_ACTIVE_HIGH
935				>;
936			status = "disabled";
937		};
938
939		usb0: ohci@00300000 {
940			compatible = "atmel,at91rm9200-ohci", "usb-ohci";
941			reg = <0x00300000 0x100000>;
942			interrupts = <23 IRQ_TYPE_LEVEL_HIGH 2>;
943			clocks = <&usb>, <&ohci_clk>, <&ohci_clk>, <&uhpck>;
944			clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck";
945			status = "disabled";
946		};
947	};
948
949	i2c@0 {
950		compatible = "i2c-gpio";
951		gpios = <&pioA 25 GPIO_ACTIVE_HIGH /* sda */
952			 &pioA 26 GPIO_ACTIVE_HIGH /* scl */
953			>;
954		i2c-gpio,sda-open-drain;
955		i2c-gpio,scl-open-drain;
956		i2c-gpio,delay-us = <2>;	/* ~100 kHz */
957		pinctrl-names = "default";
958		pinctrl-0 = <&pinctrl_twi_gpio>;
959		#address-cells = <1>;
960		#size-cells = <0>;
961		status = "disabled";
962	};
963};
964