1/*
2 * Device Tree Include file for Marvell Armada XP family SoC
3 *
4 * Copyright (C) 2012 Marvell
5 *
6 * Lior Amsalem <alior@marvell.com>
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 * Ben Dooks <ben.dooks@codethink.co.uk>
10 *
11 * This file is dual-licensed: you can use it either under the terms
12 * of the GPL or the X11 license, at your option. Note that this dual
13 * licensing only applies to this file, and not this project as a
14 * whole.
15 *
16 *  a) This file is free software; you can redistribute it and/or
17 *     modify it under the terms of the GNU General Public License as
18 *     published by the Free Software Foundation; either version 2 of the
19 *     License, or (at your option) any later version.
20 *
21 *     This file is distributed in the hope that it will be useful
22 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
23 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
24 *     GNU General Public License for more details.
25 *
26 * Or, alternatively
27 *
28 *  b) Permission is hereby granted, free of charge, to any person
29 *     obtaining a copy of this software and associated documentation
30 *     files (the "Software"), to deal in the Software without
31 *     restriction, including without limitation the rights to use
32 *     copy, modify, merge, publish, distribute, sublicense, and/or
33 *     sell copies of the Software, and to permit persons to whom the
34 *     Software is furnished to do so, subject to the following
35 *     conditions:
36 *
37 *     The above copyright notice and this permission notice shall be
38 *     included in all copies or substantial portions of the Software.
39 *
40 *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
41 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
42 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
43 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
44 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
45 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
46 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
47 *     OTHER DEALINGS IN THE SOFTWARE.
48 *
49 * Contains definitions specific to the Armada XP SoC that are not
50 * common to all Armada SoCs.
51 */
52
53#include "armada-370-xp.dtsi"
54
55/ {
56	model = "Marvell Armada XP family SoC";
57	compatible = "marvell,armadaxp", "marvell,armada-370-xp";
58
59	aliases {
60		serial2 = &uart2;
61		serial3 = &uart3;
62	};
63
64	soc {
65		compatible = "marvell,armadaxp-mbus", "simple-bus";
66
67		bootrom {
68			compatible = "marvell,bootrom";
69			reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
70		};
71
72		internal-regs {
73			sdramc@1400 {
74				compatible = "marvell,armada-xp-sdram-controller";
75				reg = <0x1400 0x500>;
76			};
77
78			L2: l2-cache {
79				compatible = "marvell,aurora-system-cache";
80				reg = <0x08000 0x1000>;
81				cache-id-part = <0x100>;
82				cache-level = <2>;
83				cache-unified;
84				wt-override;
85			};
86
87			spi0: spi@10600 {
88				pinctrl-0 = <&spi0_pins>;
89				pinctrl-names = "default";
90			};
91
92			i2c0: i2c@11000 {
93				compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
94				reg = <0x11000 0x100>;
95			};
96
97			i2c1: i2c@11100 {
98				compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
99				reg = <0x11100 0x100>;
100			};
101
102			uart2: serial@12200 {
103				compatible = "snps,dw-apb-uart";
104				pinctrl-0 = <&uart2_pins>;
105				pinctrl-names = "default";
106				reg = <0x12200 0x100>;
107				reg-shift = <2>;
108				interrupts = <43>;
109				reg-io-width = <1>;
110				clocks = <&coreclk 0>;
111				status = "disabled";
112			};
113
114			uart3: serial@12300 {
115				compatible = "snps,dw-apb-uart";
116				pinctrl-0 = <&uart3_pins>;
117				pinctrl-names = "default";
118				reg = <0x12300 0x100>;
119				reg-shift = <2>;
120				interrupts = <44>;
121				reg-io-width = <1>;
122				clocks = <&coreclk 0>;
123				status = "disabled";
124			};
125
126			system-controller@18200 {
127				compatible = "marvell,armada-370-xp-system-controller";
128				reg = <0x18200 0x500>;
129			};
130
131			gateclk: clock-gating-control@18220 {
132				compatible = "marvell,armada-xp-gating-clock";
133				reg = <0x18220 0x4>;
134				clocks = <&coreclk 0>;
135				#clock-cells = <1>;
136			};
137
138			coreclk: mvebu-sar@18230 {
139				compatible = "marvell,armada-xp-core-clock";
140				reg = <0x18230 0x08>;
141				#clock-cells = <1>;
142			};
143
144			thermal@182b0 {
145				compatible = "marvell,armadaxp-thermal";
146				reg = <0x182b0 0x4
147					0x184d0 0x4>;
148				status = "okay";
149			};
150
151			cpuclk: clock-complex@18700 {
152				#clock-cells = <1>;
153				compatible = "marvell,armada-xp-cpu-clock";
154				reg = <0x18700 0x24>, <0x1c054 0x10>;
155				clocks = <&coreclk 1>;
156			};
157
158			interrupt-controller@20a00 {
159			      reg = <0x20a00 0x2d0>, <0x21070 0x58>;
160			};
161
162			timer@20300 {
163				compatible = "marvell,armada-xp-timer";
164				clocks = <&coreclk 2>, <&refclk>;
165				clock-names = "nbclk", "fixed";
166			};
167
168			watchdog@20300 {
169				compatible = "marvell,armada-xp-wdt";
170				clocks = <&coreclk 2>, <&refclk>;
171				clock-names = "nbclk", "fixed";
172			};
173
174			cpurst@20800 {
175				compatible = "marvell,armada-370-cpu-reset";
176				reg = <0x20800 0x20>;
177			};
178
179			eth2: ethernet@30000 {
180				compatible = "marvell,armada-xp-neta";
181				reg = <0x30000 0x4000>;
182				interrupts = <12>;
183				clocks = <&gateclk 2>;
184				status = "disabled";
185			};
186
187			usb@50000 {
188				clocks = <&gateclk 18>;
189			};
190
191			usb@51000 {
192				clocks = <&gateclk 19>;
193			};
194
195			usb@52000 {
196				compatible = "marvell,orion-ehci";
197				reg = <0x52000 0x500>;
198				interrupts = <47>;
199				clocks = <&gateclk 20>;
200				status = "disabled";
201			};
202
203			xor@60900 {
204				compatible = "marvell,orion-xor";
205				reg = <0x60900 0x100
206				       0x60b00 0x100>;
207				clocks = <&gateclk 22>;
208				status = "okay";
209
210				xor10 {
211					interrupts = <51>;
212					dmacap,memcpy;
213					dmacap,xor;
214				};
215				xor11 {
216					interrupts = <52>;
217					dmacap,memcpy;
218					dmacap,xor;
219					dmacap,memset;
220				};
221			};
222
223			ethernet@70000 {
224				compatible = "marvell,armada-xp-neta";
225			};
226
227			ethernet@74000 {
228				compatible = "marvell,armada-xp-neta";
229			};
230
231			xor@f0900 {
232				compatible = "marvell,orion-xor";
233				reg = <0xF0900 0x100
234				       0xF0B00 0x100>;
235				clocks = <&gateclk 28>;
236				status = "okay";
237
238				xor00 {
239					interrupts = <94>;
240					dmacap,memcpy;
241					dmacap,xor;
242				};
243				xor01 {
244					interrupts = <95>;
245					dmacap,memcpy;
246					dmacap,xor;
247					dmacap,memset;
248				};
249			};
250		};
251	};
252
253	clocks {
254		/* 25 MHz reference crystal */
255		refclk: oscillator {
256			compatible = "fixed-clock";
257			#clock-cells = <0>;
258			clock-frequency = <25000000>;
259		};
260	};
261};
262
263&pinctrl {
264	ge0_gmii_pins: ge0-gmii-pins {
265		marvell,pins =
266		     "mpp0",  "mpp1",  "mpp2",  "mpp3",
267		     "mpp4",  "mpp5",  "mpp6",  "mpp7",
268		     "mpp8",  "mpp9",  "mpp10", "mpp11",
269		     "mpp12", "mpp13", "mpp14", "mpp15",
270		     "mpp16", "mpp17", "mpp18", "mpp19",
271		     "mpp20", "mpp21", "mpp22", "mpp23";
272		marvell,function = "ge0";
273	};
274
275	ge0_rgmii_pins: ge0-rgmii-pins {
276		marvell,pins =
277		     "mpp0", "mpp1", "mpp2", "mpp3",
278		     "mpp4", "mpp5", "mpp6", "mpp7",
279		     "mpp8", "mpp9", "mpp10", "mpp11";
280		marvell,function = "ge0";
281	};
282
283	ge1_rgmii_pins: ge1-rgmii-pins {
284		marvell,pins =
285		     "mpp12", "mpp13", "mpp14", "mpp15",
286		     "mpp16", "mpp17", "mpp18", "mpp19",
287		     "mpp20", "mpp21", "mpp22", "mpp23";
288		marvell,function = "ge1";
289	};
290
291	sdio_pins: sdio-pins {
292		marvell,pins = "mpp30", "mpp31", "mpp32",
293			       "mpp33", "mpp34", "mpp35";
294		marvell,function = "sd0";
295	};
296
297	spi0_pins: spi0-pins {
298		marvell,pins = "mpp36", "mpp37",
299			       "mpp38", "mpp39";
300		marvell,function = "spi";
301	};
302
303	uart2_pins: uart2-pins {
304		marvell,pins = "mpp42", "mpp43";
305		marvell,function = "uart2";
306	};
307
308	uart3_pins: uart3-pins {
309		marvell,pins = "mpp44", "mpp45";
310		marvell,function = "uart3";
311	};
312};
313