1/*
2 * Device Tree file for Marvell Armada 375 evaluation board
3 * (DB-88F6720)
4 *
5 *  Copyright (C) 2014 Marvell
6 *
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 *
10 * This file is dual-licensed: you can use it either under the terms
11 * of the GPL or the X11 license, at your option. Note that this dual
12 * licensing only applies to this file, and not this project as a
13 * whole.
14 *
15 *  a) This file is free software; you can redistribute it and/or
16 *     modify it under the terms of the GNU General Public License as
17 *     published by the Free Software Foundation; either version 2 of the
18 *     License, or (at your option) any later version.
19 *
20 *     This file is distributed in the hope that it will be useful
21 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
22 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
23 *     GNU General Public License for more details.
24 *
25 * Or, alternatively
26 *
27 *  b) Permission is hereby granted, free of charge, to any person
28 *     obtaining a copy of this software and associated documentation
29 *     files (the "Software"), to deal in the Software without
30 *     restriction, including without limitation the rights to use
31 *     copy, modify, merge, publish, distribute, sublicense, and/or
32 *     sell copies of the Software, and to permit persons to whom the
33 *     Software is furnished to do so, subject to the following
34 *     conditions:
35 *
36 *     The above copyright notice and this permission notice shall be
37 *     included in all copies or substantial portions of the Software.
38 *
39 *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
40 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
41 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
42 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
43 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
44 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
45 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
46 *     OTHER DEALINGS IN THE SOFTWARE.
47 */
48
49/dts-v1/;
50#include <dt-bindings/gpio/gpio.h>
51#include "armada-375.dtsi"
52
53/ {
54	model = "Marvell Armada 375 Development Board";
55	compatible = "marvell,a375-db", "marvell,armada375";
56
57	chosen {
58		stdout-path = "serial0:115200n8";
59	};
60
61	memory {
62		device_type = "memory";
63		reg = <0x00000000 0x40000000>; /* 1 GB */
64	};
65
66	soc {
67		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
68			  MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
69
70		internal-regs {
71			spi@10600 {
72				pinctrl-0 = <&spi0_pins>;
73				pinctrl-names = "default";
74				/*
75				 * SPI conflicts with NAND, so we disable it
76				 * here, and select NAND as the enabled device
77				 * by default.
78				 */
79				status = "disabled";
80
81				spi-flash@0 {
82					#address-cells = <1>;
83					#size-cells = <1>;
84					compatible = "n25q128a13";
85					reg = <0>; /* Chip select 0 */
86					spi-max-frequency = <108000000>;
87				};
88			};
89
90			i2c@11000 {
91				status = "okay";
92				clock-frequency = <100000>;
93				pinctrl-0 = <&i2c0_pins>;
94				pinctrl-names = "default";
95			};
96
97			i2c@11100 {
98				status = "okay";
99				clock-frequency = <100000>;
100				pinctrl-0 = <&i2c1_pins>;
101				pinctrl-names = "default";
102			};
103
104			serial@12000 {
105				status = "okay";
106			};
107
108			pinctrl {
109				sdio_st_pins: sdio-st-pins {
110					marvell,pins = "mpp44", "mpp45";
111					marvell,function = "gpio";
112				};
113			};
114
115			sata@a0000 {
116				status = "okay";
117				nr-ports = <2>;
118			};
119
120			nand: nand@d0000 {
121				pinctrl-0 = <&nand_pins>;
122				pinctrl-names = "default";
123				status = "okay";
124				num-cs = <1>;
125				marvell,nand-keep-config;
126				marvell,nand-enable-arbiter;
127				nand-on-flash-bbt;
128				nand-ecc-strength = <4>;
129				nand-ecc-step-size = <512>;
130
131				partition@0 {
132					label = "U-Boot";
133					reg = <0 0x800000>;
134				};
135				partition@800000 {
136					label = "Linux";
137					reg = <0x800000 0x800000>;
138				};
139				partition@1000000 {
140					label = "Filesystem";
141					reg = <0x1000000 0x3f000000>;
142				};
143			};
144
145			usb@54000 {
146				status = "okay";
147			};
148
149			usb3@58000 {
150				status = "okay";
151			};
152
153			mvsdio@d4000 {
154				pinctrl-0 = <&sdio_pins &sdio_st_pins>;
155				pinctrl-names = "default";
156				status = "okay";
157				cd-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
158				wp-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
159			};
160
161			mdio {
162				phy0: ethernet-phy@0 {
163					reg = <0>;
164				};
165
166				phy3: ethernet-phy@3 {
167					reg = <3>;
168				};
169			};
170
171			ethernet@f0000 {
172				status = "okay";
173
174				eth0@c4000 {
175					status = "okay";
176					phy = <&phy0>;
177					phy-mode = "rgmii-id";
178				};
179
180				eth1@c5000 {
181					status = "okay";
182					phy = <&phy3>;
183					phy-mode = "gmii";
184				};
185			};
186		};
187
188		pcie-controller {
189			status = "okay";
190			/*
191			 * The two PCIe units are accessible through
192			 * standard PCIe slots on the board.
193			 */
194			pcie@1,0 {
195				/* Port 0, Lane 0 */
196				status = "okay";
197			};
198			pcie@2,0 {
199				/* Port 1, Lane 0 */
200				status = "okay";
201			};
202		};
203	};
204};
205