1/*
2 * Device Tree Include file for Marvell Armada 370 family SoC
3 *
4 * Copyright (C) 2012 Marvell
5 *
6 * Lior Amsalem <alior@marvell.com>
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 *
10 * This file is dual-licensed: you can use it either under the terms
11 * of the GPL or the X11 license, at your option. Note that this dual
12 * licensing only applies to this file, and not this project as a
13 * whole.
14 *
15 *  a) This file is free software; you can redistribute it and/or
16 *     modify it under the terms of the GNU General Public License as
17 *     published by the Free Software Foundation; either version 2 of the
18 *     License, or (at your option) any later version.
19 *
20 *     This file is distributed in the hope that it will be useful
21 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
22 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
23 *     GNU General Public License for more details.
24 *
25 * Or, alternatively
26 *
27 *  b) Permission is hereby granted, free of charge, to any person
28 *     obtaining a copy of this software and associated documentation
29 *     files (the "Software"), to deal in the Software without
30 *     restriction, including without limitation the rights to use
31 *     copy, modify, merge, publish, distribute, sublicense, and/or
32 *     sell copies of the Software, and to permit persons to whom the
33 *     Software is furnished to do so, subject to the following
34 *     conditions:
35 *
36 *     The above copyright notice and this permission notice shall be
37 *     included in all copies or substantial portions of the Software.
38 *
39 *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
40 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
41 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
42 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
43 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
44 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
45 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
46 *     OTHER DEALINGS IN THE SOFTWARE.
47 *
48 * Contains definitions specific to the Armada 370 SoC that are not
49 * common to all Armada SoCs.
50 */
51
52#include "armada-370-xp.dtsi"
53/include/ "skeleton.dtsi"
54
55/ {
56	model = "Marvell Armada 370 family SoC";
57	compatible = "marvell,armada370", "marvell,armada-370-xp";
58
59	aliases {
60		gpio0 = &gpio0;
61		gpio1 = &gpio1;
62		gpio2 = &gpio2;
63	};
64
65	soc {
66		compatible = "marvell,armada370-mbus", "simple-bus";
67
68		bootrom {
69			compatible = "marvell,bootrom";
70			reg = <MBUS_ID(0x01, 0xe0) 0 0x100000>;
71		};
72
73		pcie-controller {
74			compatible = "marvell,armada-370-pcie";
75			status = "disabled";
76			device_type = "pci";
77
78			#address-cells = <3>;
79			#size-cells = <2>;
80
81			msi-parent = <&mpic>;
82			bus-range = <0x00 0xff>;
83
84			ranges =
85			       <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
86				0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
87				0x82000000 0x1 0     MBUS_ID(0x04, 0xe8) 0       1 0 /* Port 0.0 MEM */
88				0x81000000 0x1 0     MBUS_ID(0x04, 0xe0) 0       1 0 /* Port 0.0 IO  */
89				0x82000000 0x2 0     MBUS_ID(0x08, 0xe8) 0       1 0 /* Port 1.0 MEM */
90				0x81000000 0x2 0     MBUS_ID(0x08, 0xe0) 0       1 0 /* Port 1.0 IO  */>;
91
92			pcie@1,0 {
93				device_type = "pci";
94				assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
95				reg = <0x0800 0 0 0 0>;
96				#address-cells = <3>;
97				#size-cells = <2>;
98				#interrupt-cells = <1>;
99                                ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
100                                          0x81000000 0 0 0x81000000 0x1 0 1 0>;
101				interrupt-map-mask = <0 0 0 0>;
102				interrupt-map = <0 0 0 0 &mpic 58>;
103				marvell,pcie-port = <0>;
104				marvell,pcie-lane = <0>;
105				clocks = <&gateclk 5>;
106				status = "disabled";
107			};
108
109			pcie@2,0 {
110				device_type = "pci";
111				assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
112				reg = <0x1000 0 0 0 0>;
113				#address-cells = <3>;
114				#size-cells = <2>;
115				#interrupt-cells = <1>;
116                                ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
117                                          0x81000000 0 0 0x81000000 0x2 0 1 0>;
118				interrupt-map-mask = <0 0 0 0>;
119				interrupt-map = <0 0 0 0 &mpic 62>;
120				marvell,pcie-port = <1>;
121				marvell,pcie-lane = <0>;
122				clocks = <&gateclk 9>;
123				status = "disabled";
124			};
125		};
126
127		internal-regs {
128			L2: l2-cache {
129				compatible = "marvell,aurora-outer-cache";
130				reg = <0x08000 0x1000>;
131				cache-id-part = <0x100>;
132				cache-level = <2>;
133				cache-unified;
134				wt-override;
135			};
136
137			/*
138			 * Default SPI pinctrl setting, can be overwritten on
139			 * board level if a different configuration is used.
140			 */
141			spi0: spi@10600 {
142				pinctrl-0 = <&spi0_pins1>;
143				pinctrl-names = "default";
144			};
145
146			spi1: spi@10680 {
147				pinctrl-0 = <&spi1_pins>;
148				pinctrl-names = "default";
149			};
150
151			i2c0: i2c@11000 {
152				reg = <0x11000 0x20>;
153			};
154
155			i2c1: i2c@11100 {
156				reg = <0x11100 0x20>;
157			};
158
159			gpio0: gpio@18100 {
160				compatible = "marvell,orion-gpio";
161				reg = <0x18100 0x40>;
162				ngpios = <32>;
163				gpio-controller;
164				#gpio-cells = <2>;
165				interrupt-controller;
166				#interrupt-cells = <2>;
167				interrupts = <82>, <83>, <84>, <85>;
168			};
169
170			gpio1: gpio@18140 {
171				compatible = "marvell,orion-gpio";
172				reg = <0x18140 0x40>;
173				ngpios = <32>;
174				gpio-controller;
175				#gpio-cells = <2>;
176				interrupt-controller;
177				#interrupt-cells = <2>;
178				interrupts = <87>, <88>, <89>, <90>;
179			};
180
181			gpio2: gpio@18180 {
182				compatible = "marvell,orion-gpio";
183				reg = <0x18180 0x40>;
184				ngpios = <2>;
185				gpio-controller;
186				#gpio-cells = <2>;
187				interrupt-controller;
188				#interrupt-cells = <2>;
189				interrupts = <91>;
190			};
191
192			/*
193			 * Default UART pinctrl setting without RTS/CTS, can
194			 * be overwritten on board level if a different
195			 * configuration is used.
196			 */
197			uart0: serial@12000 {
198				pinctrl-0 = <&uart0_pins>;
199				pinctrl-names = "default";
200			};
201
202			uart1: serial@12100 {
203				pinctrl-0 = <&uart1_pins>;
204				pinctrl-names = "default";
205			};
206
207			system-controller@18200 {
208				compatible = "marvell,armada-370-xp-system-controller";
209				reg = <0x18200 0x100>;
210			};
211
212			gateclk: clock-gating-control@18220 {
213				compatible = "marvell,armada-370-gating-clock";
214				reg = <0x18220 0x4>;
215				clocks = <&coreclk 0>;
216				#clock-cells = <1>;
217			};
218
219			coreclk: mvebu-sar@18230 {
220				compatible = "marvell,armada-370-core-clock";
221				reg = <0x18230 0x08>;
222				#clock-cells = <1>;
223			};
224
225			thermal@18300 {
226				compatible = "marvell,armada370-thermal";
227				reg = <0x18300 0x4
228					0x18304 0x4>;
229				status = "okay";
230			};
231
232			sscg@18330 {
233				reg = <0x18330 0x4>;
234			};
235
236			interrupt-controller@20a00 {
237				reg = <0x20a00 0x1d0>, <0x21870 0x58>;
238			};
239
240			timer@20300 {
241				compatible = "marvell,armada-370-timer";
242				clocks = <&coreclk 2>;
243			};
244
245			watchdog@20300 {
246				compatible = "marvell,armada-370-wdt";
247				clocks = <&coreclk 2>;
248			};
249
250			cpurst@20800 {
251				compatible = "marvell,armada-370-cpu-reset";
252				reg = <0x20800 0x8>;
253			};
254
255			audio_controller: audio-controller@30000 {
256				#sound-dai-cells = <1>;
257				compatible = "marvell,armada370-audio";
258				reg = <0x30000 0x4000>;
259				interrupts = <93>;
260				clocks = <&gateclk 0>;
261				clock-names = "internal";
262				status = "disabled";
263			};
264
265			usb@50000 {
266				clocks = <&coreclk 0>;
267			};
268
269			usb@51000 {
270				clocks = <&coreclk 0>;
271			};
272
273			xor@60800 {
274				compatible = "marvell,orion-xor";
275				reg = <0x60800 0x100
276				       0x60A00 0x100>;
277				status = "okay";
278
279				xor00 {
280					interrupts = <51>;
281					dmacap,memcpy;
282					dmacap,xor;
283				};
284				xor01 {
285					interrupts = <52>;
286					dmacap,memcpy;
287					dmacap,xor;
288					dmacap,memset;
289				};
290			};
291
292			xor@60900 {
293				compatible = "marvell,orion-xor";
294				reg = <0x60900 0x100
295				       0x60b00 0x100>;
296				status = "okay";
297
298				xor10 {
299					interrupts = <94>;
300					dmacap,memcpy;
301					dmacap,xor;
302				};
303				xor11 {
304					interrupts = <95>;
305					dmacap,memcpy;
306					dmacap,xor;
307					dmacap,memset;
308				};
309			};
310
311			ethernet@70000 {
312				compatible = "marvell,armada-370-neta";
313			};
314
315			ethernet@74000 {
316				compatible = "marvell,armada-370-neta";
317			};
318		};
319	};
320};
321
322&pinctrl {
323	compatible = "marvell,mv88f6710-pinctrl";
324
325	spi0_pins1: spi0-pins1 {
326		marvell,pins = "mpp33", "mpp34",
327			       "mpp35", "mpp36";
328		marvell,function = "spi0";
329	};
330
331	spi0_pins2: spi0_pins2 {
332		marvell,pins = "mpp32", "mpp63",
333			       "mpp64", "mpp65";
334		marvell,function = "spi0";
335	};
336
337	spi1_pins: spi1-pins {
338		marvell,pins = "mpp49", "mpp50",
339			       "mpp51", "mpp52";
340		marvell,function = "spi1";
341	};
342
343	uart0_pins: uart0-pins {
344		marvell,pins = "mpp0", "mpp1";
345		marvell,function = "uart0";
346	};
347
348	uart1_pins: uart1-pins {
349		marvell,pins = "mpp41", "mpp42";
350		marvell,function = "uart1";
351	};
352
353	sdio_pins1: sdio-pins1 {
354		marvell,pins = "mpp9",  "mpp11", "mpp12",
355				"mpp13", "mpp14", "mpp15";
356		marvell,function = "sd0";
357	};
358
359	sdio_pins2: sdio-pins2 {
360		marvell,pins = "mpp47", "mpp48", "mpp49",
361				"mpp50", "mpp51", "mpp52";
362		marvell,function = "sd0";
363	};
364
365	sdio_pins3: sdio-pins3 {
366		marvell,pins = "mpp48", "mpp49", "mpp50",
367				"mpp51", "mpp52", "mpp53";
368		marvell,function = "sd0";
369	};
370
371	i2c0_pins: i2c0-pins {
372		marvell,pins = "mpp2", "mpp3";
373		marvell,function = "i2c0";
374	};
375
376	i2s_pins1: i2s-pins1 {
377		marvell,pins = "mpp5", "mpp6", "mpp7",
378			       "mpp8", "mpp9", "mpp10",
379			       "mpp12", "mpp13";
380		marvell,function = "audio";
381	};
382
383	i2s_pins2: i2s-pins2 {
384		marvell,pins = "mpp49", "mpp47", "mpp50",
385			       "mpp59", "mpp57", "mpp61",
386			       "mpp62", "mpp60", "mpp58";
387		marvell,function = "audio";
388	};
389
390	mdio_pins: mdio-pins {
391		marvell,pins = "mpp17", "mpp18";
392		marvell,function = "ge";
393	};
394
395	ge0_rgmii_pins: ge0-rgmii-pins {
396		marvell,pins = "mpp5", "mpp6", "mpp7", "mpp8",
397			       "mpp9", "mpp10", "mpp11", "mpp12",
398			       "mpp13", "mpp14", "mpp15", "mpp16";
399		marvell,function = "ge0";
400	};
401
402	ge1_rgmii_pins: ge1-rgmii-pins {
403		marvell,pins = "mpp19", "mpp20", "mpp21", "mpp22",
404			       "mpp23", "mpp24", "mpp25", "mpp26",
405			       "mpp27", "mpp28", "mpp29", "mpp30";
406		marvell,function = "ge1";
407	};
408};
409