1/*
2 * Device Tree Include file for Marvell Armada 370 and Armada XP SoC
3 *
4 * Copyright (C) 2012 Marvell
5 *
6 * Lior Amsalem <alior@marvell.com>
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 * Ben Dooks <ben.dooks@codethink.co.uk>
10 *
11 * This file is dual-licensed: you can use it either under the terms
12 * of the GPL or the X11 license, at your option. Note that this dual
13 * licensing only applies to this file, and not this project as a
14 * whole.
15 *
16 *  a) This file is free software; you can redistribute it and/or
17 *     modify it under the terms of the GNU General Public License as
18 *     published by the Free Software Foundation; either version 2 of the
19 *     License, or (at your option) any later version.
20 *
21 *     This file is distributed in the hope that it will be useful
22 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
23 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
24 *     GNU General Public License for more details.
25 *
26 * Or, alternatively
27 *
28 *  b) Permission is hereby granted, free of charge, to any person
29 *     obtaining a copy of this software and associated documentation
30 *     files (the "Software"), to deal in the Software without
31 *     restriction, including without limitation the rights to use
32 *     copy, modify, merge, publish, distribute, sublicense, and/or
33 *     sell copies of the Software, and to permit persons to whom the
34 *     Software is furnished to do so, subject to the following
35 *     conditions:
36 *
37 *     The above copyright notice and this permission notice shall be
38 *     included in all copies or substantial portions of the Software.
39 *
40 *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
41 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
42 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
43 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
44 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
45 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
46 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
47 *     OTHER DEALINGS IN THE SOFTWARE.
48 *
49 * This file contains the definitions that are common to the Armada
50 * 370 and Armada XP SoC.
51 */
52
53/include/ "skeleton64.dtsi"
54
55#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
56
57/ {
58	model = "Marvell Armada 370 and XP SoC";
59	compatible = "marvell,armada-370-xp";
60
61	aliases {
62		serial0 = &uart0;
63		serial1 = &uart1;
64	};
65
66	cpus {
67		#address-cells = <1>;
68		#size-cells = <0>;
69		cpu@0 {
70			compatible = "marvell,sheeva-v7";
71			device_type = "cpu";
72			reg = <0>;
73		};
74	};
75
76	pmu {
77		compatible = "arm,cortex-a9-pmu";
78		interrupts-extended = <&mpic 3>;
79	};
80
81	soc {
82		#address-cells = <2>;
83		#size-cells = <1>;
84		controller = <&mbusc>;
85		interrupt-parent = <&mpic>;
86		pcie-mem-aperture = <0xf8000000 0x7e00000>;
87		pcie-io-aperture  = <0xffe00000 0x100000>;
88
89		devbus-bootcs {
90			compatible = "marvell,mvebu-devbus";
91			reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
92			ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
93			#address-cells = <1>;
94			#size-cells = <1>;
95			clocks = <&coreclk 0>;
96			status = "disabled";
97		};
98
99		devbus-cs0 {
100			compatible = "marvell,mvebu-devbus";
101			reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
102			ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
103			#address-cells = <1>;
104			#size-cells = <1>;
105			clocks = <&coreclk 0>;
106			status = "disabled";
107		};
108
109		devbus-cs1 {
110			compatible = "marvell,mvebu-devbus";
111			reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
112			ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
113			#address-cells = <1>;
114			#size-cells = <1>;
115			clocks = <&coreclk 0>;
116			status = "disabled";
117		};
118
119		devbus-cs2 {
120			compatible = "marvell,mvebu-devbus";
121			reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
122			ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
123			#address-cells = <1>;
124			#size-cells = <1>;
125			clocks = <&coreclk 0>;
126			status = "disabled";
127		};
128
129		devbus-cs3 {
130			compatible = "marvell,mvebu-devbus";
131			reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
132			ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
133			#address-cells = <1>;
134			#size-cells = <1>;
135			clocks = <&coreclk 0>;
136			status = "disabled";
137		};
138
139		internal-regs {
140			compatible = "simple-bus";
141			#address-cells = <1>;
142			#size-cells = <1>;
143			ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
144
145			rtc@10300 {
146				compatible = "marvell,orion-rtc";
147				reg = <0x10300 0x20>;
148				interrupts = <50>;
149			};
150
151			spi0: spi@10600 {
152				compatible = "marvell,armada-370-spi", "marvell,orion-spi";
153				reg = <0x10600 0x28>;
154				#address-cells = <1>;
155				#size-cells = <0>;
156				cell-index = <0>;
157				interrupts = <30>;
158				clocks = <&coreclk 0>;
159				status = "disabled";
160			};
161
162			spi1: spi@10680 {
163				compatible = "marvell,armada-370-spi", "marvell,orion-spi";
164				reg = <0x10680 0x28>;
165				#address-cells = <1>;
166				#size-cells = <0>;
167				cell-index = <1>;
168				interrupts = <92>;
169				clocks = <&coreclk 0>;
170				status = "disabled";
171			};
172
173			i2c0: i2c@11000 {
174				compatible = "marvell,mv64xxx-i2c";
175				#address-cells = <1>;
176				#size-cells = <0>;
177				interrupts = <31>;
178				timeout-ms = <1000>;
179				clocks = <&coreclk 0>;
180				status = "disabled";
181			};
182
183			i2c1: i2c@11100 {
184				compatible = "marvell,mv64xxx-i2c";
185				#address-cells = <1>;
186				#size-cells = <0>;
187				interrupts = <32>;
188				timeout-ms = <1000>;
189				clocks = <&coreclk 0>;
190				status = "disabled";
191			};
192
193			uart0: serial@12000 {
194				compatible = "snps,dw-apb-uart";
195				reg = <0x12000 0x100>;
196				reg-shift = <2>;
197				interrupts = <41>;
198				reg-io-width = <1>;
199				clocks = <&coreclk 0>;
200				status = "disabled";
201			};
202
203			uart1: serial@12100 {
204				compatible = "snps,dw-apb-uart";
205				reg = <0x12100 0x100>;
206				reg-shift = <2>;
207				interrupts = <42>;
208				reg-io-width = <1>;
209				clocks = <&coreclk 0>;
210				status = "disabled";
211			};
212
213			pinctrl: pin-ctrl@18000 {
214				reg = <0x18000 0x38>;
215			};
216
217			coredivclk: corediv-clock@18740 {
218				compatible = "marvell,armada-370-corediv-clock";
219				reg = <0x18740 0xc>;
220				#clock-cells = <1>;
221				clocks = <&mainpll>;
222				clock-output-names = "nand";
223			};
224
225			mbusc: mbus-controller@20000 {
226				compatible = "marvell,mbus-controller";
227				reg = <0x20000 0x100>, <0x20180 0x20>,
228				      <0x20250 0x8>;
229			};
230
231			mpic: interrupt-controller@20a00 {
232				compatible = "marvell,mpic";
233				#interrupt-cells = <1>;
234				#size-cells = <1>;
235				interrupt-controller;
236				msi-controller;
237			};
238
239			coherency-fabric@20200 {
240				compatible = "marvell,coherency-fabric";
241				reg = <0x20200 0xb0>, <0x21010 0x1c>;
242			};
243
244			timer@20300 {
245				reg = <0x20300 0x30>, <0x21040 0x30>;
246				interrupts = <37>, <38>, <39>, <40>, <5>, <6>;
247			};
248
249			watchdog@20300 {
250				reg = <0x20300 0x34>, <0x20704 0x4>;
251			};
252
253			pmsu@22000 {
254				compatible = "marvell,armada-370-pmsu";
255				reg = <0x22000 0x1000>;
256			};
257
258			usb@50000 {
259				compatible = "marvell,orion-ehci";
260				reg = <0x50000 0x500>;
261				interrupts = <45>;
262				status = "disabled";
263			};
264
265			usb@51000 {
266				compatible = "marvell,orion-ehci";
267				reg = <0x51000 0x500>;
268				interrupts = <46>;
269				status = "disabled";
270			};
271
272			eth0: ethernet@70000 {
273				reg = <0x70000 0x4000>;
274				interrupts = <8>;
275				clocks = <&gateclk 4>;
276				status = "disabled";
277			};
278
279			mdio: mdio {
280				#address-cells = <1>;
281				#size-cells = <0>;
282				compatible = "marvell,orion-mdio";
283				reg = <0x72004 0x4>;
284				clocks = <&gateclk 4>;
285			};
286
287			eth1: ethernet@74000 {
288				reg = <0x74000 0x4000>;
289				interrupts = <10>;
290				clocks = <&gateclk 3>;
291				status = "disabled";
292			};
293
294			sata@a0000 {
295				compatible = "marvell,armada-370-sata";
296				reg = <0xa0000 0x5000>;
297				interrupts = <55>;
298				clocks = <&gateclk 15>, <&gateclk 30>;
299				clock-names = "0", "1";
300				status = "disabled";
301			};
302
303			nand@d0000 {
304				compatible = "marvell,armada370-nand";
305				reg = <0xd0000 0x54>;
306				#address-cells = <1>;
307				#size-cells = <1>;
308				interrupts = <113>;
309				clocks = <&coredivclk 0>;
310				status = "disabled";
311			};
312
313			mvsdio@d4000 {
314				compatible = "marvell,orion-sdio";
315				reg = <0xd4000 0x200>;
316				interrupts = <54>;
317				clocks = <&gateclk 17>;
318				bus-width = <4>;
319				cap-sdio-irq;
320				cap-sd-highspeed;
321				cap-mmc-highspeed;
322				status = "disabled";
323			};
324		};
325	};
326
327	clocks {
328		/* 2 GHz fixed main PLL */
329		mainpll: mainpll {
330			compatible = "fixed-clock";
331			#clock-cells = <0>;
332			clock-frequency = <2000000000>;
333		};
334	};
335 };
336