1#ifndef __ASM_ALPHA_FPU_H
2#define __ASM_ALPHA_FPU_H
3
4#include <asm/special_insns.h>
5#include <uapi/asm/fpu.h>
6
7/* The following two functions don't need trapb/excb instructions
8   around the mf_fpcr/mt_fpcr instructions because (a) the kernel
9   never generates arithmetic faults and (b) call_pal instructions
10   are implied trap barriers.  */
11
12static inline unsigned long
13rdfpcr(void)
14{
15	unsigned long tmp, ret;
16
17#if defined(CONFIG_ALPHA_EV6) || defined(CONFIG_ALPHA_EV67)
18	__asm__ __volatile__ (
19		"ftoit $f0,%0\n\t"
20		"mf_fpcr $f0\n\t"
21		"ftoit $f0,%1\n\t"
22		"itoft %0,$f0"
23		: "=r"(tmp), "=r"(ret));
24#else
25	__asm__ __volatile__ (
26		"stt $f0,%0\n\t"
27		"mf_fpcr $f0\n\t"
28		"stt $f0,%1\n\t"
29		"ldt $f0,%0"
30		: "=m"(tmp), "=m"(ret));
31#endif
32
33	return ret;
34}
35
36static inline void
37wrfpcr(unsigned long val)
38{
39	unsigned long tmp;
40
41#if defined(CONFIG_ALPHA_EV6) || defined(CONFIG_ALPHA_EV67)
42	__asm__ __volatile__ (
43		"ftoit $f0,%0\n\t"
44		"itoft %1,$f0\n\t"
45		"mt_fpcr $f0\n\t"
46		"itoft %0,$f0"
47		: "=&r"(tmp) : "r"(val));
48#else
49	__asm__ __volatile__ (
50		"stt $f0,%0\n\t"
51		"ldt $f0,%1\n\t"
52		"mt_fpcr $f0\n\t"
53		"ldt $f0,%0"
54		: "=m"(tmp) : "m"(val));
55#endif
56}
57
58static inline unsigned long
59swcr_update_status(unsigned long swcr, unsigned long fpcr)
60{
61	/* EV6 implements most of the bits in hardware.  Collect
62	   the acrued exception bits from the real fpcr.  */
63	if (implver() == IMPLVER_EV6) {
64		swcr &= ~IEEE_STATUS_MASK;
65		swcr |= (fpcr >> 35) & IEEE_STATUS_MASK;
66	}
67	return swcr;
68}
69
70extern unsigned long alpha_read_fp_reg (unsigned long reg);
71extern void alpha_write_fp_reg (unsigned long reg, unsigned long val);
72extern unsigned long alpha_read_fp_reg_s (unsigned long reg);
73extern void alpha_write_fp_reg_s (unsigned long reg, unsigned long val);
74
75#endif /* __ASM_ALPHA_FPU_H */
76