1* Atmel Watchdog Timers 2 3** at91sam9-wdt 4 5Required properties: 6- compatible: must be "atmel,at91sam9260-wdt". 7- reg: physical base address of the controller and length of memory mapped 8 region. 9 10Optional properties: 11- timeout-sec: contains the watchdog timeout in seconds. 12- interrupts : Should contain WDT interrupt. 13- atmel,max-heartbeat-sec : Should contain the maximum heartbeat value in 14 seconds. This value should be less or equal to 16. It is used to 15 compute the WDV field. 16- atmel,min-heartbeat-sec : Should contain the minimum heartbeat value in 17 seconds. This value must be smaller than the max-heartbeat-sec value. 18 It is used to compute the WDD field. 19- atmel,watchdog-type : Should be "hardware" or "software". Hardware watchdog 20 use the at91 watchdog reset. Software watchdog use the watchdog 21 interrupt to trigger a software reset. 22- atmel,reset-type : Should be "proc" or "all". 23 "all" : assert peripherals and processor reset signals 24 "proc" : assert the processor reset signal 25 This is valid only when using "hardware" watchdog. 26- atmel,disable : Should be present if you want to disable the watchdog. 27- atmel,idle-halt : Should be present if you want to stop the watchdog when 28 entering idle state. 29 CAUTION: This property should be used with care, it actually makes the 30 watchdog not counting when the CPU is in idle state, therefore the 31 watchdog reset time depends on mean CPU usage and will not reset at all 32 if the CPU stop working while it is in idle state, which is probably 33 not what you want. 34- atmel,dbg-halt : Should be present if you want to stop the watchdog when 35 entering debug state. 36 37Example: 38 watchdog@fffffd40 { 39 compatible = "atmel,at91sam9260-wdt"; 40 reg = <0xfffffd40 0x10>; 41 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 42 timeout-sec = <15>; 43 atmel,watchdog-type = "hardware"; 44 atmel,reset-type = "all"; 45 atmel,dbg-halt; 46 atmel,idle-halt; 47 atmel,max-heartbeat-sec = <16>; 48 atmel,min-heartbeat-sec = <0>; 49 status = "okay"; 50 }; 51