1* Mediatek MT65XX Pin Controller
2
3The Mediatek's Pin controller is used to control SoC pins.
4
5Required properties:
6- compatible: value should be either of the following.
7    (a) "mediatek,mt8135-pinctrl", compatible with mt8135 pinctrl.
8- mediatek,pctl-regmap: Should be a phandle of the syscfg node.
9- pins-are-numbered: Specify the subnodes are using numbered pinmux to
10  specify pins.
11- gpio-controller : Marks the device node as a gpio controller.
12- #gpio-cells: number of cells in GPIO specifier. Since the generic GPIO
13  binding is used, the amount of cells must be specified as 2. See the below
14  mentioned gpio binding representation for description of particular cells.
15
16	Eg: <&pio 6 0>
17	<[phandle of the gpio controller node]
18	[line number within the gpio controller]
19	[flags]>
20
21	Values for gpio specifier:
22	- Line number: is a value between 0 to 202.
23	- Flags:  bit field of flags, as defined in <dt-bindings/gpio/gpio.h>.
24            Only the following flags are supported:
25            0 - GPIO_ACTIVE_HIGH
26            1 - GPIO_ACTIVE_LOW
27- reg: physicall address base for EINT registers
28- interrupt-controller: Marks the device node as an interrupt controller
29- #interrupt-cells: Should be two.
30- interrupts : The interrupt outputs from the controller.
31
32Please refer to pinctrl-bindings.txt in this directory for details of the
33common pinctrl bindings used by client devices.
34
35Subnode format
36A pinctrl node should contain at least one subnodes representing the
37pinctrl groups available on the machine. Each subnode will list the
38pins it needs, and how they should be configured, with regard to muxer
39configuration, pullups, drive strength, input enable/disable and input schmitt.
40
41    node {
42	pinmux = <PIN_NUMBER_PINMUX>;
43	GENERIC_PINCONFIG;
44    };
45
46Required properties:
47- pinmux: integer array, represents gpio pin number and mux setting.
48    Supported pin number and mux varies for different SoCs, and are defined
49    as macros in boot/dts/<soc>-pinfunc.h directly.
50
51Optional properties:
52- GENERIC_PINCONFIG: is the generic pinconfig options to use, bias-disable,
53    bias-pull-down, bias-pull-up, input-enable, input-disable, output-low, output-high,
54    input-schmitt-enable, input-schmitt-disable and drive-strength are valid.
55
56    Some special pins have extra pull up strength, there are R0 and R1 pull-up
57    resistors available, but for user, it's only need to set R1R0 as 00, 01, 10 or 11.
58    So when config bias-pull-up, it support arguments for those special pins.
59    Some macros have been defined for this usage, such as MTK_PUPD_SET_R1R0_00.
60    See dt-bindings/pinctrl/mt65xx.h.
61
62    When config drive-strength, it can support some arguments, such as
63    MTK_DRIVE_4mA, MTK_DRIVE_6mA, etc. See dt-bindings/pinctrl/mt65xx.h.
64
65Examples:
66
67#include "mt8135-pinfunc.h"
68
69...
70{
71	syscfg_pctl_a: syscfg_pctl_a@10005000 {
72		compatible = "mediatek,mt8135-pctl-a-syscfg", "syscon";
73		reg = <0 0x10005000 0 0x1000>;
74	};
75
76	syscfg_pctl_b: syscfg_pctl_b@1020C020 {
77		compatible = "mediatek,mt8135-pctl-b-syscfg", "syscon";
78		reg = <0 0x1020C020 0 0x1000>;
79	};
80
81	pinctrl@01c20800 {
82		compatible = "mediatek,mt8135-pinctrl";
83		reg = <0 0x1000B000 0 0x1000>;
84		mediatek,pctl-regmap = <&syscfg_pctl_a &syscfg_pctl_b>;
85		pins-are-numbered;
86		gpio-controller;
87		#gpio-cells = <2>;
88		interrupt-controller;
89		#interrupt-cells = <2>;
90		interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
91				<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
92				<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
93
94		i2c0_pins_a: i2c0@0 {
95			pins1 {
96				pinmux = <MT8135_PIN_100_SDA0__FUNC_SDA0>,
97					 <MT8135_PIN_101_SCL0__FUNC_SCL0>;
98				bias-disable;
99			};
100		};
101
102		i2c1_pins_a: i2c1@0 {
103			pins {
104				pinmux = <MT8135_PIN_195_SDA1__FUNC_SDA1>,
105					 <MT8135_PIN_196_SCL1__FUNC_SCL1>;
106				bias-pull-up = <55>;
107			};
108		};
109
110		i2c2_pins_a: i2c2@0 {
111			pins1 {
112				pinmux = <MT8135_PIN_193_SDA2__FUNC_SDA2>;
113				bias-pull-down;
114			};
115
116			pins2 {
117				pinmux = <MT8135_PIN_49_WATCHDOG__FUNC_GPIO49>;
118				bias-pull-up;
119			};
120		};
121
122		i2c3_pins_a: i2c3@0 {
123			pins1 {
124				pinmux = <MT8135_PIN_40_DAC_CLK__FUNC_GPIO40>,
125					 <MT8135_PIN_41_DAC_WS__FUNC_GPIO41>;
126				bias-pull-up = <55>;
127			};
128
129			pins2 {
130				pinmux = <MT8135_PIN_35_SCL3__FUNC_SCL3>,
131					 <MT8135_PIN_36_SDA3__FUNC_SDA3>;
132				output-low;
133				bias-pull-up = <55>;
134			};
135
136			pins3 {
137				pinmux = <MT8135_PIN_57_JTCK__FUNC_GPIO57>,
138					 <MT8135_PIN_60_JTDI__FUNC_JTDI>;
139				drive-strength = <32>;
140			};
141		};
142
143		...
144	}
145};
146