1* Xilinx AXI PCIe Root Port Bridge DT description
2
3Required properties:
4- #address-cells: Address representation for root ports, set to <3>
5- #size-cells: Size representation for root ports, set to <2>
6- #interrupt-cells: specifies the number of cells needed to encode an
7	interrupt source. The value must be 1.
8- compatible: Should contain "xlnx,axi-pcie-host-1.00.a"
9- reg: Should contain AXI PCIe registers location and length
10- device_type: must be "pci"
11- interrupts: Should contain AXI PCIe interrupt
12- interrupt-map-mask,
13  interrupt-map: standard PCI properties to define the mapping of the
14	PCI interface to interrupt numbers.
15- ranges: ranges for the PCI memory regions (I/O space region is not
16	supported by hardware)
17	Please refer to the standard PCI bus binding document for a more
18	detailed explanation
19
20Optional properties:
21- bus-range: PCI bus numbers covered
22
23Interrupt controller child node
24+++++++++++++++++++++++++++++++
25Required properties:
26- interrupt-controller: identifies the node as an interrupt controller
27- #address-cells: specifies the number of cells needed to encode an
28	address. The value must be 0.
29- #interrupt-cells: specifies the number of cells needed to encode an
30	interrupt source. The value must be 1.
31
32NOTE:
33The core provides a single interrupt for both INTx/MSI messages. So,
34created a interrupt controller node to support 'interrupt-map' DT
35functionality.  The driver will create an IRQ domain for this map, decode
36the four INTx interrupts in ISR and route them to this domain.
37
38
39Example:
40++++++++
41
42	pci_express: axi-pcie@50000000 {
43		#address-cells = <3>;
44		#size-cells = <2>;
45		#interrupt-cells = <1>;
46		compatible = "xlnx,axi-pcie-host-1.00.a";
47		reg = < 0x50000000 0x10000000 >;
48		device_type = "pci";
49		interrupts = < 0 52 4 >;
50		interrupt-map-mask = <0 0 0 7>;
51		interrupt-map = <0 0 0 1 &pcie_intc 1>,
52				<0 0 0 2 &pcie_intc 2>,
53				<0 0 0 3 &pcie_intc 3>,
54				<0 0 0 4 &pcie_intc 4>;
55		ranges = < 0x02000000 0 0x60000000 0x60000000 0 0x10000000 >;
56
57		pcie_intc: interrupt-controller {
58			interrupt-controller;
59			#address-cells = <0>;
60			#interrupt-cells = <1>;
61		}
62	};
63