1* Freescale i.MX6 PCIe interface
2
3This PCIe host controller is based on the Synopsis Designware PCIe IP
4and thus inherits all the common properties defined in designware-pcie.txt.
5
6Required properties:
7- compatible: "fsl,imx6q-pcie"
8- reg: base addresse and length of the pcie controller
9- interrupts: A list of interrupt outputs of the controller. Must contain an
10  entry for each entry in the interrupt-names property.
11- interrupt-names: Must include the following entries:
12	- "msi": The interrupt that is asserted when an MSI is received
13- clock-names: Must include the following additional entries:
14	- "pcie_phy"
15
16Example:
17
18	pcie@0x01000000 {
19		compatible = "fsl,imx6q-pcie", "snps,dw-pcie";
20		reg = <0x01ffc000 0x04000>,
21		      <0x01f00000 0x80000>;
22		reg-names = "dbi", "config";
23		#address-cells = <3>;
24		#size-cells = <2>;
25		device_type = "pci";
26		ranges = <0x00000800 0 0x01f00000 0x01f00000 0 0x00080000
27			  0x81000000 0 0          0x01f80000 0 0x00010000
28			  0x82000000 0 0x01000000 0x01000000 0 0x00f00000>;
29		num-lanes = <1>;
30		interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
31		interrupt-names = "msi";
32		#interrupt-cells = <1>;
33		interrupt-map-mask = <0 0 0 0x7>;
34		interrupt-map = <0 0 0 1 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
35		                <0 0 0 2 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
36		                <0 0 0 3 &intc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
37		                <0 0 0 4 &intc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
38		clocks = <&clks 144>, <&clks 206>, <&clks 189>;
39		clock-names = "pcie", "pcie_bus", "pcie_phy";
40	};
41