1Device tree bindings for Ethernet chip connected to TI GPMC
2
3Besides being used to interface with external memory devices, the
4General-Purpose Memory Controller can be used to connect Pseudo-SRAM devices
5such as ethernet controllers to processors using the TI GPMC as a data bus.
6
7Ethernet controllers connected to TI GPMC are represented as child nodes of
8the GPMC controller with an "ethernet" name.
9
10All timing relevant properties as well as generic GPMC child properties are
11explained in a separate documents. Please refer to
12Documentation/devicetree/bindings/bus/ti-gpmc.txt
13
14For the properties relevant to the ethernet controller connected to the GPMC
15refer to the binding documentation of the device. For example, the documentation
16for the SMSC 911x is Documentation/devicetree/bindings/net/smsc911x.txt
17
18Child nodes need to specify the GPMC bus address width using the "bank-width"
19property but is possible that an ethernet controller also has a property to
20specify the I/O registers address width. Even when the GPMC has a maximum 16-bit
21address width, it supports devices with 32-bit word registers.
22For example with an SMSC LAN911x/912x controller connected to the TI GPMC on an
23OMAP2+ board, "bank-width = <2>;" and "reg-io-width = <4>;".
24
25Required properties:
26- bank-width: 		Address width of the device in bytes. GPMC supports 8-bit
27			and 16-bit devices and so must be either 1 or 2 bytes.
28- compatible:		Compatible string property for the ethernet child device.
29- gpmc,cs-on-ns:	Chip-select assertion time
30- gpmc,cs-rd-off-ns:	Chip-select de-assertion time for reads
31- gpmc,cs-wr-off-ns:	Chip-select de-assertion time for writes
32- gpmc,oe-on-ns:	Output-enable assertion time
33- gpmc,oe-off-ns:	Output-enable de-assertion time
34- gpmc,we-on-ns:	Write-enable assertion time
35- gpmc,we-off-ns:	Write-enable de-assertion time
36- gpmc,access-ns:	Start cycle to first data capture (read access)
37- gpmc,rd-cycle-ns:	Total read cycle time
38- gpmc,wr-cycle-ns:	Total write cycle time
39- reg:			Chip-select, base address (relative to chip-select)
40			and size of the memory mapped for the device.
41			Note that base address will be typically 0 as this
42			is the start of the chip-select.
43
44Optional properties:
45- gpmc,XXX		Additional GPMC timings and settings parameters. See
46			Documentation/devicetree/bindings/bus/ti-gpmc.txt
47
48Example:
49
50gpmc: gpmc@6e000000 {
51	compatible = "ti,omap3430-gpmc";
52	ti,hwmods = "gpmc";
53	reg = <0x6e000000 0x1000>;
54	interrupts = <20>;
55	gpmc,num-cs = <8>;
56	gpmc,num-waitpins = <4>;
57	#address-cells = <2>;
58	#size-cells = <1>;
59
60	ranges = <5 0 0x2c000000 0x1000000>;
61
62	ethernet@5,0 {
63		compatible = "smsc,lan9221", "smsc,lan9115";
64		reg = <5 0 0xff>;
65		bank-width = <2>;
66
67		gpmc,mux-add-data;
68		gpmc,cs-on-ns = <0>;
69		gpmc,cs-rd-off-ns = <186>;
70		gpmc,cs-wr-off-ns = <186>;
71		gpmc,adv-on-ns = <12>;
72		gpmc,adv-rd-off-ns = <48>;
73		gpmc,adv-wr-off-ns = <48>;
74		gpmc,oe-on-ns = <54>;
75		gpmc,oe-off-ns = <168>;
76		gpmc,we-on-ns = <54>;
77		gpmc,we-off-ns = <168>;
78		gpmc,rd-cycle-ns = <186>;
79		gpmc,wr-cycle-ns = <186>;
80		gpmc,access-ns = <114>;
81		gpmc,page-burst-access-ns = <6>;
82		gpmc,bus-turnaround-ns = <12>;
83		gpmc,cycle2cycle-delay-ns = <18>;
84		gpmc,wr-data-mux-bus-ns = <90>;
85		gpmc,wr-access-ns = <186>;
86		gpmc,cycle2cycle-samecsen;
87		gpmc,cycle2cycle-diffcsen;
88
89		interrupt-parent = <&gpio6>;
90		interrupts = <16>;
91		vmmc-supply = <&vddvario>;
92		vmmc_aux-supply = <&vdd33a>;
93		reg-io-width = <4>;
94
95		smsc,save-mac-address;
96	};
97};
98