1* AMD 10GbE driver (amd-xgbe)
2
3Required properties:
4- compatible: Should be "amd,xgbe-seattle-v1a"
5- reg: Address and length of the register sets for the device
6   - MAC registers
7   - PCS registers
8- interrupt-parent: Should be the phandle for the interrupt controller
9  that services interrupts for this device
10- interrupts: Should contain the amd-xgbe interrupt(s). The first interrupt
11  listed is required and is the general device interrupt. If the optional
12  amd,per-channel-interrupt property is specified, then one additional
13  interrupt for each DMA channel supported by the device should be specified
14- clocks:
15   - DMA clock for the amd-xgbe device (used for calculating the
16     correct Rx interrupt watchdog timer value on a DMA channel
17     for coalescing)
18   - PTP clock for the amd-xgbe device
19- clock-names: Should be the names of the clocks
20   - "dma_clk" for the DMA clock
21   - "ptp_clk" for the PTP clock
22- phy-handle: See ethernet.txt file in the same directory
23- phy-mode: See ethernet.txt file in the same directory
24
25Optional properties:
26- mac-address: mac address to be assigned to the device. Can be overridden
27  by UEFI.
28- dma-coherent: Present if dma operations are coherent
29- amd,per-channel-interrupt: Indicates that Rx and Tx complete will generate
30  a unique interrupt for each DMA channel - this requires an additional
31  interrupt be configured for each DMA channel
32
33Example:
34	xgbe@e0700000 {
35		compatible = "amd,xgbe-seattle-v1a";
36		reg = <0 0xe0700000 0 0x80000>,
37		      <0 0xe0780000 0 0x80000>;
38		interrupt-parent = <&gic>;
39		interrupts = <0 325 4>,
40			     <0 326 1>, <0 327 1>, <0 328 1>, <0 329 1>;
41		amd,per-channel-interrupt;
42		clocks = <&xgbe_dma_clk>, <&xgbe_ptp_clk>;
43		clock-names = "dma_clk", "ptp_clk";
44		phy-handle = <&phy>;
45		phy-mode = "xgmii";
46		mac-address = [ 02 a1 a2 a3 a4 a5 ];
47	};
48