1These properties are common to multiple MMC host controllers. Any host 2that requires the respective functionality should implement them using 3these definitions. 4 5Interpreted by the OF core: 6- reg: Registers location and length. 7- interrupts: Interrupts used by the MMC controller. 8 9Card detection: 10If no property below is supplied, host native card detect is used. 11Only one of the properties in this section should be supplied: 12 - broken-cd: There is no card detection available; polling must be used. 13 - cd-gpios: Specify GPIOs for card detection, see gpio binding 14 - non-removable: non-removable slot (like eMMC); assume always present. 15 16Optional properties: 17- bus-width: Number of data lines, can be <1>, <4>, or <8>. The default 18 will be <1> if the property is absent. 19- wp-gpios: Specify GPIOs for write protection, see gpio binding 20- cd-inverted: when present, polarity on the CD line is inverted. See the note 21 below for the case, when a GPIO is used for the CD line 22- wp-inverted: when present, polarity on the WP line is inverted. See the note 23 below for the case, when a GPIO is used for the WP line 24- max-frequency: maximum operating clock frequency 25- no-1-8-v: when present, denotes that 1.8v card voltage is not supported on 26 this system, even if the controller claims it is. 27- cap-sd-highspeed: SD high-speed timing is supported 28- cap-mmc-highspeed: MMC high-speed timing is supported 29- sd-uhs-sdr12: SD UHS SDR12 speed is supported 30- sd-uhs-sdr25: SD UHS SDR25 speed is supported 31- sd-uhs-sdr50: SD UHS SDR50 speed is supported 32- sd-uhs-sdr104: SD UHS SDR104 speed is supported 33- sd-uhs-ddr50: SD UHS DDR50 speed is supported 34- cap-power-off-card: powering off the card is safe 35- cap-sdio-irq: enable SDIO IRQ signalling on this interface 36- full-pwr-cycle: full power cycle of the card is supported 37- mmc-ddr-1_8v: eMMC high-speed DDR mode(1.8V I/O) is supported 38- mmc-ddr-1_2v: eMMC high-speed DDR mode(1.2V I/O) is supported 39- mmc-hs200-1_8v: eMMC HS200 mode(1.8V I/O) is supported 40- mmc-hs200-1_2v: eMMC HS200 mode(1.2V I/O) is supported 41- mmc-hs400-1_8v: eMMC HS400 mode(1.8V I/O) is supported 42- mmc-hs400-1_2v: eMMC HS400 mode(1.2V I/O) is supported 43- dsr: Value the card's (optional) Driver Stage Register (DSR) should be 44 programmed with. Valid range: [0 .. 0xffff]. 45 46*NOTE* on CD and WP polarity. To use common for all SD/MMC host controllers line 47polarity properties, we have to fix the meaning of the "normal" and "inverted" 48line levels. We choose to follow the SDHCI standard, which specifies both those 49lines as "active low." Therefore, using the "cd-inverted" property means, that 50the CD line is active high, i.e. it is high, when a card is inserted. Similar 51logic applies to the "wp-inverted" property. 52 53CD and WP lines can be implemented on the hardware in one of two ways: as GPIOs, 54specified in cd-gpios and wp-gpios properties, or as dedicated pins. Polarity of 55dedicated pins can be specified, using *-inverted properties. GPIO polarity can 56also be specified using the OF_GPIO_ACTIVE_LOW flag. This creates an ambiguity 57in the latter case. We choose to use the XOR logic for GPIO CD and WP lines. 58This means, the two properties are "superimposed," for example leaving the 59OF_GPIO_ACTIVE_LOW flag clear and specifying the respective *-inverted 60property results in a double-inversion and actually means the "normal" line 61polarity is in effect. 62 63Optional SDIO properties: 64- keep-power-in-suspend: Preserves card power during a suspend/resume cycle 65- enable-sdio-wakeup: Enables wake up of host system on SDIO IRQ assertion 66 67 68MMC power sequences: 69-------------------- 70 71System on chip designs may specify a specific MMC power sequence. To 72successfully detect an (e)MMC/SD/SDIO card, that power sequence must be 73maintained while initializing the card. 74 75Optional property: 76- mmc-pwrseq: phandle to the MMC power sequence node. See "mmc-pwrseq-*" 77 for documentation of MMC power sequence bindings. 78 79 80Use of Function subnodes 81------------------------ 82 83On embedded systems the cards connected to a host may need additional 84properties. These can be specified in subnodes to the host controller node. 85The subnodes are identified by the standard 'reg' property. 86Which information exactly can be specified depends on the bindings for the 87SDIO function driver for the subnode, as specified by the compatible string. 88 89Required host node properties when using function subnodes: 90- #address-cells: should be one. The cell is the slot id. 91- #size-cells: should be zero. 92 93Required function subnode properties: 94- compatible: name of SDIO function following generic names recommended practice 95- reg: Must contain the SDIO function number of the function this subnode 96 describes. A value of 0 denotes the memory SD function, values from 97 1 to 7 denote the SDIO functions. 98 99 100Examples 101-------- 102 103Basic example: 104 105sdhci@ab000000 { 106 compatible = "sdhci"; 107 reg = <0xab000000 0x200>; 108 interrupts = <23>; 109 bus-width = <4>; 110 cd-gpios = <&gpio 69 0>; 111 cd-inverted; 112 wp-gpios = <&gpio 70 0>; 113 max-frequency = <50000000>; 114 keep-power-in-suspend; 115 enable-sdio-wakeup; 116 mmc-pwrseq = <&sdhci0_pwrseq> 117} 118 119Example with sdio function subnode: 120 121mmc3: mmc@01c12000 { 122 #address-cells = <1>; 123 #size-cells = <0>; 124 125 pinctrl-names = "default"; 126 pinctrl-0 = <&mmc3_pins_a>; 127 vmmc-supply = <®_vmmc3>; 128 bus-width = <4>; 129 non-removable; 130 mmc-pwrseq = <&sdhci0_pwrseq> 131 status = "okay"; 132 133 brcmf: bcrmf@1 { 134 reg = <1>; 135 compatible = "brcm,bcm43xx-fmac"; 136 interrupt-parent = <&pio>; 137 interrupts = <10 8>; /* PH10 / EINT10 */ 138 interrupt-names = "host-wake"; 139 }; 140}; 141