1* Cavium Interrupt Bus widget
2
3Properties:
4- compatible: "cavium,octeon-7130-cib"
5
6  Compatibility with cn70XX SoCs.
7
8- interrupt-controller:  This is an interrupt controller.
9
10- reg: Two elements consisting of the addresses of the RAW and EN
11  registers of the CIB block
12
13- cavium,max-bits: The index (zero based) of the highest numbered bit
14  in the CIB block.
15
16- interrupt-parent:  Always the CIU on the SoC.
17
18- interrupts: The CIU line to which the CIB block is connected.
19
20- #interrupt-cells: Must be <2>.  The first cell is the bit within the
21   CIB.  The second cell specifies the triggering semantics of the
22   line.
23
24Example:
25
26	interrupt-controller@107000000e000 {
27		compatible = "cavium,octeon-7130-cib";
28		reg = <0x10700 0x0000e000 0x0 0x8>, /* RAW */
29		      <0x10700 0x0000e100 0x0 0x8>; /* EN */
30		cavium,max-bits = <23>;
31
32		interrupt-controller;
33		interrupt-parent = <&ciu>;
34		interrupts = <1 24>;
35		/* Interrupts are specified by two parts:
36		 * 1) Bit number in the CIB* registers
37		 * 2) Triggering (1 - edge rising
38		 *		  2 - edge falling
39		 *		  4 - level active high
40		 *		  8 - level active low)
41		 */
42		#interrupt-cells = <2>;
43	};
44