1Samsung Exynos IOMMU H/W, System MMU (System Memory Management Unit)
2
3Samsung's Exynos architecture contains System MMUs that enables scattered
4physical memory chunks visible as a contiguous region to DMA-capable peripheral
5devices like MFC, FIMC, FIMD, GScaler, FIMC-IS and so forth.
6
7System MMU is an IOMMU and supports identical translation table format to
8ARMv7 translation tables with minimum set of page properties including access
9permissions, shareability and security protection. In addition, System MMU has
10another capabilities like L2 TLB or block-fetch buffers to minimize translation
11latency.
12
13System MMUs are in many to one relation with peripheral devices, i.e. single
14peripheral device might have multiple System MMUs (usually one for each bus
15master), but one System MMU can handle transactions from only one peripheral
16device. The relation between a System MMU and the peripheral device needs to be
17defined in device node of the peripheral device.
18
19MFC in all Exynos SoCs and FIMD, M2M Scalers and G2D in Exynos5420 has 2 System
20MMUs.
21* MFC has one System MMU on its left and right bus.
22* FIMD in Exynos5420 has one System MMU for window 0 and 4, the other system MMU
23  for window 1, 2 and 3.
24* M2M Scalers and G2D in Exynos5420 has one System MMU on the read channel and
25  the other System MMU on the write channel.
26The drivers must consider how to handle those System MMUs. One of the idea is
27to implement child devices or sub-devices which are the client devices of the
28System MMU.
29
30Note:
31The current DT binding for the Exynos System MMU is incomplete.
32The following properties can be removed or changed, if found incompatible with
33the "Generic IOMMU Binding" support for attaching devices to the IOMMU.
34
35Required properties:
36- compatible: Should be "samsung,exynos-sysmmu"
37- reg: A tuple of base address and size of System MMU registers.
38- interrupt-parent: The phandle of the interrupt controller of System MMU
39- interrupts: An interrupt specifier for interrupt signal of System MMU,
40	      according to the format defined by a particular interrupt
41	      controller.
42- clock-names: Should be "sysmmu" if the System MMU is needed to gate its clock.
43	       Optional "master" if the clock to the System MMU is gated by
44	       another gate clock other than "sysmmu".
45	       Exynos4 SoCs, there needs no "master" clock.
46	       Exynos5 SoCs, some System MMUs must have "master" clocks.
47- clocks: Required if the System MMU is needed to gate its clock.
48- power-domains: Required if the System MMU is needed to gate its power.
49	  Please refer to the following document:
50	  Documentation/devicetree/bindings/arm/exynos/power_domain.txt
51
52Examples:
53	gsc_0: gsc@13e00000 {
54		compatible = "samsung,exynos5-gsc";
55		reg = <0x13e00000 0x1000>;
56		interrupts = <0 85 0>;
57		power-domains = <&pd_gsc>;
58		clocks = <&clock CLK_GSCL0>;
59		clock-names = "gscl";
60	};
61
62	sysmmu_gsc0: sysmmu@13E80000 {
63		compatible = "samsung,exynos-sysmmu";
64		reg = <0x13E80000 0x1000>;
65		interrupt-parent = <&combiner>;
66		interrupts = <2 0>;
67		clock-names = "sysmmu", "master";
68		clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>;
69		power-domains = <&pd_gsc>;
70	};
71