1* ARM System MMU Architecture Implementation
2
3ARM SoCs may contain an implementation of the ARM System Memory
4Management Unit Architecture, which can be used to provide 1 or 2 stages
5of address translation to bus masters external to the CPU.
6
7The SMMU may also raise interrupts in response to various fault
8conditions.
9
10** System MMU required properties:
11
12- compatible    : Should be one of:
13
14                        "arm,smmu-v1"
15                        "arm,smmu-v2"
16                        "arm,mmu-400"
17                        "arm,mmu-401"
18                        "arm,mmu-500"
19
20                  depending on the particular implementation and/or the
21                  version of the architecture implemented.
22
23- reg           : Base address and size of the SMMU.
24
25- #global-interrupts : The number of global interrupts exposed by the
26                       device.
27
28- interrupts    : Interrupt list, with the first #global-irqs entries
29                  corresponding to the global interrupts and any
30                  following entries corresponding to context interrupts,
31                  specified in order of their indexing by the SMMU.
32
33                  For SMMUv2 implementations, there must be exactly one
34                  interrupt per context bank. In the case of a single,
35                  combined interrupt, it must be listed multiple times.
36
37- mmu-masters   : A list of phandles to device nodes representing bus
38                  masters for which the SMMU can provide a translation
39                  and their corresponding StreamIDs (see example below).
40                  Each device node linked from this list must have a
41                  "#stream-id-cells" property, indicating the number of
42                  StreamIDs associated with it.
43
44** System MMU optional properties:
45
46- calxeda,smmu-secure-config-access : Enable proper handling of buggy
47                  implementations that always use secure access to
48                  SMMU configuration registers. In this case non-secure
49                  aliases of secure registers have to be used during
50                  SMMU configuration.
51
52Example:
53
54        smmu {
55                compatible = "arm,smmu-v1";
56                reg = <0xba5e0000 0x10000>;
57                #global-interrupts = <2>;
58                interrupts = <0 32 4>,
59                             <0 33 4>,
60                             <0 34 4>, /* This is the first context interrupt */
61                             <0 35 4>,
62                             <0 36 4>,
63                             <0 37 4>;
64
65                /*
66                 * Two DMA controllers, the first with two StreamIDs (0xd01d
67                 * and 0xd01e) and the second with only one (0xd11c).
68                 */
69                mmu-masters = <&dma0 0xd01d 0xd01e>,
70                              <&dma1 0xd11c>;
71        };
72