1Broadcom BCM7120-style Level 2 interrupt controller
2
3This interrupt controller hardware is a second level interrupt controller that
4is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based
5platforms. It can be found on BCM7xxx products starting with BCM7120.
6
7Such an interrupt controller has the following hardware design:
8
9- outputs multiple interrupts signals towards its interrupt controller parent
10
11- controls how some of the interrupts will be flowing, whether they will
12  directly output an interrupt signal towards the interrupt controller parent,
13  or if they will output an interrupt signal at this 2nd level interrupt
14  controller, in particular for UARTs
15
16- has one 32-bit enable word and one 32-bit status word
17
18- no atomic set/clear operations
19
20- not all bits within the interrupt controller actually map to an interrupt
21
22The typical hardware layout for this controller is represented below:
23
242nd level interrupt line		Outputs for the parent controller (e.g: ARM GIC)
25
260 -----[ MUX ] ------------|==========> GIC interrupt 75
27          \-----------\
28                       |
291 -----[ MUX ] --------)---|==========> GIC interrupt 76
30          \------------|
31                       |
322 -----[ MUX ] --------)---|==========> GIC interrupt 77
33          \------------|
34                       |
353 ---------------------|
364 ---------------------|
375 ---------------------|
387 ---------------------|---|===========> GIC interrupt 66
399 ---------------------|
4010 --------------------|
4111 --------------------/
42
436 ------------------------\
44                           |===========> GIC interrupt 64
458 ------------------------/
46
4712 ........................ X
4813 ........................ X 		(not connected)
49..
5031 ........................ X
51
52Required properties:
53
54- compatible: should be "brcm,bcm7120-l2-intc"
55- reg: specifies the base physical address and size of the registers
56- interrupt-controller: identifies the node as an interrupt controller
57- #interrupt-cells: specifies the number of cells needed to encode an interrupt
58  source, should be 1.
59- interrupt-parent: specifies the phandle to the parent interrupt controller
60  this one is cascaded from
61- interrupts: specifies the interrupt line(s) in the interrupt-parent controller
62  node, valid values depend on the type of parent interrupt controller
63- brcm,int-map-mask: 32-bits bit mask describing how many and which interrupts
64  are wired to this 2nd level interrupt controller, and how they match their
65  respective interrupt parents. Should match exactly the number of interrupts
66  specified in the 'interrupts' property.
67
68Optional properties:
69
70- brcm,irq-can-wake: if present, this means the L2 controller can be used as a
71  wakeup source for system suspend/resume.
72
73- brcm,int-fwd-mask: if present, a bit mask to configure the interrupts which
74  have a mux gate, typically UARTs. Setting these bits will make their
75  respective interrupt outputs bypass this 2nd level interrupt controller
76  completely; it is completely transparent for the interrupt controller
77  parent. This should have one 32-bit word per enable/status pair.
78
79Example:
80
81irq0_intc: interrupt-controller@f0406800 {
82	compatible = "brcm,bcm7120-l2-intc";
83	interrupt-parent = <&intc>;
84	#interrupt-cells = <1>;
85	reg = <0xf0406800 0x8>;
86	interrupt-controller;
87	interrupts = <0x0 0x42 0x0>, <0x0 0x40 0x0>;
88	brcm,int-map-mask = <0xeb8>, <0x140>;
89	brcm,int-fwd-mask = <0x7>;
90};
91