1STMicroelectronics stih4xx platforms
2
3- sti-vtg: video timing generator
4  Required properties:
5  - compatible: "st,vtg"
6  - reg: Physical base address of the IP registers and length of memory mapped region.
7  Optional properties:
8  - interrupts : VTG interrupt number to the CPU.
9  - st,slave: phandle on a slave vtg
10
11- sti-vtac: video timing advanced inter dye communication Rx and TX
12  Required properties:
13  - compatible: "st,vtac-main" or "st,vtac-aux"
14  - reg: Physical base address of the IP registers and length of memory mapped region.
15  - clocks: from common clock binding: handle hardware IP needed clocks, the
16    number of clocks may depend of the SoC type.
17    See ../clocks/clock-bindings.txt for details.
18  - clock-names: names of the clocks listed in clocks property in the same
19    order.
20
21- sti-display-subsystem: Master device for DRM sub-components
22  This device must be the parent of all the sub-components and is responsible
23  of bind them.
24  Required properties:
25  - compatible: "st,sti-display-subsystem"
26  - ranges: to allow probing of subdevices
27
28- sti-compositor: frame compositor engine
29  must be a child of sti-display-subsystem
30  Required properties:
31  - compatible: "st,stih<chip>-compositor"
32  - reg: Physical base address of the IP registers and length of memory mapped region.
33  - clocks: from common clock binding: handle hardware IP needed clocks, the
34    number of clocks may depend of the SoC type.
35    See ../clocks/clock-bindings.txt for details.
36  - clock-names: names of the clocks listed in clocks property in the same
37    order.
38  - resets: resets to be used by the device
39    See ../reset/reset.txt for details.
40  - reset-names: names of the resets listed in resets property in the same
41    order.
42  - st,vtg: phandle(s) on vtg device (main and aux) nodes.
43
44- sti-tvout: video out hardware block
45  must be a child of sti-display-subsystem
46  Required properties:
47  - compatible: "st,stih<chip>-tvout"
48  - reg: Physical base address of the IP registers and length of memory mapped region.
49  - reg-names: names of the mapped memory regions listed in regs property in
50    the same order.
51  - resets: resets to be used by the device
52    See ../reset/reset.txt for details.
53  - reset-names: names of the resets listed in resets property in the same
54    order.
55  - ranges: to allow probing of subdevices
56
57- sti-hdmi: hdmi output block
58  must be a child of sti-tvout
59  Required properties:
60  - compatible: "st,stih<chip>-hdmi";
61  - reg: Physical base address of the IP registers and length of memory mapped region.
62  - reg-names: names of the mapped memory regions listed in regs property in
63    the same order.
64  - interrupts : HDMI interrupt number to the CPU.
65  - interrupt-names: name of the interrupts listed in interrupts property in
66    the same order
67  - clocks: from common clock binding: handle hardware IP needed clocks, the
68    number of clocks may depend of the SoC type.
69  - clock-names: names of the clocks listed in clocks property in the same
70    order.
71  - ddc: phandle of an I2C controller used for DDC EDID probing
72
73sti-hda:
74  Required properties:
75  must be a child of sti-tvout
76  - compatible: "st,stih<chip>-hda"
77  - reg: Physical base address of the IP registers and length of memory mapped region.
78  - reg-names: names of the mapped memory regions listed in regs property in
79    the same order.
80  - clocks: from common clock binding: handle hardware IP needed clocks, the
81    number of clocks may depend of the SoC type.
82    See ../clocks/clock-bindings.txt for details.
83  - clock-names: names of the clocks listed in clocks property in the same
84    order.
85
86sti-dvo:
87  Required properties:
88  must be a child of sti-tvout
89  - compatible: "st,stih<chip>-dvo"
90  - reg: Physical base address of the IP registers and length of memory mapped region.
91  - reg-names: names of the mapped memory regions listed in regs property in
92    the same order.
93  - clocks: from common clock binding: handle hardware IP needed clocks, the
94    number of clocks may depend of the SoC type.
95    See ../clocks/clock-bindings.txt for details.
96  - clock-names: names of the clocks listed in clocks property in the same
97    order.
98  - pinctrl-0: pin control handle
99  - pinctrl-name: names of the pin control to use
100  - sti,panel: phandle of the panel connected to the DVO output
101
102sti-hqvdp:
103  must be a child of sti-display-subsystem
104  Required properties:
105  - compatible: "st,stih<chip>-hqvdp"
106  - reg: Physical base address of the IP registers and length of memory mapped region.
107  - clocks: from common clock binding: handle hardware IP needed clocks, the
108    number of clocks may depend of the SoC type.
109    See ../clocks/clock-bindings.txt for details.
110  - clock-names: names of the clocks listed in clocks property in the same
111    order.
112  - resets: resets to be used by the device
113    See ../reset/reset.txt for details.
114  - reset-names: names of the resets listed in resets property in the same
115    order.
116  - st,vtg: phandle on vtg main device node.
117
118Example:
119
120/ {
121	...
122
123	vtg_main_slave: sti-vtg-main-slave@fe85A800 {
124		compatible	= "st,vtg";
125		reg		= <0xfe85A800 0x300>;
126		interrupts	= <GIC_SPI 175 IRQ_TYPE_NONE>;
127	};
128
129	vtg_main: sti-vtg-main-master@fd348000 {
130		compatible	= "st,vtg";
131		reg		= <0xfd348000 0x400>;
132		st,slave	= <&vtg_main_slave>;
133	};
134
135	vtg_aux_slave: sti-vtg-aux-slave@fd348400 {
136		compatible	= "st,vtg";
137		reg		= <0xfe858200 0x300>;
138		interrupts	= <GIC_SPI 176 IRQ_TYPE_NONE>;
139	};
140
141	vtg_aux: sti-vtg-aux-master@fd348400 {
142		compatible	= "st,vtg";
143		reg		= <0xfd348400 0x400>;
144		st,slave	= <&vtg_aux_slave>;
145	};
146
147
148	sti-vtac-rx-main@fee82800 {
149		compatible	= "st,vtac-main";
150		reg		= <0xfee82800 0x200>;
151		clock-names     = "vtac";
152		clocks          = <&clk_m_a2_div0 CLK_M_VTAC_MAIN_PHY>;
153	};
154
155	sti-vtac-rx-aux@fee82a00 {
156		compatible	= "st,vtac-aux";
157		reg		= <0xfee82a00 0x200>;
158		clock-names     = "vtac";
159		clocks          = <&clk_m_a2_div0 CLK_M_VTAC_AUX_PHY>;
160	};
161
162	sti-vtac-tx-main@fd349000 {
163		compatible	= "st,vtac-main";
164		reg		= <0xfd349000 0x200>, <0xfd320000 0x10000>;
165		clock-names     = "vtac";
166		clocks           = <&clk_s_a1_hs CLK_S_VTAC_TX_PHY>;
167	};
168
169	sti-vtac-tx-aux@fd349200 {
170		compatible	= "st,vtac-aux";
171		reg		= <0xfd349200 0x200>, <0xfd320000 0x10000>;
172		clock-names     = "vtac";
173		clocks          = <&clk_s_a1_hs CLK_S_VTAC_TX_PHY>;
174	};
175
176	sti-display-subsystem {
177		compatible = "st,sti-display-subsystem";
178		ranges;
179
180		sti-compositor@fd340000 {
181			compatible	= "st,stih416-compositor";
182			reg		= <0xfd340000 0x1000>;
183			clock-names	= "compo_main", "compo_aux",
184			                  "pix_main", "pix_aux";
185			clocks          = <&clk_m_a2_div1 CLK_M_COMPO_MAIN>, <&clk_m_a2_div1 CLK_M_COMPO_AUX>,
186					  <&clockgen_c_vcc CLK_S_PIX_MAIN>, <&clockgen_c_vcc CLK_S_PIX_AUX>;
187			reset-names     = "compo-main", "compo-aux";
188			resets          = <&softreset STIH416_COMPO_M_SOFTRESET>, <&softreset STIH416_COMPO_A_SOFTRESET>;
189			st,vtg		= <&vtg_main>, <&vtg_aux>;
190		};
191
192		sti-tvout@fe000000 {
193			compatible	= "st,stih416-tvout";
194			reg		= <0xfe000000 0x1000>, <0xfe85a000 0x400>, <0xfe830000 0x10000>;
195			reg-names	= "tvout-reg", "hda-reg", "syscfg";
196			reset-names     = "tvout";
197			resets          = <&softreset STIH416_HDTVOUT_SOFTRESET>;
198			ranges;
199
200			sti-hdmi@fe85c000 {
201				compatible	= "st,stih416-hdmi";
202				reg		= <0xfe85c000 0x1000>, <0xfe830000 0x10000>;
203				reg-names	= "hdmi-reg", "syscfg";
204				interrupts	= <GIC_SPI 173 IRQ_TYPE_NONE>;
205				interrupt-names	= "irq";
206				clock-names	= "pix", "tmds", "phy", "audio";
207				clocks          = <&clockgen_c_vcc CLK_S_PIX_HDMI>, <&clockgen_c_vcc CLK_S_TMDS_HDMI>, <&clockgen_c_vcc CLK_S_HDMI_REJECT_PLL>, <&clockgen_b1 CLK_S_PCM_0>;
208			};
209
210			sti-hda@fe85a000 {
211				compatible	= "st,stih416-hda";
212				reg		= <0xfe85a000 0x400>, <0xfe83085c 0x4>;
213				reg-names	= "hda-reg", "video-dacs-ctrl";
214				clock-names	= "pix", "hddac";
215				clocks          = <&clockgen_c_vcc CLK_S_PIX_HD>, <&clockgen_c_vcc CLK_S_HDDAC>;
216			};
217
218			sti-dvo@8d00400 {
219				compatible	= "st,stih407-dvo";
220				reg		= <0x8d00400 0x200>;
221				reg-names	= "dvo-reg";
222				clock-names	= "dvo_pix", "dvo",
223						  "main_parent", "aux_parent";
224				clocks		= <&clk_s_d2_flexgen CLK_PIX_DVO>, <&clk_s_d2_flexgen CLK_DVO>,
225						  <&clk_s_d2_quadfs 0>, <&clk_s_d2_quadfs 1>;
226				pinctrl-names	= "default";
227				pinctrl-0	= <&pinctrl_dvo>;
228				sti,panel	= <&panel_dvo>;
229			};
230		};
231
232		sti-hqvdp@9c000000 {
233				compatible	= "st,stih407-hqvdp";
234				reg		= <0x9C00000 0x100000>;
235				clock-names	= "hqvdp", "pix_main";
236				clocks		= <&clk_s_c0_flexgen CLK_MAIN_DISP>, <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>;
237				reset-names     = "hqvdp";
238				resets          = <&softreset STIH407_HDQVDP_SOFTRESET>;
239				st,vtg		= <&vtg_main>;
240			};
241	};
242	...
243};
244