1Specifying GPIO information for devices 2============================================ 3 41) gpios property 5----------------- 6 7Nodes that makes use of GPIOs should specify them using one or more 8properties, each containing a 'gpio-list': 9 10 gpio-list ::= <single-gpio> [gpio-list] 11 single-gpio ::= <gpio-phandle> <gpio-specifier> 12 gpio-phandle : phandle to gpio controller node 13 gpio-specifier : Array of #gpio-cells specifying specific gpio 14 (controller specific) 15 16GPIO properties should be named "[<name>-]gpios", with <name> being the purpose 17of this GPIO for the device. While a non-existent <name> is considered valid 18for compatibility reasons (resolving to the "gpios" property), it is not allowed 19for new bindings. 20 21GPIO properties can contain one or more GPIO phandles, but only in exceptional 22cases should they contain more than one. If your device uses several GPIOs with 23distinct functions, reference each of them under its own property, giving it a 24meaningful name. The only case where an array of GPIOs is accepted is when 25several GPIOs serve the same function (e.g. a parallel data line). 26 27The exact purpose of each gpios property must be documented in the device tree 28binding of the device. 29 30The following example could be used to describe GPIO pins used as device enable 31and bit-banged data signals: 32 33 gpio1: gpio1 { 34 gpio-controller 35 #gpio-cells = <2>; 36 }; 37 gpio2: gpio2 { 38 gpio-controller 39 #gpio-cells = <1>; 40 }; 41 [...] 42 43 enable-gpios = <&gpio2 2>; 44 data-gpios = <&gpio1 12 0>, 45 <&gpio1 13 0>, 46 <&gpio1 14 0>, 47 <&gpio1 15 0>; 48 49Note that gpio-specifier length is controller dependent. In the 50above example, &gpio1 uses 2 cells to specify a gpio, while &gpio2 51only uses one. 52 53gpio-specifier may encode: bank, pin position inside the bank, 54whether pin is open-drain and whether pin is logically inverted. 55Exact meaning of each specifier cell is controller specific, and must 56be documented in the device tree binding for the device. Use the macros 57defined in include/dt-bindings/gpio/gpio.h whenever possible: 58 59Example of a node using GPIOs: 60 61 node { 62 enable-gpios = <&qe_pio_e 18 GPIO_ACTIVE_HIGH>; 63 }; 64 65GPIO_ACTIVE_HIGH is 0, so in this example gpio-specifier is "18 0" and encodes 66GPIO pin number, and GPIO flags as accepted by the "qe_pio_e" gpio-controller. 67 681.1) GPIO specifier best practices 69---------------------------------- 70 71A gpio-specifier should contain a flag indicating the GPIO polarity; active- 72high or active-low. If it does, the following best practices should be 73followed: 74 75The gpio-specifier's polarity flag should represent the physical level at the 76GPIO controller that achieves (or represents, for inputs) a logically asserted 77value at the device. The exact definition of logically asserted should be 78defined by the binding for the device. If the board inverts the signal between 79the GPIO controller and the device, then the gpio-specifier will represent the 80opposite physical level than the signal at the device's pin. 81 82When the device's signal polarity is configurable, the binding for the 83device must either: 84 85a) Define a single static polarity for the signal, with the expectation that 86any software using that binding would statically program the device to use 87that signal polarity. 88 89The static choice of polarity may be either: 90 91a1) (Preferred) Dictated by a binding-specific DT property. 92 93or: 94 95a2) Defined statically by the DT binding itself. 96 97In particular, the polarity cannot be derived from the gpio-specifier, since 98that would prevent the DT from separately representing the two orthogonal 99concepts of configurable signal polarity in the device, and possible board- 100level signal inversion. 101 102or: 103 104b) Pick a single option for device signal polarity, and document this choice 105in the binding. The gpio-specifier should represent the polarity of the signal 106(at the GPIO controller) assuming that the device is configured for this 107particular signal polarity choice. If software chooses to program the device 108to generate or receive a signal of the opposite polarity, software will be 109responsible for correctly interpreting (inverting) the GPIO signal at the GPIO 110controller. 111 1122) gpio-controller nodes 113------------------------ 114 115Every GPIO controller node must contain both an empty "gpio-controller" 116property, and a #gpio-cells integer property, which indicates the number of 117cells in a gpio-specifier. 118 119The GPIO chip may contain GPIO hog definitions. GPIO hogging is a mechanism 120providing automatic GPIO request and configuration as part of the 121gpio-controller's driver probe function. 122 123Each GPIO hog definition is represented as a child node of the GPIO controller. 124Required properties: 125- gpio-hog: A property specifying that this child node represent a GPIO hog. 126- gpios: Store the GPIO information (id, flags, ...). Shall contain the 127 number of cells specified in its parent node (GPIO controller 128 node). 129Only one of the following properties scanned in the order shown below. 130This means that when multiple properties are present they will be searched 131in the order presented below and the first match is taken as the intended 132configuration. 133- input: A property specifying to set the GPIO direction as input. 134- output-low A property specifying to set the GPIO direction as output with 135 the value low. 136- output-high A property specifying to set the GPIO direction as output with 137 the value high. 138 139Optional properties: 140- line-name: The GPIO label name. If not present the node name is used. 141 142Example of two SOC GPIO banks defined as gpio-controller nodes: 143 144 qe_pio_a: gpio-controller@1400 { 145 compatible = "fsl,qe-pario-bank-a", "fsl,qe-pario-bank"; 146 reg = <0x1400 0x18>; 147 gpio-controller; 148 #gpio-cells = <2>; 149 150 line_b { 151 gpio-hog; 152 gpios = <6 0>; 153 output-low; 154 line-name = "foo-bar-gpio"; 155 }; 156 }; 157 158 qe_pio_e: gpio-controller@1460 { 159 compatible = "fsl,qe-pario-bank-e", "fsl,qe-pario-bank"; 160 reg = <0x1460 0x18>; 161 gpio-controller; 162 #gpio-cells = <2>; 163 }; 164 1652.1) gpio- and pin-controller interaction 166----------------------------------------- 167 168Some or all of the GPIOs provided by a GPIO controller may be routed to pins 169on the package via a pin controller. This allows muxing those pins between 170GPIO and other functions. 171 172It is useful to represent which GPIOs correspond to which pins on which pin 173controllers. The gpio-ranges property described below represents this, and 174contains information structures as follows: 175 176 gpio-range-list ::= <single-gpio-range> [gpio-range-list] 177 single-gpio-range ::= <numeric-gpio-range> | <named-gpio-range> 178 numeric-gpio-range ::= 179 <pinctrl-phandle> <gpio-base> <pinctrl-base> <count> 180 named-gpio-range ::= <pinctrl-phandle> <gpio-base> '<0 0>' 181 pinctrl-phandle : phandle to pin controller node 182 gpio-base : Base GPIO ID in the GPIO controller 183 pinctrl-base : Base pinctrl pin ID in the pin controller 184 count : The number of GPIOs/pins in this range 185 186The "pin controller node" mentioned above must conform to the bindings 187described in ../pinctrl/pinctrl-bindings.txt. 188 189In case named gpio ranges are used (ranges with both <pinctrl-base> and 190<count> set to 0), the property gpio-ranges-group-names contains one string 191for every single-gpio-range in gpio-ranges: 192 gpiorange-names-list ::= <gpiorange-name> [gpiorange-names-list] 193 gpiorange-name : Name of the pingroup associated to the GPIO range in 194 the respective pin controller. 195 196Elements of gpiorange-names-list corresponding to numeric ranges contain 197the empty string. Elements of gpiorange-names-list corresponding to named 198ranges contain the name of a pin group defined in the respective pin 199controller. The number of pins/GPIOs in the range is the number of pins in 200that pin group. 201 202Previous versions of this binding required all pin controller nodes that 203were referenced by any gpio-ranges property to contain a property named 204#gpio-range-cells with value <3>. This requirement is now deprecated. 205However, that property may still exist in older device trees for 206compatibility reasons, and would still be required even in new device 207trees that need to be compatible with older software. 208 209Example 1: 210 211 qe_pio_e: gpio-controller@1460 { 212 #gpio-cells = <2>; 213 compatible = "fsl,qe-pario-bank-e", "fsl,qe-pario-bank"; 214 reg = <0x1460 0x18>; 215 gpio-controller; 216 gpio-ranges = <&pinctrl1 0 20 10>, <&pinctrl2 10 50 20>; 217 }; 218 219Here, a single GPIO controller has GPIOs 0..9 routed to pin controller 220pinctrl1's pins 20..29, and GPIOs 10..19 routed to pin controller pinctrl2's 221pins 50..59. 222 223Example 2: 224 225 gpio_pio_i: gpio-controller@14B0 { 226 #gpio-cells = <2>; 227 compatible = "fsl,qe-pario-bank-e", "fsl,qe-pario-bank"; 228 reg = <0x1480 0x18>; 229 gpio-controller; 230 gpio-ranges = <&pinctrl1 0 20 10>, 231 <&pinctrl2 10 0 0>, 232 <&pinctrl1 15 0 10>, 233 <&pinctrl2 25 0 0>; 234 gpio-ranges-group-names = "", 235 "foo", 236 "", 237 "bar"; 238 }; 239 240Here, three GPIO ranges are defined wrt. two pin controllers. pinctrl1 GPIO 241ranges are defined using pin numbers whereas the GPIO ranges wrt. pinctrl2 242are named "foo" and "bar". 243