1Device tree Clock bindings for Renesas EMMA Mobile EV2
2
3This binding uses the common clock binding.
4
5* SMU
6System Management Unit described in user's manual R19UH0037EJ1000_SMU.
7This is not a clock provider, but clocks under SMU depend on it.
8
9Required properties:
10- compatible: Should be "renesas,emev2-smu"
11- reg: Address and Size of SMU registers
12
13* SMU_CLKDIV
14Function block with an input mux and a divider, which corresponds to
15"Serial clock generator" in fig."Clock System Overview" of the manual,
16and "xxx frequency division setting register" (XXXCLKDIV) registers.
17This makes internal (neither input nor output) clock that is provided
18to input of xxxGCLK block.
19
20Required properties:
21- compatible: Should be "renesas,emev2-smu-clkdiv"
22- reg: Byte offset from SMU base and Bit position in the register
23- clocks: Parent clocks. Input clocks as described in clock-bindings.txt
24- #clock-cells: Should be <0>
25
26* SMU_GCLK
27Clock gating node shown as "Clock stop processing block" in the
28fig."Clock System Overview" of the manual.
29Registers are "xxx clock gate control register" (XXXGCLKCTRL).
30
31Required properties:
32- compatible: Should be "renesas,emev2-smu-gclk"
33- reg: Byte offset from SMU base and Bit position in the register
34- clocks: Input clock as described in clock-bindings.txt
35- #clock-cells: Should be <0>
36
37Example of provider:
38
39usia_u0_sclkdiv: usia_u0_sclkdiv {
40	compatible = "renesas,emev2-smu-clkdiv";
41	reg = <0x610 0>;
42	clocks = <&pll3_fo>, <&pll4_fo>, <&pll1_fo>, <&osc1_fo>;
43	#clock-cells = <0>;
44};
45
46usia_u0_sclk: usia_u0_sclk {
47	compatible = "renesas,emev2-smu-gclk";
48	reg = <0x4a0 1>;
49	clocks = <&usia_u0_sclkdiv>;
50	#clock-cells = <0>;
51};
52
53Example of consumer:
54
55uart@e1020000 {
56	compatible = "renesas,em-uart";
57	reg = <0xe1020000 0x38>;
58	interrupts = <0 8 0>;
59	clocks = <&usia_u0_sclk>;
60	clock-names = "sclk";
61};
62
63Example of clock-tree description:
64
65 This describes a clock path in the clock tree
66  c32ki -> pll3_fo -> usia_u0_sclkdiv -> usia_u0_sclk
67
68smu@e0110000 {
69	compatible = "renesas,emev2-smu";
70	reg = <0xe0110000 0x10000>;
71	#address-cells = <2>;
72	#size-cells = <0>;
73
74	c32ki: c32ki {
75		compatible = "fixed-clock";
76		clock-frequency = <32768>;
77		#clock-cells = <0>;
78	};
79	pll3_fo: pll3_fo {
80		compatible = "fixed-factor-clock";
81		clocks = <&c32ki>;
82		clock-div = <1>;
83		clock-mult = <7000>;
84		#clock-cells = <0>;
85	};
86	usia_u0_sclkdiv: usia_u0_sclkdiv {
87		compatible = "renesas,emev2-smu-clkdiv";
88		reg = <0x610 0>;
89		clocks = <&pll3_fo>;
90		#clock-cells = <0>;
91	};
92	usia_u0_sclk: usia_u0_sclk {
93		compatible = "renesas,emev2-smu-gclk";
94		reg = <0x4a0 1>;
95		clocks = <&usia_u0_sclkdiv>;
96		#clock-cells = <0>;
97	};
98};
99